diff options
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r-- | drivers/net/r8169.c | 212 |
1 files changed, 207 insertions, 5 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 5c480750d8fb..caa99cdb5818 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c | |||
@@ -37,6 +37,8 @@ | |||
37 | 37 | ||
38 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" | 38 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
39 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | 39 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" |
40 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" | ||
41 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | ||
40 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" | 42 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
41 | 43 | ||
42 | #ifdef RTL8169_DEBUG | 44 | #ifdef RTL8169_DEBUG |
@@ -128,6 +130,8 @@ enum mac_version { | |||
128 | RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E | 130 | RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E |
129 | RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E | 131 | RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E |
130 | RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP | 132 | RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP |
133 | RTL_GIGA_MAC_VER_32 = 0x20, // 8168E | ||
134 | RTL_GIGA_MAC_VER_33 = 0x21, // 8168E | ||
131 | }; | 135 | }; |
132 | 136 | ||
133 | #define _R(NAME,MAC,MASK) \ | 137 | #define _R(NAME,MAC,MASK) \ |
@@ -168,7 +172,9 @@ static const struct { | |||
168 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E | 172 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E |
169 | _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E | 173 | _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E |
170 | _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E | 174 | _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E |
171 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, 0xff7e1880) // PCI-E | 175 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, 0xff7e1880), // PCI-E |
176 | _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, 0xff7e1880), // PCI-E | ||
177 | _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, 0xff7e1880) // PCI-E | ||
172 | }; | 178 | }; |
173 | #undef _R | 179 | #undef _R |
174 | 180 | ||
@@ -317,7 +323,9 @@ enum rtl8168_registers { | |||
317 | #define OCPAR_FLAG 0x80000000 | 323 | #define OCPAR_FLAG 0x80000000 |
318 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | 324 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 |
319 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | 325 | #define OCPAR_GPHY_READ_CMD 0x0000f060 |
320 | RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */ | 326 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
327 | MISC = 0xf0, /* 8168e only. */ | ||
328 | txpla_rst = (1 << 29) | ||
321 | }; | 329 | }; |
322 | 330 | ||
323 | enum rtl_register_content { | 331 | enum rtl_register_content { |
@@ -395,6 +403,7 @@ enum rtl_register_content { | |||
395 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ | 403 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
396 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | 404 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
397 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | 405 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
406 | spi_en = (1 << 3), | ||
398 | LanWake = (1 << 1), /* LanWake enable/disable */ | 407 | LanWake = (1 << 1), /* LanWake enable/disable */ |
399 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ | 408 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
400 | 409 | ||
@@ -579,6 +588,8 @@ MODULE_LICENSE("GPL"); | |||
579 | MODULE_VERSION(RTL8169_VERSION); | 588 | MODULE_VERSION(RTL8169_VERSION); |
580 | MODULE_FIRMWARE(FIRMWARE_8168D_1); | 589 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
581 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | 590 | MODULE_FIRMWARE(FIRMWARE_8168D_2); |
591 | MODULE_FIRMWARE(FIRMWARE_8168E_1); | ||
592 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | ||
582 | MODULE_FIRMWARE(FIRMWARE_8105E_1); | 593 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
583 | 594 | ||
584 | static int rtl8169_open(struct net_device *dev); | 595 | static int rtl8169_open(struct net_device *dev); |
@@ -1575,6 +1586,11 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, | |||
1575 | u32 val; | 1586 | u32 val; |
1576 | int mac_version; | 1587 | int mac_version; |
1577 | } mac_info[] = { | 1588 | } mac_info[] = { |
1589 | /* 8168E family. */ | ||
1590 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, | ||
1591 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | ||
1592 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | ||
1593 | |||
1578 | /* 8168D family. */ | 1594 | /* 8168D family. */ |
1579 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, | 1595 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
1580 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | 1596 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
@@ -2466,6 +2482,93 @@ static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) | |||
2466 | rtl_patchphy(tp, 0x0d, 1 << 5); | 2482 | rtl_patchphy(tp, 0x0d, 1 << 5); |
2467 | } | 2483 | } |
2468 | 2484 | ||
2485 | static void rtl8168e_hw_phy_config(struct rtl8169_private *tp) | ||
2486 | { | ||
2487 | static const struct phy_reg phy_reg_init[] = { | ||
2488 | /* Enable Delay cap */ | ||
2489 | { 0x1f, 0x0005 }, | ||
2490 | { 0x05, 0x8b80 }, | ||
2491 | { 0x06, 0xc896 }, | ||
2492 | { 0x1f, 0x0000 }, | ||
2493 | |||
2494 | /* Channel estimation fine tune */ | ||
2495 | { 0x1f, 0x0001 }, | ||
2496 | { 0x0b, 0x6c20 }, | ||
2497 | { 0x07, 0x2872 }, | ||
2498 | { 0x1c, 0xefff }, | ||
2499 | { 0x1f, 0x0003 }, | ||
2500 | { 0x14, 0x6420 }, | ||
2501 | { 0x1f, 0x0000 }, | ||
2502 | |||
2503 | /* Update PFM & 10M TX idle timer */ | ||
2504 | { 0x1f, 0x0007 }, | ||
2505 | { 0x1e, 0x002f }, | ||
2506 | { 0x15, 0x1919 }, | ||
2507 | { 0x1f, 0x0000 }, | ||
2508 | |||
2509 | { 0x1f, 0x0007 }, | ||
2510 | { 0x1e, 0x00ac }, | ||
2511 | { 0x18, 0x0006 }, | ||
2512 | { 0x1f, 0x0000 } | ||
2513 | }; | ||
2514 | |||
2515 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | ||
2516 | |||
2517 | /* DCO enable for 10M IDLE Power */ | ||
2518 | rtl_writephy(tp, 0x1f, 0x0007); | ||
2519 | rtl_writephy(tp, 0x1e, 0x0023); | ||
2520 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | ||
2521 | rtl_writephy(tp, 0x1f, 0x0000); | ||
2522 | |||
2523 | /* For impedance matching */ | ||
2524 | rtl_writephy(tp, 0x1f, 0x0002); | ||
2525 | rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); | ||
2526 | rtl_writephy(tp, 0x1F, 0x0000); | ||
2527 | |||
2528 | /* PHY auto speed down */ | ||
2529 | rtl_writephy(tp, 0x1f, 0x0007); | ||
2530 | rtl_writephy(tp, 0x1e, 0x002d); | ||
2531 | rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); | ||
2532 | rtl_writephy(tp, 0x1f, 0x0000); | ||
2533 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | ||
2534 | |||
2535 | rtl_writephy(tp, 0x1f, 0x0005); | ||
2536 | rtl_writephy(tp, 0x05, 0x8b86); | ||
2537 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | ||
2538 | rtl_writephy(tp, 0x1f, 0x0000); | ||
2539 | |||
2540 | rtl_writephy(tp, 0x1f, 0x0005); | ||
2541 | rtl_writephy(tp, 0x05, 0x8b85); | ||
2542 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | ||
2543 | rtl_writephy(tp, 0x1f, 0x0007); | ||
2544 | rtl_writephy(tp, 0x1e, 0x0020); | ||
2545 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); | ||
2546 | rtl_writephy(tp, 0x1f, 0x0006); | ||
2547 | rtl_writephy(tp, 0x00, 0x5a00); | ||
2548 | rtl_writephy(tp, 0x1f, 0x0000); | ||
2549 | rtl_writephy(tp, 0x0d, 0x0007); | ||
2550 | rtl_writephy(tp, 0x0e, 0x003c); | ||
2551 | rtl_writephy(tp, 0x0d, 0x4007); | ||
2552 | rtl_writephy(tp, 0x0e, 0x0000); | ||
2553 | rtl_writephy(tp, 0x0d, 0x0000); | ||
2554 | } | ||
2555 | |||
2556 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) | ||
2557 | { | ||
2558 | if (rtl_apply_firmware(tp, FIRMWARE_8168E_1) < 0) | ||
2559 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); | ||
2560 | |||
2561 | rtl8168e_hw_phy_config(tp); | ||
2562 | } | ||
2563 | |||
2564 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) | ||
2565 | { | ||
2566 | if (rtl_apply_firmware(tp, FIRMWARE_8168E_2) < 0) | ||
2567 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); | ||
2568 | |||
2569 | rtl8168e_hw_phy_config(tp); | ||
2570 | } | ||
2571 | |||
2469 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) | 2572 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2470 | { | 2573 | { |
2471 | static const struct phy_reg phy_reg_init[] = { | 2574 | static const struct phy_reg phy_reg_init[] = { |
@@ -2581,6 +2684,12 @@ static void rtl_hw_phy_config(struct net_device *dev) | |||
2581 | case RTL_GIGA_MAC_VER_30: | 2684 | case RTL_GIGA_MAC_VER_30: |
2582 | rtl8105e_hw_phy_config(tp); | 2685 | rtl8105e_hw_phy_config(tp); |
2583 | break; | 2686 | break; |
2687 | case RTL_GIGA_MAC_VER_32: | ||
2688 | rtl8168e_1_hw_phy_config(tp); | ||
2689 | break; | ||
2690 | case RTL_GIGA_MAC_VER_33: | ||
2691 | rtl8168e_2_hw_phy_config(tp); | ||
2692 | break; | ||
2584 | 2693 | ||
2585 | default: | 2694 | default: |
2586 | break; | 2695 | break; |
@@ -2931,15 +3040,59 @@ static void r810x_pll_power_up(struct rtl8169_private *tp) | |||
2931 | static void r8168_phy_power_up(struct rtl8169_private *tp) | 3040 | static void r8168_phy_power_up(struct rtl8169_private *tp) |
2932 | { | 3041 | { |
2933 | rtl_writephy(tp, 0x1f, 0x0000); | 3042 | rtl_writephy(tp, 0x1f, 0x0000); |
2934 | rtl_writephy(tp, 0x0e, 0x0000); | 3043 | switch (tp->mac_version) { |
3044 | case RTL_GIGA_MAC_VER_11: | ||
3045 | case RTL_GIGA_MAC_VER_12: | ||
3046 | case RTL_GIGA_MAC_VER_17: | ||
3047 | case RTL_GIGA_MAC_VER_18: | ||
3048 | case RTL_GIGA_MAC_VER_19: | ||
3049 | case RTL_GIGA_MAC_VER_20: | ||
3050 | case RTL_GIGA_MAC_VER_21: | ||
3051 | case RTL_GIGA_MAC_VER_22: | ||
3052 | case RTL_GIGA_MAC_VER_23: | ||
3053 | case RTL_GIGA_MAC_VER_24: | ||
3054 | case RTL_GIGA_MAC_VER_25: | ||
3055 | case RTL_GIGA_MAC_VER_26: | ||
3056 | case RTL_GIGA_MAC_VER_27: | ||
3057 | case RTL_GIGA_MAC_VER_28: | ||
3058 | case RTL_GIGA_MAC_VER_31: | ||
3059 | rtl_writephy(tp, 0x0e, 0x0000); | ||
3060 | break; | ||
3061 | default: | ||
3062 | break; | ||
3063 | } | ||
2935 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | 3064 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
2936 | } | 3065 | } |
2937 | 3066 | ||
2938 | static void r8168_phy_power_down(struct rtl8169_private *tp) | 3067 | static void r8168_phy_power_down(struct rtl8169_private *tp) |
2939 | { | 3068 | { |
2940 | rtl_writephy(tp, 0x1f, 0x0000); | 3069 | rtl_writephy(tp, 0x1f, 0x0000); |
2941 | rtl_writephy(tp, 0x0e, 0x0200); | 3070 | switch (tp->mac_version) { |
2942 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | 3071 | case RTL_GIGA_MAC_VER_32: |
3072 | case RTL_GIGA_MAC_VER_33: | ||
3073 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); | ||
3074 | break; | ||
3075 | |||
3076 | case RTL_GIGA_MAC_VER_11: | ||
3077 | case RTL_GIGA_MAC_VER_12: | ||
3078 | case RTL_GIGA_MAC_VER_17: | ||
3079 | case RTL_GIGA_MAC_VER_18: | ||
3080 | case RTL_GIGA_MAC_VER_19: | ||
3081 | case RTL_GIGA_MAC_VER_20: | ||
3082 | case RTL_GIGA_MAC_VER_21: | ||
3083 | case RTL_GIGA_MAC_VER_22: | ||
3084 | case RTL_GIGA_MAC_VER_23: | ||
3085 | case RTL_GIGA_MAC_VER_24: | ||
3086 | case RTL_GIGA_MAC_VER_25: | ||
3087 | case RTL_GIGA_MAC_VER_26: | ||
3088 | case RTL_GIGA_MAC_VER_27: | ||
3089 | case RTL_GIGA_MAC_VER_28: | ||
3090 | case RTL_GIGA_MAC_VER_31: | ||
3091 | rtl_writephy(tp, 0x0e, 0x0200); | ||
3092 | default: | ||
3093 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | ||
3094 | break; | ||
3095 | } | ||
2943 | } | 3096 | } |
2944 | 3097 | ||
2945 | static void r8168_pll_power_down(struct rtl8169_private *tp) | 3098 | static void r8168_pll_power_down(struct rtl8169_private *tp) |
@@ -2959,6 +3112,10 @@ static void r8168_pll_power_down(struct rtl8169_private *tp) | |||
2959 | return; | 3112 | return; |
2960 | } | 3113 | } |
2961 | 3114 | ||
3115 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || | ||
3116 | tp->mac_version == RTL_GIGA_MAC_VER_33) | ||
3117 | rtl_ephy_write(ioaddr, 0x19, 0xff64); | ||
3118 | |||
2962 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { | 3119 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
2963 | rtl_writephy(tp, 0x1f, 0x0000); | 3120 | rtl_writephy(tp, 0x1f, 0x0000); |
2964 | rtl_writephy(tp, MII_BMCR, 0x0000); | 3121 | rtl_writephy(tp, MII_BMCR, 0x0000); |
@@ -2976,6 +3133,8 @@ static void r8168_pll_power_down(struct rtl8169_private *tp) | |||
2976 | case RTL_GIGA_MAC_VER_27: | 3133 | case RTL_GIGA_MAC_VER_27: |
2977 | case RTL_GIGA_MAC_VER_28: | 3134 | case RTL_GIGA_MAC_VER_28: |
2978 | case RTL_GIGA_MAC_VER_31: | 3135 | case RTL_GIGA_MAC_VER_31: |
3136 | case RTL_GIGA_MAC_VER_32: | ||
3137 | case RTL_GIGA_MAC_VER_33: | ||
2979 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); | 3138 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
2980 | break; | 3139 | break; |
2981 | } | 3140 | } |
@@ -2998,6 +3157,8 @@ static void r8168_pll_power_up(struct rtl8169_private *tp) | |||
2998 | case RTL_GIGA_MAC_VER_27: | 3157 | case RTL_GIGA_MAC_VER_27: |
2999 | case RTL_GIGA_MAC_VER_28: | 3158 | case RTL_GIGA_MAC_VER_28: |
3000 | case RTL_GIGA_MAC_VER_31: | 3159 | case RTL_GIGA_MAC_VER_31: |
3160 | case RTL_GIGA_MAC_VER_32: | ||
3161 | case RTL_GIGA_MAC_VER_33: | ||
3001 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); | 3162 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
3002 | break; | 3163 | break; |
3003 | } | 3164 | } |
@@ -3053,6 +3214,8 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) | |||
3053 | case RTL_GIGA_MAC_VER_27: | 3214 | case RTL_GIGA_MAC_VER_27: |
3054 | case RTL_GIGA_MAC_VER_28: | 3215 | case RTL_GIGA_MAC_VER_28: |
3055 | case RTL_GIGA_MAC_VER_31: | 3216 | case RTL_GIGA_MAC_VER_31: |
3217 | case RTL_GIGA_MAC_VER_32: | ||
3218 | case RTL_GIGA_MAC_VER_33: | ||
3056 | ops->down = r8168_pll_power_down; | 3219 | ops->down = r8168_pll_power_down; |
3057 | ops->up = r8168_pll_power_up; | 3220 | ops->up = r8168_pll_power_up; |
3058 | break; | 3221 | break; |
@@ -3855,6 +4018,41 @@ static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) | |||
3855 | rtl_enable_clock_request(pdev); | 4018 | rtl_enable_clock_request(pdev); |
3856 | } | 4019 | } |
3857 | 4020 | ||
4021 | static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev) | ||
4022 | { | ||
4023 | static const struct ephy_info e_info_8168e[] = { | ||
4024 | { 0x00, 0x0200, 0x0100 }, | ||
4025 | { 0x00, 0x0000, 0x0004 }, | ||
4026 | { 0x06, 0x0002, 0x0001 }, | ||
4027 | { 0x06, 0x0000, 0x0030 }, | ||
4028 | { 0x07, 0x0000, 0x2000 }, | ||
4029 | { 0x00, 0x0000, 0x0020 }, | ||
4030 | { 0x03, 0x5800, 0x2000 }, | ||
4031 | { 0x03, 0x0000, 0x0001 }, | ||
4032 | { 0x01, 0x0800, 0x1000 }, | ||
4033 | { 0x07, 0x0000, 0x4000 }, | ||
4034 | { 0x1e, 0x0000, 0x2000 }, | ||
4035 | { 0x19, 0xffff, 0xfe6c }, | ||
4036 | { 0x0a, 0x0000, 0x0040 } | ||
4037 | }; | ||
4038 | |||
4039 | rtl_csi_access_enable_2(ioaddr); | ||
4040 | |||
4041 | rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e)); | ||
4042 | |||
4043 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
4044 | |||
4045 | RTL_W8(MaxTxPacketSize, TxPacketMax); | ||
4046 | |||
4047 | rtl_disable_clock_request(pdev); | ||
4048 | |||
4049 | /* Reset tx FIFO pointer */ | ||
4050 | RTL_W32(MISC, RTL_R32(MISC) | txpla_rst); | ||
4051 | RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst); | ||
4052 | |||
4053 | RTL_W8(Config5, RTL_R8(Config5) & ~spi_en); | ||
4054 | } | ||
4055 | |||
3858 | static void rtl_hw_start_8168(struct net_device *dev) | 4056 | static void rtl_hw_start_8168(struct net_device *dev) |
3859 | { | 4057 | { |
3860 | struct rtl8169_private *tp = netdev_priv(dev); | 4058 | struct rtl8169_private *tp = netdev_priv(dev); |
@@ -3940,6 +4138,10 @@ static void rtl_hw_start_8168(struct net_device *dev) | |||
3940 | rtl_hw_start_8168dp(ioaddr, pdev); | 4138 | rtl_hw_start_8168dp(ioaddr, pdev); |
3941 | break; | 4139 | break; |
3942 | 4140 | ||
4141 | case RTL_GIGA_MAC_VER_32: | ||
4142 | case RTL_GIGA_MAC_VER_33: | ||
4143 | rtl_hw_start_8168e(ioaddr, pdev); | ||
4144 | break; | ||
3943 | 4145 | ||
3944 | default: | 4146 | default: |
3945 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | 4147 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |