1 files changed, 165 insertions, 0 deletions

diff --git a/drivers/net/qlge/qlge_mpi.c b/drivers/net/qlge/qlge_mpi.c
index e2b2286102d4..e2c846f17fc7 100644
--- a/drivers/net/qlge/qlge_mpi.c
+++ b/drivers/net/qlge/qlge_mpi.c
@@ -1,5 +1,54 @@
 #include "qlge.h"
 
+int ql_unpause_mpi_risc(struct ql_adapter *qdev)
+{
+        u32 tmp;
+
+        /* Un-pause the RISC */
+        tmp = ql_read32(qdev, CSR);
+        if (!(tmp & CSR_RP))
+                return -EIO;
+
+        ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE);
+        return 0;
+}
+
+int ql_pause_mpi_risc(struct ql_adapter *qdev)
+{
+        u32 tmp;
+        int count = UDELAY_COUNT;
+
+        /* Pause the RISC */
+        ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE);
+        do {
+                tmp = ql_read32(qdev, CSR);
+                if (tmp & CSR_RP)
+                        break;
+                mdelay(UDELAY_DELAY);
+                count--;
+        } while (count);
+        return (count == 0) ? -ETIMEDOUT : 0;
+}
+
+int ql_hard_reset_mpi_risc(struct ql_adapter *qdev)
+{
+        u32 tmp;
+        int count = UDELAY_COUNT;
+
+        /* Reset the RISC */
+        ql_write32(qdev, CSR, CSR_CMD_SET_RST);
+        do {
+                tmp = ql_read32(qdev, CSR);
+                if (tmp & CSR_RR) {
+                        ql_write32(qdev, CSR, CSR_CMD_CLR_RST);
+                        break;
+                }
+                mdelay(UDELAY_DELAY);
+                count--;
+        } while (count);
+        return (count == 0) ? -ETIMEDOUT : 0;
+}
+
 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 {
         int status;
@@ -45,6 +94,35 @@ int ql_soft_reset_mpi_risc(struct ql_adapter *qdev)
         return status;
 }
 
+/* Determine if we are in charge of the firwmare. If
+ * we are the lower of the 2 NIC pcie functions, or if
+ * we are the higher function and the lower function
+ * is not enabled.
+ */
+int ql_own_firmware(struct ql_adapter *qdev)
+{
+        u32 temp;
+
+        /* If we are the lower of the 2 NIC functions
+         * on the chip the we are responsible for
+         * core dump and firmware reset after an error.
+         */
+        if (qdev->func < qdev->alt_func)
+                return 1;
+
+        /* If we are the higher of the 2 NIC functions
+         * on the chip and the lower function is not
+         * enabled, then we are responsible for
+         * core dump and firmware reset after an error.
+         */
+        temp =  ql_read32(qdev, STS);
+        if (!(temp & (1 << (8 + qdev->alt_func))))
+                return 1;
+
+        return 0;
+
+}
+
 static int ql_get_mb_sts(struct ql_adapter *qdev, struct mbox_params *mbcp)
 {
         int i, status;
@@ -529,6 +607,22 @@ end:
         return status;
 }
 
+int ql_mb_sys_err(struct ql_adapter *qdev)
+{
+        struct mbox_params mbc;
+        struct mbox_params *mbcp = &mbc;
+        int status;
+
+        memset(mbcp, 0, sizeof(struct mbox_params));
+
+        mbcp->in_count = 1;
+        mbcp->out_count = 0;
+
+        mbcp->mbox_in[0] = MB_CMD_MAKE_SYS_ERR;
+
+        status = ql_mailbox_command(qdev, mbcp);
+        return status;
+}
 
 /* Get MPI firmware version. This will be used for
  * driver banner and for ethtool info.
@@ -669,6 +763,63 @@ int ql_mb_set_port_cfg(struct ql_adapter *qdev)
         return status;
 }
 
+int ql_mb_dump_ram(struct ql_adapter *qdev, u64 req_dma, u32 addr,
+        u32 size)
+{
+        int status = 0;
+        struct mbox_params mbc;
+        struct mbox_params *mbcp = &mbc;
+
+        memset(mbcp, 0, sizeof(struct mbox_params));
+
+        mbcp->in_count = 9;
+        mbcp->out_count = 1;
+
+        mbcp->mbox_in[0] = MB_CMD_DUMP_RISC_RAM;
+        mbcp->mbox_in[1] = LSW(addr);
+        mbcp->mbox_in[2] = MSW(req_dma);
+        mbcp->mbox_in[3] = LSW(req_dma);
+        mbcp->mbox_in[4] = MSW(size);
+        mbcp->mbox_in[5] = LSW(size);
+        mbcp->mbox_in[6] = MSW(MSD(req_dma));
+        mbcp->mbox_in[7] = LSW(MSD(req_dma));
+        mbcp->mbox_in[8] = MSW(addr);
+
+
+        status = ql_mailbox_command(qdev, mbcp);
+        if (status)
+                return status;
+
+        if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
+                QPRINTK(qdev, DRV, ERR,
+                        "Failed to dump risc RAM.\n");
+                status = -EIO;
+        }
+        return status;
+}
+
+/* Issue a mailbox command to dump RISC RAM. */
+int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
+                u32 ram_addr, int word_count)
+{
+        int status;
+        char *my_buf;
+        dma_addr_t buf_dma;
+
+        my_buf = pci_alloc_consistent(qdev->pdev, word_count * sizeof(u32),
+                                        &buf_dma);
+        if (!my_buf)
+                return -EIO;
+
+        status = ql_mb_dump_ram(qdev, buf_dma, ram_addr, word_count);
+        if (!status)
+                memcpy(buf, my_buf, word_count * sizeof(u32));
+
+        pci_free_consistent(qdev->pdev, word_count * sizeof(u32), my_buf,
+                                buf_dma);
+        return status;
+}
+
 /* Get link settings and maximum frame size settings
  * for the current port.
  * Most likely will block.
@@ -1143,5 +1294,19 @@ void ql_mpi_reset_work(struct work_struct *work)
         cancel_delayed_work_sync(&qdev->mpi_work);
         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
         cancel_delayed_work_sync(&qdev->mpi_idc_work);
+        /* If we're not the dominant NIC function,
+         * then there is nothing to do.
+         */
+        if (!ql_own_firmware(qdev)) {
+                QPRINTK(qdev, DRV, ERR, "Don't own firmware!\n");
+                return;
+        }
+
+        if (!ql_core_dump(qdev, qdev->mpi_coredump)) {
+                QPRINTK(qdev, DRV, ERR, "Core is dumped!\n");
+                qdev->core_is_dumped = 1;
+                queue_delayed_work(qdev->workqueue,
+                        &qdev->mpi_core_to_log, 5 * HZ);
+        }
         ql_soft_reset_mpi_risc(qdev);
 }