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path: root/drivers/net/qlcnic/qlcnic_hdr.h
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Diffstat (limited to 'drivers/net/qlcnic/qlcnic_hdr.h')
-rw-r--r--drivers/net/qlcnic/qlcnic_hdr.h23
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/net/qlcnic/qlcnic_hdr.h b/drivers/net/qlcnic/qlcnic_hdr.h
index 15fc32070be3..716203e41dc7 100644
--- a/drivers/net/qlcnic/qlcnic_hdr.h
+++ b/drivers/net/qlcnic/qlcnic_hdr.h
@@ -698,7 +698,7 @@ enum {
698#define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0)) 698#define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0))
699#define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8)) 699#define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8))
700#define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac)) 700#define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac))
701#define QLCNIC_CRB_DEV_REF_COUNT (QLCNIC_CAM_RAM(0x138)) 701#define QLCNIC_CRB_DRV_ACTIVE (QLCNIC_CAM_RAM(0x138))
702#define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140)) 702#define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140))
703 703
704#define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144)) 704#define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144))
@@ -718,8 +718,9 @@ enum {
718#define QLCNIC_DEV_FAILED 0x6 718#define QLCNIC_DEV_FAILED 0x6
719#define QLCNIC_DEV_QUISCENT 0x7 719#define QLCNIC_DEV_QUISCENT 0x7
720 720
721#define QLCNIC_DEV_NPAR_NOT_RDY 0 721#define QLCNIC_DEV_NPAR_NON_OPER 0 /* NON Operational */
722#define QLCNIC_DEV_NPAR_RDY 1 722#define QLCNIC_DEV_NPAR_OPER 1 /* NPAR Operational */
723#define QLCNIC_DEV_NPAR_OPER_TIMEO 30 /* Operational time out */
723 724
724#define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) &= (1 << (FN * 4))) 725#define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) &= (1 << (FN * 4)))
725#define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) 726#define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
@@ -744,6 +745,15 @@ enum {
744#define FW_POLL_DELAY (1 * HZ) 745#define FW_POLL_DELAY (1 * HZ)
745#define FW_FAIL_THRESH 2 746#define FW_FAIL_THRESH 2
746 747
748#define QLCNIC_RESET_TIMEOUT_SECS 10
749#define QLCNIC_INIT_TIMEOUT_SECS 30
750#define QLCNIC_RCVPEG_CHECK_RETRY_COUNT 2000
751#define QLCNIC_RCVPEG_CHECK_DELAY 10
752#define QLCNIC_CMDPEG_CHECK_RETRY_COUNT 60
753#define QLCNIC_CMDPEG_CHECK_DELAY 500
754#define QLCNIC_HEARTBEAT_PERIOD_MSECS 200
755#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT 45
756
747#define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 757#define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
748#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 758#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
749 759
@@ -770,6 +780,7 @@ struct qlcnic_legacy_intr_set {
770#define QLCNIC_DRV_OP_MODE 0x1b2170 780#define QLCNIC_DRV_OP_MODE 0x1b2170
771#define QLCNIC_MSIX_BASE 0x132110 781#define QLCNIC_MSIX_BASE 0x132110
772#define QLCNIC_MAX_PCI_FUNC 8 782#define QLCNIC_MAX_PCI_FUNC 8
783#define QLCNIC_MAX_VLAN_FILTERS 64
773 784
774/* PCI function operational mode */ 785/* PCI function operational mode */
775enum { 786enum {
@@ -778,6 +789,12 @@ enum {
778 QLCNIC_NON_PRIV_FUNC = 2 789 QLCNIC_NON_PRIV_FUNC = 2
779}; 790};
780 791
792enum {
793 QLCNIC_PORT_DEFAULTS = 0,
794 QLCNIC_ADD_VLAN = 1,
795 QLCNIC_DEL_VLAN = 2
796};
797
781#define QLC_DEV_DRV_DEFAULT 0x11111111 798#define QLC_DEV_DRV_DEFAULT 0x11111111
782 799
783#define LSB(x) ((uint8_t)(x)) 800#define LSB(x) ((uint8_t)(x))