diff options
Diffstat (limited to 'drivers/net/qlcnic/qlcnic.h')
-rw-r--r-- | drivers/net/qlcnic/qlcnic.h | 176 |
1 files changed, 175 insertions, 1 deletions
diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h index f729363b3fc3..689adea62700 100644 --- a/drivers/net/qlcnic/qlcnic.h +++ b/drivers/net/qlcnic/qlcnic.h | |||
@@ -411,6 +411,29 @@ struct qlcnic_nic_intr_coalesce { | |||
411 | u32 timer_out; | 411 | u32 timer_out; |
412 | }; | 412 | }; |
413 | 413 | ||
414 | struct qlcnic_dump_template_hdr { | ||
415 | __le32 type; | ||
416 | __le32 offset; | ||
417 | __le32 size; | ||
418 | __le32 cap_mask; | ||
419 | __le32 num_entries; | ||
420 | __le32 version; | ||
421 | __le32 timestamp; | ||
422 | __le32 checksum; | ||
423 | __le32 drv_cap_mask; | ||
424 | __le32 sys_info[3]; | ||
425 | __le32 saved_state[16]; | ||
426 | __le32 cap_sizes[8]; | ||
427 | __le32 rsvd[0]; | ||
428 | }; | ||
429 | |||
430 | struct qlcnic_fw_dump { | ||
431 | u8 clr; /* flag to indicate if dump is cleared */ | ||
432 | u32 size; /* total size of the dump */ | ||
433 | void *data; /* dump data area */ | ||
434 | struct qlcnic_dump_template_hdr *tmpl_hdr; | ||
435 | }; | ||
436 | |||
414 | /* | 437 | /* |
415 | * One hardware_context{} per adapter | 438 | * One hardware_context{} per adapter |
416 | * contains interrupt info as well shared hardware info. | 439 | * contains interrupt info as well shared hardware info. |
@@ -431,6 +454,7 @@ struct qlcnic_hardware_context { | |||
431 | u16 board_type; | 454 | u16 board_type; |
432 | 455 | ||
433 | struct qlcnic_nic_intr_coalesce coal; | 456 | struct qlcnic_nic_intr_coalesce coal; |
457 | struct qlcnic_fw_dump fw_dump; | ||
434 | }; | 458 | }; |
435 | 459 | ||
436 | struct qlcnic_adapter_stats { | 460 | struct qlcnic_adapter_stats { |
@@ -574,6 +598,8 @@ struct qlcnic_recv_context { | |||
574 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 | 598 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
575 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a | 599 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
576 | #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E | 600 | #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E |
601 | #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f | ||
602 | #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 | ||
577 | 603 | ||
578 | #define QLCNIC_RCODE_SUCCESS 0 | 604 | #define QLCNIC_RCODE_SUCCESS 0 |
579 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 | 605 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
@@ -1157,6 +1183,152 @@ struct qlcnic_esw_statistics { | |||
1157 | struct __qlcnic_esw_statistics tx; | 1183 | struct __qlcnic_esw_statistics tx; |
1158 | }; | 1184 | }; |
1159 | 1185 | ||
1186 | struct qlcnic_common_entry_hdr { | ||
1187 | __le32 type; | ||
1188 | __le32 offset; | ||
1189 | __le32 cap_size; | ||
1190 | u8 mask; | ||
1191 | u8 rsvd[2]; | ||
1192 | u8 flags; | ||
1193 | } __packed; | ||
1194 | |||
1195 | struct __crb { | ||
1196 | __le32 addr; | ||
1197 | u8 stride; | ||
1198 | u8 rsvd1[3]; | ||
1199 | __le32 data_size; | ||
1200 | __le32 no_ops; | ||
1201 | __le32 rsvd2[4]; | ||
1202 | } __packed; | ||
1203 | |||
1204 | struct __ctrl { | ||
1205 | __le32 addr; | ||
1206 | u8 stride; | ||
1207 | u8 index_a; | ||
1208 | __le16 timeout; | ||
1209 | __le32 data_size; | ||
1210 | __le32 no_ops; | ||
1211 | u8 opcode; | ||
1212 | u8 index_v; | ||
1213 | u8 shl_val; | ||
1214 | u8 shr_val; | ||
1215 | __le32 val1; | ||
1216 | __le32 val2; | ||
1217 | __le32 val3; | ||
1218 | } __packed; | ||
1219 | |||
1220 | struct __cache { | ||
1221 | __le32 addr; | ||
1222 | u8 stride; | ||
1223 | u8 rsvd; | ||
1224 | __le16 init_tag_val; | ||
1225 | __le32 size; | ||
1226 | __le32 no_ops; | ||
1227 | __le32 ctrl_addr; | ||
1228 | __le32 ctrl_val; | ||
1229 | __le32 read_addr; | ||
1230 | u8 read_addr_stride; | ||
1231 | u8 read_addr_num; | ||
1232 | u8 rsvd1[2]; | ||
1233 | } __packed; | ||
1234 | |||
1235 | struct __ocm { | ||
1236 | u8 rsvd[8]; | ||
1237 | __le32 size; | ||
1238 | __le32 no_ops; | ||
1239 | u8 rsvd1[8]; | ||
1240 | __le32 read_addr; | ||
1241 | __le32 read_addr_stride; | ||
1242 | } __packed; | ||
1243 | |||
1244 | struct __mem { | ||
1245 | u8 rsvd[24]; | ||
1246 | __le32 addr; | ||
1247 | __le32 size; | ||
1248 | } __packed; | ||
1249 | |||
1250 | struct __mux { | ||
1251 | __le32 addr; | ||
1252 | u8 rsvd[4]; | ||
1253 | __le32 size; | ||
1254 | __le32 no_ops; | ||
1255 | __le32 val; | ||
1256 | __le32 val_stride; | ||
1257 | __le32 read_addr; | ||
1258 | u8 rsvd2[4]; | ||
1259 | } __packed; | ||
1260 | |||
1261 | struct __queue { | ||
1262 | __le32 sel_addr; | ||
1263 | __le16 stride; | ||
1264 | u8 rsvd[2]; | ||
1265 | __le32 size; | ||
1266 | __le32 no_ops; | ||
1267 | u8 rsvd2[8]; | ||
1268 | __le32 read_addr; | ||
1269 | u8 read_addr_stride; | ||
1270 | u8 read_addr_cnt; | ||
1271 | u8 rsvd3[2]; | ||
1272 | } __packed; | ||
1273 | |||
1274 | struct qlcnic_dump_entry { | ||
1275 | struct qlcnic_common_entry_hdr hdr; | ||
1276 | union { | ||
1277 | struct __crb crb; | ||
1278 | struct __cache cache; | ||
1279 | struct __ocm ocm; | ||
1280 | struct __mem mem; | ||
1281 | struct __mux mux; | ||
1282 | struct __queue que; | ||
1283 | struct __ctrl ctrl; | ||
1284 | } region; | ||
1285 | } __packed; | ||
1286 | |||
1287 | enum op_codes { | ||
1288 | QLCNIC_DUMP_NOP = 0, | ||
1289 | QLCNIC_DUMP_READ_CRB = 1, | ||
1290 | QLCNIC_DUMP_READ_MUX = 2, | ||
1291 | QLCNIC_DUMP_QUEUE = 3, | ||
1292 | QLCNIC_DUMP_BRD_CONFIG = 4, | ||
1293 | QLCNIC_DUMP_READ_OCM = 6, | ||
1294 | QLCNIC_DUMP_PEG_REG = 7, | ||
1295 | QLCNIC_DUMP_L1_DTAG = 8, | ||
1296 | QLCNIC_DUMP_L1_ITAG = 9, | ||
1297 | QLCNIC_DUMP_L1_DATA = 11, | ||
1298 | QLCNIC_DUMP_L1_INST = 12, | ||
1299 | QLCNIC_DUMP_L2_DTAG = 21, | ||
1300 | QLCNIC_DUMP_L2_ITAG = 22, | ||
1301 | QLCNIC_DUMP_L2_DATA = 23, | ||
1302 | QLCNIC_DUMP_L2_INST = 24, | ||
1303 | QLCNIC_DUMP_READ_ROM = 71, | ||
1304 | QLCNIC_DUMP_READ_MEM = 72, | ||
1305 | QLCNIC_DUMP_READ_CTRL = 98, | ||
1306 | QLCNIC_DUMP_TLHDR = 99, | ||
1307 | QLCNIC_DUMP_RDEND = 255 | ||
1308 | }; | ||
1309 | |||
1310 | #define QLCNIC_DUMP_WCRB BIT_0 | ||
1311 | #define QLCNIC_DUMP_RWCRB BIT_1 | ||
1312 | #define QLCNIC_DUMP_ANDCRB BIT_2 | ||
1313 | #define QLCNIC_DUMP_ORCRB BIT_3 | ||
1314 | #define QLCNIC_DUMP_POLLCRB BIT_4 | ||
1315 | #define QLCNIC_DUMP_RD_SAVE BIT_5 | ||
1316 | #define QLCNIC_DUMP_WRT_SAVED BIT_6 | ||
1317 | #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7 | ||
1318 | #define QLCNIC_DUMP_SKIP BIT_7 | ||
1319 | |||
1320 | #define QLCNIC_DUMP_MASK_MIN 3 | ||
1321 | #define QLCNIC_DUMP_MASK_DEF 0x0f | ||
1322 | #define QLCNIC_DUMP_MASK_MAX 0xff | ||
1323 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed | ||
1324 | |||
1325 | struct qlcnic_dump_operations { | ||
1326 | enum op_codes opcode; | ||
1327 | u32 (*handler)(struct qlcnic_adapter *, | ||
1328 | struct qlcnic_dump_entry *, u32 *); | ||
1329 | }; | ||
1330 | |||
1331 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); | ||
1160 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); | 1332 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
1161 | 1333 | ||
1162 | u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); | 1334 | u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); |
@@ -1203,6 +1375,7 @@ int qlcnic_wol_supported(struct qlcnic_adapter *adapter); | |||
1203 | int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); | 1375 | int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); |
1204 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); | 1376 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1205 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | 1377 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); |
1378 | int qlcnic_dump_fw(struct qlcnic_adapter *); | ||
1206 | 1379 | ||
1207 | /* Functions from qlcnic_init.c */ | 1380 | /* Functions from qlcnic_init.c */ |
1208 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); | 1381 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
@@ -1213,7 +1386,7 @@ int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |||
1213 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); | 1386 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
1214 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); | 1387 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
1215 | 1388 | ||
1216 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp); | 1389 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
1217 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, | 1390 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1218 | u8 *bytes, size_t size); | 1391 | u8 *bytes, size_t size); |
1219 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | 1392 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); |
@@ -1265,6 +1438,7 @@ int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |||
1265 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); | 1438 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
1266 | int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val); | 1439 | int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val); |
1267 | int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data); | 1440 | int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data); |
1441 | void qlcnic_dev_request_reset(struct qlcnic_adapter *); | ||
1268 | 1442 | ||
1269 | /* Management functions */ | 1443 | /* Management functions */ |
1270 | int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); | 1444 | int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); |