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-rwxr-xr-x[-rw-r--r--]drivers/net/qla3xxx.h88
1 files changed, 78 insertions, 10 deletions
diff --git a/drivers/net/qla3xxx.h b/drivers/net/qla3xxx.h
index ea94de7fd071..b2d76ea68827 100644..100755
--- a/drivers/net/qla3xxx.h
+++ b/drivers/net/qla3xxx.h
@@ -21,7 +21,9 @@
21 21
22#define OPCODE_UPDATE_NCB_IOCB 0xF0 22#define OPCODE_UPDATE_NCB_IOCB 0xF0
23#define OPCODE_IB_MAC_IOCB 0xF9 23#define OPCODE_IB_MAC_IOCB 0xF9
24#define OPCODE_IB_3032_MAC_IOCB 0x09
24#define OPCODE_IB_IP_IOCB 0xFA 25#define OPCODE_IB_IP_IOCB 0xFA
26#define OPCODE_IB_3032_IP_IOCB 0x0A
25#define OPCODE_IB_TCP_IOCB 0xFB 27#define OPCODE_IB_TCP_IOCB 0xFB
26#define OPCODE_DUMP_PROTO_IOCB 0xFE 28#define OPCODE_DUMP_PROTO_IOCB 0xFE
27#define OPCODE_BUFFER_ALERT_IOCB 0xFB 29#define OPCODE_BUFFER_ALERT_IOCB 0xFB
@@ -37,18 +39,23 @@
37struct ob_mac_iocb_req { 39struct ob_mac_iocb_req {
38 u8 opcode; 40 u8 opcode;
39 u8 flags; 41 u8 flags;
40#define OB_MAC_IOCB_REQ_MA 0xC0 42#define OB_MAC_IOCB_REQ_MA 0xe0
41#define OB_MAC_IOCB_REQ_F 0x20 43#define OB_MAC_IOCB_REQ_F 0x10
42#define OB_MAC_IOCB_REQ_X 0x10 44#define OB_MAC_IOCB_REQ_X 0x08
43#define OB_MAC_IOCB_REQ_D 0x02 45#define OB_MAC_IOCB_REQ_D 0x02
44#define OB_MAC_IOCB_REQ_I 0x01 46#define OB_MAC_IOCB_REQ_I 0x01
45 __le16 reserved0; 47 u8 flags1;
48#define OB_3032MAC_IOCB_REQ_IC 0x04
49#define OB_3032MAC_IOCB_REQ_TC 0x02
50#define OB_3032MAC_IOCB_REQ_UC 0x01
51 u8 reserved0;
46 52
47 __le32 transaction_id; 53 __le32 transaction_id;
48 __le16 data_len; 54 __le16 data_len;
49 __le16 reserved1; 55 u8 ip_hdr_off;
56 u8 ip_hdr_len;
57 __le32 reserved1;
50 __le32 reserved2; 58 __le32 reserved2;
51 __le32 reserved3;
52 __le32 buf_addr0_low; 59 __le32 buf_addr0_low;
53 __le32 buf_addr0_high; 60 __le32 buf_addr0_high;
54 __le32 buf_0_len; 61 __le32 buf_0_len;
@@ -58,8 +65,8 @@ struct ob_mac_iocb_req {
58 __le32 buf_addr2_low; 65 __le32 buf_addr2_low;
59 __le32 buf_addr2_high; 66 __le32 buf_addr2_high;
60 __le32 buf_2_len; 67 __le32 buf_2_len;
68 __le32 reserved3;
61 __le32 reserved4; 69 __le32 reserved4;
62 __le32 reserved5;
63}; 70};
64/* 71/*
65 * The following constants define control bits for buffer 72 * The following constants define control bits for buffer
@@ -74,6 +81,7 @@ struct ob_mac_iocb_rsp {
74 u8 opcode; 81 u8 opcode;
75 u8 flags; 82 u8 flags;
76#define OB_MAC_IOCB_RSP_P 0x08 83#define OB_MAC_IOCB_RSP_P 0x08
84#define OB_MAC_IOCB_RSP_L 0x04
77#define OB_MAC_IOCB_RSP_S 0x02 85#define OB_MAC_IOCB_RSP_S 0x02
78#define OB_MAC_IOCB_RSP_I 0x01 86#define OB_MAC_IOCB_RSP_I 0x01
79 87
@@ -85,6 +93,7 @@ struct ob_mac_iocb_rsp {
85 93
86struct ib_mac_iocb_rsp { 94struct ib_mac_iocb_rsp {
87 u8 opcode; 95 u8 opcode;
96#define IB_MAC_IOCB_RSP_V 0x80
88 u8 flags; 97 u8 flags;
89#define IB_MAC_IOCB_RSP_S 0x80 98#define IB_MAC_IOCB_RSP_S 0x80
90#define IB_MAC_IOCB_RSP_H1 0x40 99#define IB_MAC_IOCB_RSP_H1 0x40
@@ -138,6 +147,7 @@ struct ob_ip_iocb_req {
138struct ob_ip_iocb_rsp { 147struct ob_ip_iocb_rsp {
139 u8 opcode; 148 u8 opcode;
140 u8 flags; 149 u8 flags;
150#define OB_MAC_IOCB_RSP_H 0x10
141#define OB_MAC_IOCB_RSP_E 0x08 151#define OB_MAC_IOCB_RSP_E 0x08
142#define OB_MAC_IOCB_RSP_L 0x04 152#define OB_MAC_IOCB_RSP_L 0x04
143#define OB_MAC_IOCB_RSP_S 0x02 153#define OB_MAC_IOCB_RSP_S 0x02
@@ -220,6 +230,10 @@ struct ob_tcp_iocb_rsp {
220 230
221struct ib_ip_iocb_rsp { 231struct ib_ip_iocb_rsp {
222 u8 opcode; 232 u8 opcode;
233#define IB_IP_IOCB_RSP_3032_V 0x80
234#define IB_IP_IOCB_RSP_3032_O 0x40
235#define IB_IP_IOCB_RSP_3032_I 0x20
236#define IB_IP_IOCB_RSP_3032_R 0x10
223 u8 flags; 237 u8 flags;
224#define IB_IP_IOCB_RSP_S 0x80 238#define IB_IP_IOCB_RSP_S 0x80
225#define IB_IP_IOCB_RSP_H1 0x40 239#define IB_IP_IOCB_RSP_H1 0x40
@@ -230,6 +244,12 @@ struct ib_ip_iocb_rsp {
230 244
231 __le16 length; 245 __le16 length;
232 __le16 checksum; 246 __le16 checksum;
247#define IB_IP_IOCB_RSP_3032_ICE 0x01
248#define IB_IP_IOCB_RSP_3032_CE 0x02
249#define IB_IP_IOCB_RSP_3032_NUC 0x04
250#define IB_IP_IOCB_RSP_3032_UDP 0x08
251#define IB_IP_IOCB_RSP_3032_TCP 0x10
252#define IB_IP_IOCB_RSP_3032_IPE 0x20
233 __le16 reserved; 253 __le16 reserved;
234#define IB_IP_IOCB_RSP_R 0x01 254#define IB_IP_IOCB_RSP_R 0x01
235 __le32 ial_low; 255 __le32 ial_low;
@@ -524,6 +544,21 @@ enum {
524 IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005, 544 IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
525 IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006, 545 IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
526 IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007, 546 IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
547 IP_ADDR_INDEX_REG_6 = 0x0008,
548 IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
549 IP_ADDR_INDEX_REG_E = 0x0040,
550};
551enum {
552 QL3032_PORT_CONTROL_DS = 0x0001,
553 QL3032_PORT_CONTROL_HH = 0x0002,
554 QL3032_PORT_CONTROL_EIv6 = 0x0004,
555 QL3032_PORT_CONTROL_EIv4 = 0x0008,
556 QL3032_PORT_CONTROL_ET = 0x0010,
557 QL3032_PORT_CONTROL_EF = 0x0020,
558 QL3032_PORT_CONTROL_DRM = 0x0040,
559 QL3032_PORT_CONTROL_RLB = 0x0080,
560 QL3032_PORT_CONTROL_RCB = 0x0100,
561 QL3032_PORT_CONTROL_KIE = 0x0200,
527}; 562};
528 563
529enum { 564enum {
@@ -657,7 +692,8 @@ struct ql3xxx_port_registers {
657 u32 internalRamWDataReg; 692 u32 internalRamWDataReg;
658 u32 reclaimedBufferAddrRegLow; 693 u32 reclaimedBufferAddrRegLow;
659 u32 reclaimedBufferAddrRegHigh; 694 u32 reclaimedBufferAddrRegHigh;
660 u32 reserved[2]; 695 u32 tcpConfiguration;
696 u32 functionControl;
661 u32 fpgaRevID; 697 u32 fpgaRevID;
662 u32 localRamAddr; 698 u32 localRamAddr;
663 u32 localRamDataAutoIncr; 699 u32 localRamDataAutoIncr;
@@ -963,6 +999,7 @@ struct eeprom_data {
963 999
964#define QL3XXX_VENDOR_ID 0x1077 1000#define QL3XXX_VENDOR_ID 0x1077
965#define QL3022_DEVICE_ID 0x3022 1001#define QL3022_DEVICE_ID 0x3022
1002#define QL3032_DEVICE_ID 0x3032
966 1003
967/* MTU & Frame Size stuff */ 1004/* MTU & Frame Size stuff */
968#define NORMAL_MTU_SIZE ETH_DATA_LEN 1005#define NORMAL_MTU_SIZE ETH_DATA_LEN
@@ -1038,11 +1075,41 @@ struct ql_rcv_buf_cb {
1038 int index; 1075 int index;
1039}; 1076};
1040 1077
1078/*
1079 * Original IOCB has 3 sg entries:
1080 * first points to skb-data area
1081 * second points to first frag
1082 * third points to next oal.
1083 * OAL has 5 entries:
1084 * 1 thru 4 point to frags
1085 * fifth points to next oal.
1086 */
1087#define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1088
1089struct oal_entry {
1090 u32 dma_lo;
1091 u32 dma_hi;
1092 u32 len;
1093#define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
1094#define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
1095 u32 reserved;
1096};
1097
1098struct oal {
1099 struct oal_entry oal_entry[5];
1100};
1101
1102struct map_list {
1103 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1104 DECLARE_PCI_UNMAP_LEN(maplen);
1105};
1106
1041struct ql_tx_buf_cb { 1107struct ql_tx_buf_cb {
1042 struct sk_buff *skb; 1108 struct sk_buff *skb;
1043 struct ob_mac_iocb_req *queue_entry ; 1109 struct ob_mac_iocb_req *queue_entry ;
1044 DECLARE_PCI_UNMAP_ADDR(mapaddr); 1110 int seg_count;
1045 DECLARE_PCI_UNMAP_LEN(maplen); 1111 struct oal *oal;
1112 struct map_list map[MAX_SKB_FRAGS+1];
1046}; 1113};
1047 1114
1048/* definitions for type field */ 1115/* definitions for type field */
@@ -1189,6 +1256,7 @@ struct ql3_adapter {
1189 struct delayed_work reset_work; 1256 struct delayed_work reset_work;
1190 struct delayed_work tx_timeout_work; 1257 struct delayed_work tx_timeout_work;
1191 u32 max_frame_size; 1258 u32 max_frame_size;
1259 u32 device_id;
1192}; 1260};
1193 1261
1194#endif /* _QLA3XXX_H_ */ 1262#endif /* _QLA3XXX_H_ */