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path: root/drivers/net/ps3_gelic_net.h
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Diffstat (limited to 'drivers/net/ps3_gelic_net.h')
-rw-r--r--drivers/net/ps3_gelic_net.h415
1 files changed, 270 insertions, 145 deletions
diff --git a/drivers/net/ps3_gelic_net.h b/drivers/net/ps3_gelic_net.h
index 968560269a3b..1d39d06797e4 100644
--- a/drivers/net/ps3_gelic_net.h
+++ b/drivers/net/ps3_gelic_net.h
@@ -35,198 +35,323 @@
35#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN 35#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN
36#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN 36#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN
37#define GELIC_NET_RXBUF_ALIGN 128 37#define GELIC_NET_RXBUF_ALIGN 128
38#define GELIC_NET_RX_CSUM_DEFAULT 1 /* hw chksum */ 38#define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */
39#define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ 39#define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
40#define GELIC_NET_NAPI_WEIGHT (GELIC_NET_RX_DESCRIPTORS) 40#define GELIC_NET_NAPI_WEIGHT (GELIC_NET_RX_DESCRIPTORS)
41#define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL 41#define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
42#define GELIC_NET_VLAN_POS (VLAN_ETH_ALEN * 2) 42
43#define GELIC_NET_VLAN_MAX 4
44#define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */ 43#define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
45 44
46enum gelic_net_int0_status { 45/* virtual interrupt status register bits */
47 GELIC_NET_GDTDCEINT = 24, 46 /* INT1 */
48 GELIC_NET_GRFANMINT = 28, 47#define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
49}; 48#define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
49#define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
50#define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
51#define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
52#define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
53#define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
54#define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
55#define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
56#define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
57#define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
58#define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
59#define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
60#define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L
61#define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L
62 /* INT 0 */
63#define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
64#define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
65#define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
66#define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
67#define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
68#define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
69#define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
70
71/* initial interrupt mask */
72#define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
50 73
51/* GHIINT1STS bits */ 74#define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
52enum gelic_net_int1_status { 75 GELIC_CARD_NUMBER_OF_RX_FRAME)
53 GELIC_NET_GDADCEINT = 14, 76
77 /* RX descriptor data_status bits */
78enum gelic_descr_rx_status {
79 GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
80 GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
81 GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
82 GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
83 GELIC_DESCR_RXWTPKT = 0x00C00000, /*
84 * wakeup trigger packet
85 * 01: Magic Packet (TM)
86 * 10: ARP packet
87 * 11: Multicast MAC addr
88 */
89 GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
90 /* bit 20..16 reserved */
91 GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
92 /* bit 7..0 reserved */
54}; 93};
55 94
56/* interrupt mask */ 95#define GELIC_DESCR_DATA_STATUS_CHK_MASK \
57#define GELIC_NET_TXINT (1L << (GELIC_NET_GDTDCEINT + 32)) 96 (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
58 97
59#define GELIC_NET_RXINT0 (1L << (GELIC_NET_GRFANMINT + 32)) 98 /* TX descriptor data_status bits */
60#define GELIC_NET_RXINT1 (1L << GELIC_NET_GDADCEINT) 99enum gelic_descr_tx_status {
61#define GELIC_NET_RXINT (GELIC_NET_RXINT0 | GELIC_NET_RXINT1) 100 GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
101 * descriptor was end of
102 * a tx frame
103 */
104};
62 105
63 /* RX descriptor data_status bits */ 106/* RX descriptor data error bits */
64#define GELIC_NET_RXDMADU 0x80000000 /* destination MAC addr unknown */ 107enum gelic_descr_rx_error {
65#define GELIC_NET_RXLSTFBF 0x40000000 /* last frame buffer */ 108 /* bit 31 reserved */
66#define GELIC_NET_RXIPCHK 0x20000000 /* IP checksum performed */ 109 GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
67#define GELIC_NET_RXTCPCHK 0x10000000 /* TCP/UDP checksup performed */ 110 GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
68#define GELIC_NET_RXIPSPKT 0x08000000 /* IPsec packet */ 111 GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
69#define GELIC_NET_RXIPSAHPRT 0x04000000 /* IPsec AH protocol performed */ 112 GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
70#define GELIC_NET_RXIPSESPPRT 0x02000000 /* IPsec ESP protocol performed */ 113 GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
71#define GELIC_NET_RXSESPAH 0x01000000 /* 114 GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
72 * IPsec ESP protocol auth 115 GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
73 * performed 116 /* bit 18 reserved */
74 */ 117 GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
75 118 GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
76#define GELIC_NET_RXWTPKT 0x00C00000 /* 119 * error */
77 * wakeup trigger packet 120 GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extention error */
78 * 01: Magic Packet (TM) 121 GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
79 * 10: ARP packet 122 /* bit 13..0 reserved */
80 * 11: Multicast MAC addr 123};
81 */ 124#define GELIC_DESCR_DATA_ERROR_CHK_MASK \
82#define GELIC_NET_RXVLNPKT 0x00200000 /* VLAN packet */ 125 (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
83/* bit 20..16 reserved */
84#define GELIC_NET_RXRRECNUM 0x0000ff00 /* reception receipt number */
85#define GELIC_NET_RXRRECNUM_SHIFT 8
86/* bit 7..0 reserved */
87
88#define GELIC_NET_TXDESC_TAIL 0
89#define GELIC_NET_DATA_STATUS_CHK_MASK (GELIC_NET_RXIPCHK | GELIC_NET_RXTCPCHK)
90
91/* RX descriptor data_error bits */
92/* bit 31 reserved */
93#define GELIC_NET_RXALNERR 0x40000000 /* alignement error 10/100M */
94#define GELIC_NET_RXOVERERR 0x20000000 /* oversize error */
95#define GELIC_NET_RXRNTERR 0x10000000 /* Runt error */
96#define GELIC_NET_RXIPCHKERR 0x08000000 /* IP checksum error */
97#define GELIC_NET_RXTCPCHKERR 0x04000000 /* TCP/UDP checksum error */
98#define GELIC_NET_RXUMCHSP 0x02000000 /* unmatched sp on sp */
99#define GELIC_NET_RXUMCHSPI 0x01000000 /* unmatched SPI on SAD */
100#define GELIC_NET_RXUMCHSAD 0x00800000 /* unmatched SAD */
101#define GELIC_NET_RXIPSAHERR 0x00400000 /* auth error on AH protocol
102 * processing */
103#define GELIC_NET_RXIPSESPAHERR 0x00200000 /* auth error on ESP protocol
104 * processing */
105#define GELIC_NET_RXDRPPKT 0x00100000 /* drop packet */
106#define GELIC_NET_RXIPFMTERR 0x00080000 /* IP packet format error */
107/* bit 18 reserved */
108#define GELIC_NET_RXDATAERR 0x00020000 /* IP packet format error */
109#define GELIC_NET_RXCALERR 0x00010000 /* cariier extension length
110 * error */
111#define GELIC_NET_RXCREXERR 0x00008000 /* carrier extention error */
112#define GELIC_NET_RXMLTCST 0x00004000 /* multicast address frame */
113/* bit 13..0 reserved */
114#define GELIC_NET_DATA_ERROR_CHK_MASK \
115 (GELIC_NET_RXIPCHKERR | GELIC_NET_RXTCPCHKERR)
116 126
127/* DMA command and status (RX and TX)*/
128enum gelic_descr_dma_status {
129 GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
130 GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
131 GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
132 GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
133 GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
134 GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
135 GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
136 GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
137};
138
139#define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
117 140
118/* tx descriptor command and status */ 141/* tx descriptor command and status */
119#define GELIC_NET_DMAC_CMDSTAT_NOCS 0xa0080000 /* middle of frame */ 142enum gelic_descr_tx_dma_status {
120#define GELIC_NET_DMAC_CMDSTAT_TCPCS 0xa00a0000 143 /* [19] */
121#define GELIC_NET_DMAC_CMDSTAT_UDPCS 0xa00b0000 144 GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
122#define GELIC_NET_DMAC_CMDSTAT_END_FRAME 0x00040000 /* end of frame */ 145 /* [18] */
123 146 GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
124#define GELIC_NET_DMAC_CMDSTAT_RXDCEIS 0x00000002 /* descriptor chain end 147 * the packet
125 * interrupt status */ 148 */
126 149 /* [17..16] */
127#define GELIC_NET_DMAC_CMDSTAT_CHAIN_END 0x00000002 /* RXDCEIS:DMA stopped */ 150 GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
128#define GELIC_NET_DESCR_IND_PROC_SHIFT 28 151 GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
129#define GELIC_NET_DESCR_IND_PROC_MASKO 0x0fffffff 152 GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
130 153
131 154 /* [1] */
132enum gelic_net_descr_status { 155 GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
133 GELIC_NET_DESCR_COMPLETE = 0x00, /* used in tx */ 156 * due to chain end
134 GELIC_NET_DESCR_BUFFER_FULL = 0x00, /* used in rx */ 157 */
135 GELIC_NET_DESCR_RESPONSE_ERROR = 0x01, /* used in rx and tx */
136 GELIC_NET_DESCR_PROTECTION_ERROR = 0x02, /* used in rx and tx */
137 GELIC_NET_DESCR_FRAME_END = 0x04, /* used in rx */
138 GELIC_NET_DESCR_FORCE_END = 0x05, /* used in rx and tx */
139 GELIC_NET_DESCR_CARDOWNED = 0x0a, /* used in rx and tx */
140 GELIC_NET_DESCR_NOT_IN_USE = 0x0b /* any other value */
141}; 158};
159
160#define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
161 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
162 GELIC_DESCR_TX_DMA_NO_CHKSUM)
163
164#define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
165 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
166 GELIC_DESCR_TX_DMA_TCP_CHKSUM)
167
168#define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
169 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
170 GELIC_DESCR_TX_DMA_UDP_CHKSUM)
171
172enum gelic_descr_rx_dma_status {
173 /* [ 1 ] */
174 GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
175 * due to chain end
176 */
177};
178
142/* for lv1_net_control */ 179/* for lv1_net_control */
143#define GELIC_NET_GET_MAC_ADDRESS 0x0000000000000001 180enum gelic_lv1_net_control_code {
144#define GELIC_NET_GET_ETH_PORT_STATUS 0x0000000000000002 181 GELIC_LV1_GET_MAC_ADDRESS = 1,
145#define GELIC_NET_SET_NEGOTIATION_MODE 0x0000000000000003 182 GELIC_LV1_GET_ETH_PORT_STATUS = 2,
146#define GELIC_NET_GET_VLAN_ID 0x0000000000000004 183 GELIC_LV1_SET_NEGOTIATION_MODE = 3,
147 184 GELIC_LV1_GET_VLAN_ID = 4,
148#define GELIC_NET_LINK_UP 0x0000000000000001 185 GELIC_LV1_GET_CHANNEL = 6,
149#define GELIC_NET_FULL_DUPLEX 0x0000000000000002 186 GELIC_LV1_POST_WLAN_CMD = 9,
150#define GELIC_NET_AUTO_NEG 0x0000000000000004 187 GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
151#define GELIC_NET_SPEED_10 0x0000000000000010 188 GELIC_LV1_GET_WLAN_EVENT = 11
152#define GELIC_NET_SPEED_100 0x0000000000000020 189};
153#define GELIC_NET_SPEED_1000 0x0000000000000040 190
154 191/* status returened from GET_ETH_PORT_STATUS */
155#define GELIC_NET_VLAN_ALL 0x0000000000000001 192enum gelic_lv1_ether_port_status {
156#define GELIC_NET_VLAN_WIRED 0x0000000000000002 193 GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
157#define GELIC_NET_VLAN_WIRELESS 0x0000000000000003 194 GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
158#define GELIC_NET_VLAN_PSP 0x0000000000000004 195 GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
159#define GELIC_NET_VLAN_PORT0 0x0000000000000010 196
160#define GELIC_NET_VLAN_PORT1 0x0000000000000011 197 GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
161#define GELIC_NET_VLAN_PORT2 0x0000000000000012 198 GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
162#define GELIC_NET_VLAN_DAEMON_CLIENT_BSS 0x0000000000000013 199 GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
163#define GELIC_NET_VLAN_LIBERO_CLIENT_BSS 0x0000000000000014 200 GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L
164#define GELIC_NET_VLAN_NO_ENTRY -6 201};
165 202
166#define GELIC_NET_PORT 2 /* for port status */ 203enum gelic_lv1_vlan_index {
204 /* for outgoing packets */
205 GELIC_LV1_VLAN_TX_ETHERNET = 0x0000000000000002L,
206 GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
207 /* for incoming packets */
208 GELIC_LV1_VLAN_RX_ETHERNET = 0x0000000000000012L,
209 GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L
210};
167 211
168/* size of hardware part of gelic descriptor */ 212/* size of hardware part of gelic descriptor */
169#define GELIC_NET_DESCR_SIZE (32) 213#define GELIC_DESCR_SIZE (32)
170struct gelic_net_descr { 214
215enum gelic_port_type {
216 GELIC_PORT_ETHERNET = 0,
217 GELIC_PORT_WIRELESS = 1,
218 GELIC_PORT_MAX
219};
220
221struct gelic_descr {
171 /* as defined by the hardware */ 222 /* as defined by the hardware */
172 u32 buf_addr; 223 __be32 buf_addr;
173 u32 buf_size; 224 __be32 buf_size;
174 u32 next_descr_addr; 225 __be32 next_descr_addr;
175 u32 dmac_cmd_status; 226 __be32 dmac_cmd_status;
176 u32 result_size; 227 __be32 result_size;
177 u32 valid_size; /* all zeroes for tx */ 228 __be32 valid_size; /* all zeroes for tx */
178 u32 data_status; 229 __be32 data_status;
179 u32 data_error; /* all zeroes for tx */ 230 __be32 data_error; /* all zeroes for tx */
180 231
181 /* used in the driver */ 232 /* used in the driver */
182 struct sk_buff *skb; 233 struct sk_buff *skb;
183 dma_addr_t bus_addr; 234 dma_addr_t bus_addr;
184 struct gelic_net_descr *next; 235 struct gelic_descr *next;
185 struct gelic_net_descr *prev; 236 struct gelic_descr *prev;
186 struct vlan_ethhdr vlan;
187} __attribute__((aligned(32))); 237} __attribute__((aligned(32)));
188 238
189struct gelic_net_descr_chain { 239struct gelic_descr_chain {
190 /* we walk from tail to head */ 240 /* we walk from tail to head */
191 struct gelic_net_descr *head; 241 struct gelic_descr *head;
192 struct gelic_net_descr *tail; 242 struct gelic_descr *tail;
193}; 243};
194 244
195struct gelic_net_card { 245struct gelic_vlan_id {
196 struct net_device *netdev; 246 u16 tx;
247 u16 rx;
248};
249
250struct gelic_card {
197 struct napi_struct napi; 251 struct napi_struct napi;
252 struct net_device *netdev[GELIC_PORT_MAX];
198 /* 253 /*
199 * hypervisor requires irq_status should be 254 * hypervisor requires irq_status should be
200 * 8 bytes aligned, but u64 member is 255 * 8 bytes aligned, but u64 member is
201 * always disposed in that manner 256 * always disposed in that manner
202 */ 257 */
203 u64 irq_status; 258 u64 irq_status;
204 u64 ghiintmask; 259 u64 irq_mask;
205 260
206 struct ps3_system_bus_device *dev; 261 struct ps3_system_bus_device *dev;
207 u32 vlan_id[GELIC_NET_VLAN_MAX]; 262 struct gelic_vlan_id vlan[GELIC_PORT_MAX];
208 int vlan_index; 263 int vlan_required;
209 264
210 struct gelic_net_descr_chain tx_chain; 265 struct gelic_descr_chain tx_chain;
211 struct gelic_net_descr_chain rx_chain; 266 struct gelic_descr_chain rx_chain;
212 int rx_dma_restart_required; 267 int rx_dma_restart_required;
213 /* gurad dmac descriptor chain*/
214 spinlock_t chain_lock;
215
216 int rx_csum; 268 int rx_csum;
217 /* guard tx_dma_progress */ 269 /*
218 spinlock_t tx_dma_lock; 270 * tx_lock guards tx descriptor list and
271 * tx_dma_progress.
272 */
273 spinlock_t tx_lock;
219 int tx_dma_progress; 274 int tx_dma_progress;
220 275
221 struct work_struct tx_timeout_task; 276 struct work_struct tx_timeout_task;
222 atomic_t tx_timeout_task_counter; 277 atomic_t tx_timeout_task_counter;
223 wait_queue_head_t waitq; 278 wait_queue_head_t waitq;
224 279
225 struct gelic_net_descr *tx_top, *rx_top; 280 /* only first user should up the card */
226 struct gelic_net_descr descr[0]; 281 struct semaphore updown_lock;
282 atomic_t users;
283
284 u64 ether_port_status;
285 /* original address returned by kzalloc */
286 void *unalign;
287
288 /*
289 * each netdevice has copy of irq
290 */
291 unsigned int irq;
292 struct gelic_descr *tx_top, *rx_top;
293 struct gelic_descr descr[0]; /* must be the last */
294};
295
296struct gelic_port {
297 struct gelic_card *card;
298 struct net_device *netdev;
299 enum gelic_port_type type;
300 long priv[0]; /* long for alignment */
227}; 301};
228 302
303static inline struct gelic_card *port_to_card(struct gelic_port *p)
304{
305 return p->card;
306}
307static inline struct net_device *port_to_netdev(struct gelic_port *p)
308{
309 return p->netdev;
310}
311static inline struct gelic_card *netdev_card(struct net_device *d)
312{
313 return ((struct gelic_port *)netdev_priv(d))->card;
314}
315static inline struct gelic_port *netdev_port(struct net_device *d)
316{
317 return (struct gelic_port *)netdev_priv(d);
318}
319static inline struct device *ctodev(struct gelic_card *card)
320{
321 return &card->dev->core;
322}
323static inline u64 bus_id(struct gelic_card *card)
324{
325 return card->dev->bus_id;
326}
327static inline u64 dev_id(struct gelic_card *card)
328{
329 return card->dev->dev_id;
330}
331
332static inline void *port_priv(struct gelic_port *port)
333{
334 return port->priv;
335}
336
337extern int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
338/* shared netdev ops */
339extern void gelic_card_up(struct gelic_card *card);
340extern void gelic_card_down(struct gelic_card *card);
341extern int gelic_net_open(struct net_device *netdev);
342extern int gelic_net_stop(struct net_device *netdev);
343extern int gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
344extern void gelic_net_set_multi(struct net_device *netdev);
345extern void gelic_net_tx_timeout(struct net_device *netdev);
346extern int gelic_net_change_mtu(struct net_device *netdev, int new_mtu);
347extern int gelic_net_setup_netdev(struct net_device *netdev,
348 struct gelic_card *card);
229 349
230extern unsigned long p_to_lp(long pa); 350/* shared ethtool ops */
351extern void gelic_net_get_drvinfo(struct net_device *netdev,
352 struct ethtool_drvinfo *info);
353extern u32 gelic_net_get_rx_csum(struct net_device *netdev);
354extern int gelic_net_set_rx_csum(struct net_device *netdev, u32 data);
355extern void gelic_net_poll_controller(struct net_device *netdev);
231 356
232#endif /* _GELIC_NET_H */ 357#endif /* _GELIC_NET_H */
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