11 files changed, 447 insertions, 247 deletions

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 65de0cab8d07..14afa4f24424 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -159,8 +159,6 @@ config MDIO_OCTEON
 config MDIO_SUN4I
         tristate "Allwinner sun4i MDIO interface support"
         depends on ARCH_SUNXI
-        select REGULATOR
-        select REGULATOR_FIXED_VOLTAGE
         help
           This driver supports the MDIO interface found in the network
           interface units of the Allwinner SoC that have an EMAC (A10,
@@ -205,6 +203,14 @@ config MDIO_BUS_MUX_MMIOREG
 
           Currently, only 8-bit registers are supported.
 
+config MDIO_BCM_UNIMAC
+        tristate "Broadcom UniMAC MDIO bus controller"
+        help
+          This module provides a driver for the Broadcom UniMAC MDIO busses.
+          This hardware can be found in the Broadcom GENET Ethernet MAC
+          controllers as well as some Broadcom Ethernet switches such as the
+          Starfighter 2 switches.
+
 endif # PHYLIB
 
 config MICREL_KS8995MA
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7dc3d5b304cf..eb3b18b5978b 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
 obj-$(CONFIG_MDIO_SUN4I)        += mdio-sun4i.o
 obj-$(CONFIG_MDIO_MOXART)       += mdio-moxart.o
 obj-$(CONFIG_AMD_XGBE_PHY)      += amd-xgbe-phy.o
+obj-$(CONFIG_MDIO_BCM_UNIMAC)   += mdio-bcm-unimac.o
diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c
index f3230eef41fd..c456559f6e7f 100644
--- a/drivers/net/phy/amd-xgbe-phy.c
+++ b/drivers/net/phy/amd-xgbe-phy.c
@@ -75,7 +75,6 @@
 #include <linux/of_device.h>
 #include <linux/uaccess.h>
 
-
 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
 MODULE_LICENSE("Dual BSD/GPL");
 MODULE_VERSION("1.0.0-a");
@@ -100,9 +99,11 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #ifndef MDIO_PMA_10GBR_PMD_CTRL
 #define MDIO_PMA_10GBR_PMD_CTRL         0x0096
 #endif
+
 #ifndef MDIO_PMA_10GBR_FEC_CTRL
 #define MDIO_PMA_10GBR_FEC_CTRL         0x00ab
 #endif
+
 #ifndef MDIO_AN_XNP
 #define MDIO_AN_XNP                     0x0016
 #endif
@@ -110,14 +111,23 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #ifndef MDIO_AN_INTMASK
 #define MDIO_AN_INTMASK                 0x8001
 #endif
+
 #ifndef MDIO_AN_INT
 #define MDIO_AN_INT                     0x8002
 #endif
 
+#ifndef MDIO_AN_KR_CTRL
+#define MDIO_AN_KR_CTRL                 0x8003
+#endif
+
 #ifndef MDIO_CTRL1_SPEED1G
 #define MDIO_CTRL1_SPEED1G              (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
 #endif
 
+#ifndef MDIO_KR_CTRL_PDETECT
+#define MDIO_KR_CTRL_PDETECT            0x01
+#endif
+
 /* SerDes integration register offsets */
 #define SIR0_KR_RT_1                    0x002c
 #define SIR0_STATUS                     0x0040
@@ -161,7 +171,6 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define SPEED_1000_TXAMP                0xf
 #define SPEED_1000_WORD                 0x1
 
-
 /* SerDes RxTx register offsets */
 #define RXTX_REG20                      0x0050
 #define RXTX_REG114                     0x01c8
@@ -255,7 +264,6 @@ do {									\
         XSIR1_IOWRITE((_priv), _reg, reg_val);                          \
 } while (0)
 
-
 /* Macros for reading or writing SerDes RxTx registers
  *  The ioread macros will get bit fields or full values using the
  *  register definitions formed using the input names
@@ -283,7 +291,6 @@ do {									\
         XRXTX_IOWRITE((_priv), _reg, reg_val);                          \
 } while (0)
 
-
 enum amd_xgbe_phy_an {
         AMD_XGBE_AN_READY = 0,
         AMD_XGBE_AN_START,
@@ -331,7 +338,6 @@ struct amd_xgbe_phy_priv {
 
         /* Maintain link status for re-starting auto-negotiation */
         unsigned int link;
-        enum amd_xgbe_phy_mode mode;
         unsigned int speed_set;
 
         /* Auto-negotiation state machine support */
@@ -342,6 +348,7 @@ struct amd_xgbe_phy_priv {
         enum amd_xgbe_phy_rx kx_state;
         struct work_struct an_work;
         struct workqueue_struct *an_workqueue;
+        unsigned int parallel_detect;
 };
 
 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
@@ -468,8 +475,6 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
-        priv->mode = AMD_XGBE_MODE_KR;
-
         return 0;
 }
 
@@ -518,8 +523,6 @@ static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
-        priv->mode = AMD_XGBE_MODE_KX;
-
         return 0;
 }
 
@@ -568,18 +571,43 @@ static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
-        priv->mode = AMD_XGBE_MODE_KX;
+        return 0;
+}
+
+static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
+                                 enum amd_xgbe_phy_mode *mode)
+{
+        int ret;
+
+        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
+        if (ret < 0)
+                return ret;
+
+        if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
+                *mode = AMD_XGBE_MODE_KR;
+        else
+                *mode = AMD_XGBE_MODE_KX;
 
         return 0;
 }
 
+static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
+{
+        enum amd_xgbe_phy_mode mode;
+
+        if (amd_xgbe_phy_cur_mode(phydev, &mode))
+                return false;
+
+        return (mode == AMD_XGBE_MODE_KR);
+}
+
 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         int ret;
 
         /* If we are in KR switch to KX, and vice-versa */
-        if (priv->mode == AMD_XGBE_MODE_KR) {
+        if (amd_xgbe_phy_in_kr_mode(phydev)) {
                 if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
                         ret = amd_xgbe_phy_gmii_mode(phydev);
                 else
@@ -591,15 +619,20 @@ static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
         return ret;
 }
 
-static enum amd_xgbe_phy_an amd_xgbe_an_switch_mode(struct phy_device *phydev)
+static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
+                                 enum amd_xgbe_phy_mode mode)
 {
+        enum amd_xgbe_phy_mode cur_mode;
         int ret;
 
-        ret = amd_xgbe_phy_switch_mode(phydev);
-        if (ret < 0)
-                return AMD_XGBE_AN_ERROR;
+        ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
+        if (ret)
+                return ret;
 
-        return AMD_XGBE_AN_START;
+        if (mode != cur_mode)
+                ret = amd_xgbe_phy_switch_mode(phydev);
+
+        return ret;
 }
 
 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
@@ -610,8 +643,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
 
         *state = AMD_XGBE_RX_COMPLETE;
 
-        /* If we're in KX mode then we're done */
-        if (priv->mode == AMD_XGBE_MODE_KX)
+        /* If we're not in KR mode then we're done */
+        if (!amd_xgbe_phy_in_kr_mode(phydev))
                 return AMD_XGBE_AN_EVENT;
 
         /* Enable/Disable FEC */
@@ -669,7 +702,6 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
                                                enum amd_xgbe_phy_rx *state)
 {
-        struct amd_xgbe_phy_priv *priv = phydev->priv;
         unsigned int link_support;
         int ret, ad_reg, lp_reg;
 
@@ -679,9 +711,9 @@ static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
                 return AMD_XGBE_AN_ERROR;
 
         /* Check for a supported mode, otherwise restart in a different one */
-        link_support = (priv->mode == AMD_XGBE_MODE_KR) ? 0x80 : 0x20;
+        link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
         if (!(ret & link_support))
-                return amd_xgbe_an_switch_mode(phydev);
+                return AMD_XGBE_AN_INCOMPAT_LINK;
 
         /* Check Extended Next Page support */
         ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
@@ -722,7 +754,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
         int ret;
 
         /* Be sure we aren't looping trying to negotiate */
-        if (priv->mode == AMD_XGBE_MODE_KR) {
+        if (amd_xgbe_phy_in_kr_mode(phydev)) {
                 if (priv->kr_state != AMD_XGBE_RX_READY)
                         return AMD_XGBE_AN_NO_LINK;
                 priv->kr_state = AMD_XGBE_RX_BPA;
@@ -785,6 +817,13 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
         /* Enable and start auto-negotiation */
         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
 
+        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
+        if (ret < 0)
+                return AMD_XGBE_AN_ERROR;
+
+        ret |= MDIO_KR_CTRL_PDETECT;
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
+
         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
         if (ret < 0)
                 return AMD_XGBE_AN_ERROR;
@@ -825,8 +864,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
         enum amd_xgbe_phy_rx *state;
         int ret;
 
-        state = (priv->mode == AMD_XGBE_MODE_KR) ? &priv->kr_state
-                                                 : &priv->kx_state;
+        state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
+                                                : &priv->kx_state;
 
         switch (*state) {
         case AMD_XGBE_RX_BPA:
@@ -846,7 +885,13 @@ static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
 
 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
 {
-        return amd_xgbe_an_switch_mode(phydev);
+        int ret;
+
+        ret = amd_xgbe_phy_switch_mode(phydev);
+        if (ret)
+                return AMD_XGBE_AN_ERROR;
+
+        return AMD_XGBE_AN_START;
 }
 
 static void amd_xgbe_an_state_machine(struct work_struct *work)
@@ -859,6 +904,10 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
         int sleep;
         unsigned int an_supported = 0;
 
+        /* Start in KX mode */
+        if (amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX))
+                priv->an_state = AMD_XGBE_AN_ERROR;
+
         while (1) {
                 mutex_lock(&priv->an_mutex);
 
@@ -866,8 +915,9 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
 
                 switch (priv->an_state) {
                 case AMD_XGBE_AN_START:
-                        priv->an_state = amd_xgbe_an_start(phydev);
                         an_supported = 0;
+                        priv->parallel_detect = 0;
+                        priv->an_state = amd_xgbe_an_start(phydev);
                         break;
 
                 case AMD_XGBE_AN_EVENT:
@@ -884,6 +934,7 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
                         break;
 
                 case AMD_XGBE_AN_COMPLETE:
+                        priv->parallel_detect = an_supported ? 0 : 1;
                         netdev_info(phydev->attached_dev, "%s successful\n",
                                     an_supported ? "Auto negotiation"
                                                  : "Parallel detection");
@@ -1018,7 +1069,6 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         u32 mmd_mask = phydev->c45_ids.devices_in_package;
-        int ret;
 
         if (phydev->autoneg != AUTONEG_ENABLE)
                 return amd_xgbe_phy_setup_forced(phydev);
@@ -1027,11 +1077,6 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
         if (!(mmd_mask & MDIO_DEVS_AN))
                 return -EINVAL;
 
-        /* Get the current speed mode */
-        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-        if (ret < 0)
-                return ret;
-
         /* Start/Restart the auto-negotiation state machine */
         mutex_lock(&priv->an_mutex);
         priv->an_result = AMD_XGBE_AN_READY;
@@ -1121,18 +1166,14 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         u32 mmd_mask = phydev->c45_ids.devices_in_package;
-        int ret, mode, ad_ret, lp_ret;
+        int ret, ad_ret, lp_ret;
 
         ret = amd_xgbe_phy_update_link(phydev);
         if (ret)
                 return ret;
 
-        mode = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-        if (mode < 0)
-                return mode;
-        mode &= MDIO_PCS_CTRL2_TYPE;
-
-        if (phydev->autoneg == AUTONEG_ENABLE) {
+        if ((phydev->autoneg == AUTONEG_ENABLE) &&
+            !priv->parallel_detect) {
                 if (!(mmd_mask & MDIO_DEVS_AN))
                         return -EINVAL;
 
@@ -1163,40 +1204,39 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
                 ad_ret &= lp_ret;
                 if (ad_ret & 0x80) {
                         phydev->speed = SPEED_10000;
-                        if (mode != MDIO_PCS_CTRL2_10GBR) {
-                                ret = amd_xgbe_phy_xgmii_mode(phydev);
-                                if (ret < 0)
-                                        return ret;
-                        }
+                        ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
+                        if (ret)
+                                return ret;
                 } else {
-                        int (*mode_fcn)(struct phy_device *);
-
-                        if (priv->speed_set ==
-                            AMD_XGBE_PHY_SPEEDSET_1000_10000) {
+                        switch (priv->speed_set) {
+                        case AMD_XGBE_PHY_SPEEDSET_1000_10000:
                                 phydev->speed = SPEED_1000;
-                                mode_fcn = amd_xgbe_phy_gmii_mode;
-                        } else {
+                                break;
+
+                        case AMD_XGBE_PHY_SPEEDSET_2500_10000:
                                 phydev->speed = SPEED_2500;
-                                mode_fcn = amd_xgbe_phy_gmii_2500_mode;
+                                break;
                         }
 
-                        if (mode == MDIO_PCS_CTRL2_10GBR) {
-                                ret = mode_fcn(phydev);
-                                if (ret < 0)
-                                        return ret;
-                        }
+                        ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
+                        if (ret)
+                                return ret;
                 }
 
                 phydev->duplex = DUPLEX_FULL;
         } else {
-                if (mode == MDIO_PCS_CTRL2_10GBR) {
+                if (amd_xgbe_phy_in_kr_mode(phydev)) {
                         phydev->speed = SPEED_10000;
                 } else {
-                        if (priv->speed_set ==
-                            AMD_XGBE_PHY_SPEEDSET_1000_10000)
+                        switch (priv->speed_set) {
+                        case AMD_XGBE_PHY_SPEEDSET_1000_10000:
                                 phydev->speed = SPEED_1000;
-                        else
+                                break;
+
+                        case AMD_XGBE_PHY_SPEEDSET_2500_10000:
                                 phydev->speed = SPEED_2500;
+                                break;
+                        }
                 }
                 phydev->duplex = DUPLEX_FULL;
                 phydev->pause = 0;
@@ -1329,14 +1369,6 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
 
         priv->link = 1;
 
-        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-        if (ret < 0)
-                goto err_sir1;
-        if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
-                priv->mode = AMD_XGBE_MODE_KR;
-        else
-                priv->mode = AMD_XGBE_MODE_KX;
-
         mutex_init(&priv->an_mutex);
         INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
         priv->an_workqueue = create_singlethread_workqueue(wq_name);
diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c
index fdce1ea28790..09dd6e1dc6e1 100644
--- a/drivers/net/phy/bcm7xxx.c
+++ b/drivers/net/phy/bcm7xxx.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/bitops.h>
 #include <linux/brcmphy.h>
+#include <linux/mdio.h>
 
 /* Broadcom BCM7xxx internal PHY registers */
 #define MII_BCM7XXX_CHANNEL_WIDTH       0x2000
@@ -146,6 +147,53 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
         return 0;
 }
 
+static int bcm7xxx_apd_enable(struct phy_device *phydev)
+{
+        int val;
+
+        /* Enable powering down of the DLL during auto-power down */
+        val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
+        if (val < 0)
+                return val;
+
+        val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
+        bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
+
+        /* Enable auto-power down */
+        val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
+        if (val < 0)
+                return val;
+
+        val |= BCM54XX_SHD_APD_EN;
+        return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
+}
+
+static int bcm7xxx_eee_enable(struct phy_device *phydev)
+{
+        int val;
+
+        val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
+                                    MDIO_MMD_AN, phydev->addr);
+        if (val < 0)
+                return val;
+
+        /* Enable general EEE feature at the PHY level */
+        val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
+
+        phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
+                               MDIO_MMD_AN, phydev->addr, val);
+
+        /* Advertise supported modes */
+        val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
+                                    MDIO_MMD_AN, phydev->addr);
+
+        val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
+        phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
+                               MDIO_MMD_AN, phydev->addr, val);
+
+        return 0;
+}
+
 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
 {
         int ret;
@@ -154,7 +202,15 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
         if (ret)
                 return ret;
 
-        return bcm7xxx_28nm_afe_config_init(phydev);
+        ret = bcm7xxx_28nm_afe_config_init(phydev);
+        if (ret)
+                return ret;
+
+        ret = bcm7xxx_eee_enable(phydev);
+        if (ret)
+                return ret;
+
+        return bcm7xxx_apd_enable(phydev);
 }
 
 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
@@ -263,44 +319,28 @@ static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
         return 0;
 }
 
+#define BCM7XXX_28NM_GPHY(_oui, _name)                                  \
+{                                                                       \
+        .phy_id         = (_oui),                                       \
+        .phy_id_mask    = 0xfffffff0,                                   \
+        .name           = _name,                                        \
+        .features       = PHY_GBIT_FEATURES |                           \
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,       \
+        .flags          = PHY_IS_INTERNAL,                              \
+        .config_init    = bcm7xxx_28nm_afe_config_init,                 \
+        .config_aneg    = genphy_config_aneg,                           \
+        .read_status    = genphy_read_status,                           \
+        .resume         = bcm7xxx_28nm_resume,                          \
+        .driver         = { .owner = THIS_MODULE },                     \
+}
+
 static struct phy_driver bcm7xxx_driver[] = {
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
 {
-        .phy_id         = PHY_ID_BCM7366,
-        .phy_id_mask    = 0xfffffff0,
-        .name           = "Broadcom BCM7366",
-        .features       = PHY_GBIT_FEATURES |
-                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-        .flags          = PHY_IS_INTERNAL,
-        .config_init    = bcm7xxx_28nm_afe_config_init,
-        .config_aneg    = genphy_config_aneg,
-        .read_status    = genphy_read_status,
-        .resume         = bcm7xxx_28nm_resume,
-        .driver         = { .owner = THIS_MODULE },
-}, {
-        .phy_id         = PHY_ID_BCM7439,
-        .phy_id_mask    = 0xfffffff0,
-        .name           = "Broadcom BCM7439",
-        .features       = PHY_GBIT_FEATURES |
-                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-        .flags          = PHY_IS_INTERNAL,
-        .config_init    = bcm7xxx_28nm_afe_config_init,
-        .config_aneg    = genphy_config_aneg,
-        .read_status    = genphy_read_status,
-        .resume         = bcm7xxx_28nm_resume,
-        .driver         = { .owner = THIS_MODULE },
-}, {
-        .phy_id         = PHY_ID_BCM7445,
-        .phy_id_mask    = 0xfffffff0,
-        .name           = "Broadcom BCM7445",
-        .features       = PHY_GBIT_FEATURES |
-                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-        .flags          = PHY_IS_INTERNAL,
-        .config_init    = bcm7xxx_28nm_config_init,
-        .config_aneg    = genphy_config_aneg,
-        .read_status    = genphy_read_status,
-        .resume         = bcm7xxx_28nm_afe_config_init,
-        .driver         = { .owner = THIS_MODULE },
-}, {
         .phy_id         = PHY_BCM_OUI_4,
         .phy_id_mask    = 0xffff0000,
         .name           = "Broadcom BCM7XXX 40nm",
@@ -329,6 +369,8 @@ static struct phy_driver bcm7xxx_driver[] = {
 } };
 
 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
+        { PHY_ID_BCM7250, 0xfffffff0, },
+        { PHY_ID_BCM7364, 0xfffffff0, },
         { PHY_ID_BCM7366, 0xfffffff0, },
         { PHY_ID_BCM7439, 0xfffffff0, },
         { PHY_ID_BCM7445, 0xfffffff0, },
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 34088d60da74..854f2c9a7b2b 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -25,132 +25,10 @@
 #define BRCM_PHY_REV(phydev) \
         ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
 
-/*
- * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
- * BCM5482, and possibly some others.
- */
-#define BCM_LED_SRC_LINKSPD1    0x0
-#define BCM_LED_SRC_LINKSPD2    0x1
-#define BCM_LED_SRC_XMITLED     0x2
-#define BCM_LED_SRC_ACTIVITYLED 0x3
-#define BCM_LED_SRC_FDXLED      0x4
-#define BCM_LED_SRC_SLAVE       0x5
-#define BCM_LED_SRC_INTR        0x6
-#define BCM_LED_SRC_QUALITY     0x7
-#define BCM_LED_SRC_RCVLED      0x8
-#define BCM_LED_SRC_MULTICOLOR1 0xa
-#define BCM_LED_SRC_OPENSHORT   0xb
-#define BCM_LED_SRC_OFF         0xe     /* Tied high */
-#define BCM_LED_SRC_ON          0xf     /* Tied low */
-
-
-/*
- * BCM5482: Shadow registers
- * Shadow values go into bits [14:10] of register 0x1c to select a shadow
- * register to access.
- */
-/* 00101: Spare Control Register 3 */
-#define BCM54XX_SHD_SCR3                0x05
-#define  BCM54XX_SHD_SCR3_DEF_CLK125    0x0001
-#define  BCM54XX_SHD_SCR3_DLLAPD_DIS    0x0002
-#define  BCM54XX_SHD_SCR3_TRDDAPD       0x0004
-
-/* 01010: Auto Power-Down */
-#define BCM54XX_SHD_APD                 0x0a
-#define  BCM54XX_SHD_APD_EN             0x0020
-
-#define BCM5482_SHD_LEDS1       0x0d    /* 01101: LED Selector 1 */
-                                        /* LED3 / ~LINKSPD[2] selector */
-#define BCM5482_SHD_LEDS1_LED3(src)     ((src & 0xf) << 4)
-                                        /* LED1 / ~LINKSPD[1] selector */
-#define BCM5482_SHD_LEDS1_LED1(src)     ((src & 0xf) << 0)
-#define BCM54XX_SHD_RGMII_MODE  0x0b    /* 01011: RGMII Mode Selector */
-#define BCM5482_SHD_SSD         0x14    /* 10100: Secondary SerDes control */
-#define BCM5482_SHD_SSD_LEDM    0x0008  /* SSD LED Mode enable */
-#define BCM5482_SHD_SSD_EN      0x0001  /* SSD enable */
-#define BCM5482_SHD_MODE        0x1f    /* 11111: Mode Control Register */
-#define BCM5482_SHD_MODE_1000BX 0x0001  /* Enable 1000BASE-X registers */
-
-
-/*
- * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
- */
-#define MII_BCM54XX_EXP_AADJ1CH0                0x001f
-#define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN  0x0200
-#define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF    0x0100
-#define MII_BCM54XX_EXP_AADJ1CH3                0x601f
-#define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ      0x0002
-#define MII_BCM54XX_EXP_EXP08                   0x0F08
-#define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ        0x0001
-#define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE   0x0200
-#define MII_BCM54XX_EXP_EXP75                   0x0f75
-#define  MII_BCM54XX_EXP_EXP75_VDACCTRL         0x003c
-#define  MII_BCM54XX_EXP_EXP75_CM_OSC           0x0001
-#define MII_BCM54XX_EXP_EXP96                   0x0f96
-#define  MII_BCM54XX_EXP_EXP96_MYST             0x0010
-#define MII_BCM54XX_EXP_EXP97                   0x0f97
-#define  MII_BCM54XX_EXP_EXP97_MYST             0x0c0c
-
-/*
- * BCM5482: Secondary SerDes registers
- */
-#define BCM5482_SSD_1000BX_CTL          0x00    /* 1000BASE-X Control */
-#define BCM5482_SSD_1000BX_CTL_PWRDOWN  0x0800  /* Power-down SSD */
-#define BCM5482_SSD_SGMII_SLAVE         0x15    /* SGMII Slave Register */
-#define BCM5482_SSD_SGMII_SLAVE_EN      0x0002  /* Slave mode enable */
-#define BCM5482_SSD_SGMII_SLAVE_AD      0x0001  /* Slave auto-detection */
-
-
-/*****************************************************************************/
-/* Fast Ethernet Transceiver definitions. */
-/*****************************************************************************/
-
-#define MII_BRCM_FET_INTREG             0x1a    /* Interrupt register */
-#define MII_BRCM_FET_IR_MASK            0x0100  /* Mask all interrupts */
-#define MII_BRCM_FET_IR_LINK_EN         0x0200  /* Link status change enable */
-#define MII_BRCM_FET_IR_SPEED_EN        0x0400  /* Link speed change enable */
-#define MII_BRCM_FET_IR_DUPLEX_EN       0x0800  /* Duplex mode change enable */
-#define MII_BRCM_FET_IR_ENABLE          0x4000  /* Interrupt enable */
-
-#define MII_BRCM_FET_BRCMTEST           0x1f    /* Brcm test register */
-#define MII_BRCM_FET_BT_SRE             0x0080  /* Shadow register enable */
-
-
-/*** Shadow register definitions ***/
-
-#define MII_BRCM_FET_SHDW_MISCCTRL      0x10    /* Shadow misc ctrl */
-#define MII_BRCM_FET_SHDW_MC_FAME       0x4000  /* Force Auto MDIX enable */
-
-#define MII_BRCM_FET_SHDW_AUXMODE4      0x1a    /* Auxiliary mode 4 */
-#define MII_BRCM_FET_SHDW_AM4_LED_MASK  0x0003
-#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
-
-#define MII_BRCM_FET_SHDW_AUXSTAT2      0x1b    /* Auxiliary status 2 */
-#define MII_BRCM_FET_SHDW_AS2_APDE      0x0020  /* Auto power down enable */
-
-
 MODULE_DESCRIPTION("Broadcom PHY driver");
 MODULE_AUTHOR("Maciej W. Rozycki");
 MODULE_LICENSE("GPL");
 
-/*
- * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
- * 0x1c shadow registers.
- */
-static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
-{
-        phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
-        return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
-}
-
-static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
-{
-        return phy_write(phydev, MII_BCM54XX_SHD,
-                         MII_BCM54XX_SHD_WRITE |
-                         MII_BCM54XX_SHD_VAL(shadow) |
-                         MII_BCM54XX_SHD_DATA(val));
-}
-
 /* Indirect register access functions for the Expansion Registers */
 static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
 {
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index c301e4cb37ca..87648b306551 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -721,7 +721,7 @@ static inline u16 exts_chan_to_edata(int ch)
 }
 
 static int decode_evnt(struct dp83640_private *dp83640,
-                       void *data, u16 ests)
+                       void *data, int len, u16 ests)
 {
         struct phy_txts *phy_txts;
         struct ptp_clock_event event;
@@ -729,6 +729,16 @@ static int decode_evnt(struct dp83640_private *dp83640,
         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
         u16 ext_status = 0;
 
+        /* calculate length of the event timestamp status message */
+        if (ests & MULT_EVNT)
+                parsed = (words + 2) * sizeof(u16);
+        else
+                parsed = (words + 1) * sizeof(u16);
+
+        /* check if enough data is available */
+        if (len < parsed)
+                return len;
+
         if (ests & MULT_EVNT) {
                 ext_status = *(u16 *) data;
                 data += sizeof(ext_status);
@@ -747,10 +757,7 @@ static int decode_evnt(struct dp83640_private *dp83640,
                 dp83640->edata.ns_lo = phy_txts->ns_lo;
         }
 
-        if (ext_status) {
-                parsed = words + 2;
-        } else {
-                parsed = words + 1;
+        if (!ext_status) {
                 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
                 ext_status = exts_chan_to_edata(i);
         }
@@ -768,7 +775,7 @@ static int decode_evnt(struct dp83640_private *dp83640,
                 }
         }
 
-        return parsed * sizeof(u16);
+        return parsed;
 }
 
 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
@@ -905,9 +912,9 @@ static void decode_status_frame(struct dp83640_private *dp83640,
                         decode_txts(dp83640, phy_txts);
                         size = sizeof(*phy_txts);
 
-                } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
+                } else if (PSF_EVNT == type) {
 
-                        size = decode_evnt(dp83640, ptr, ests);
+                        size = decode_evnt(dp83640, ptr, len, ests);
 
                 } else {
                         size = 0;
@@ -1141,7 +1148,7 @@ static void dp83640_remove(struct phy_device *phydev)
                 kfree_skb(skb);
 
         while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL)
-                skb_complete_tx_timestamp(skb, NULL);
+                kfree_skb(skb);
 
         clock = dp83640_clock_get(dp83640->clock);
 
@@ -1398,7 +1405,7 @@ static void dp83640_txtstamp(struct phy_device *phydev,
 
         case HWTSTAMP_TX_ONESTEP_SYNC:
                 if (is_sync(skb, type)) {
-                        skb_complete_tx_timestamp(skb, NULL);
+                        kfree_skb(skb);
                         return;
                 }
                 /* fall through */
@@ -1409,7 +1416,7 @@ static void dp83640_txtstamp(struct phy_device *phydev,
 
         case HWTSTAMP_TX_OFF:
         default:
-                skb_complete_tx_timestamp(skb, NULL);
+                kfree_skb(skb);
                 break;
         }
 }
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index d60d875cb445..5b19fbbda6d4 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -124,6 +124,17 @@ static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
         if (reg_num >= MII_REGS_NUM)
                 return -1;
 
+        /* We do not support emulating Clause 45 over Clause 22 register reads
+         * return an error instead of bogus data.
+         */
+        switch (reg_num) {
+        case MII_MMD_CTRL:
+        case MII_MMD_DATA:
+                return -1;
+        default:
+                break;
+        }
+
         list_for_each_entry(fp, &fmb->phys, node) {
                 if (fp->addr == phy_addr) {
                         /* Issue callback if user registered it. */
diff --git a/drivers/net/phy/mdio-bcm-unimac.c b/drivers/net/phy/mdio-bcm-unimac.c
new file mode 100644
index 000000000000..5b643e588e8f
--- /dev/null
+++ b/drivers/net/phy/mdio-bcm-unimac.c
@@ -0,0 +1,213 @@
+/*
+ * Broadcom UniMAC MDIO bus controller driver
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_mdio.h>
+
+#define MDIO_CMD                0x00
+#define  MDIO_START_BUSY        (1 << 29)
+#define  MDIO_READ_FAIL         (1 << 28)
+#define  MDIO_RD                (2 << 26)
+#define  MDIO_WR                (1 << 26)
+#define  MDIO_PMD_SHIFT         21
+#define  MDIO_PMD_MASK          0x1F
+#define  MDIO_REG_SHIFT         16
+#define  MDIO_REG_MASK          0x1F
+
+#define MDIO_CFG                0x04
+#define  MDIO_C22               (1 << 0)
+#define  MDIO_C45               0
+#define  MDIO_CLK_DIV_SHIFT     4
+#define  MDIO_CLK_DIV_MASK      0x3F
+#define  MDIO_SUPP_PREAMBLE     (1 << 12)
+
+struct unimac_mdio_priv {
+        struct mii_bus          *mii_bus;
+        void __iomem            *base;
+};
+
+static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
+{
+        u32 reg;
+
+        reg = __raw_readl(priv->base + MDIO_CMD);
+        reg |= MDIO_START_BUSY;
+        __raw_writel(reg, priv->base + MDIO_CMD);
+}
+
+static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
+{
+        return __raw_readl(priv->base + MDIO_CMD) & MDIO_START_BUSY;
+}
+
+static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
+{
+        struct unimac_mdio_priv *priv = bus->priv;
+        unsigned int timeout = 1000;
+        u32 cmd;
+
+        /* Prepare the read operation */
+        cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
+        __raw_writel(cmd, priv->base + MDIO_CMD);
+
+        /* Start MDIO transaction */
+        unimac_mdio_start(priv);
+
+        do {
+                if (!unimac_mdio_busy(priv))
+                        break;
+
+                usleep_range(1000, 2000);
+        } while (timeout--);
+
+        if (!timeout)
+                return -ETIMEDOUT;
+
+        cmd = __raw_readl(priv->base + MDIO_CMD);
+        if (cmd & MDIO_READ_FAIL)
+                return -EIO;
+
+        return cmd & 0xffff;
+}
+
+static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
+                             int reg, u16 val)
+{
+        struct unimac_mdio_priv *priv = bus->priv;
+        unsigned int timeout = 1000;
+        u32 cmd;
+
+        /* Prepare the write operation */
+        cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
+                (reg << MDIO_REG_SHIFT) | (0xffff & val);
+        __raw_writel(cmd, priv->base + MDIO_CMD);
+
+        unimac_mdio_start(priv);
+
+        do {
+                if (!unimac_mdio_busy(priv))
+                        break;
+
+                usleep_range(1000, 2000);
+        } while (timeout--);
+
+        if (!timeout)
+                return -ETIMEDOUT;
+
+        return 0;
+}
+
+static int unimac_mdio_probe(struct platform_device *pdev)
+{
+        struct unimac_mdio_priv *priv;
+        struct device_node *np;
+        struct mii_bus *bus;
+        struct resource *r;
+        int ret;
+
+        np = pdev->dev.of_node;
+
+        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        /* Just ioremap, as this MDIO block is usually integrated into an
+         * Ethernet MAC controller register range
+         */
+        priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+        if (!priv->base) {
+                dev_err(&pdev->dev, "failed to remap register\n");
+                return -ENOMEM;
+        }
+
+        priv->mii_bus = mdiobus_alloc();
+        if (!priv->mii_bus)
+                return -ENOMEM;
+
+        bus = priv->mii_bus;
+        bus->priv = priv;
+        bus->name = "unimac MII bus";
+        bus->parent = &pdev->dev;
+        bus->read = unimac_mdio_read;
+        bus->write = unimac_mdio_write;
+        snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
+
+        bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
+        if (!bus->irq) {
+                ret = -ENOMEM;
+                goto out_mdio_free;
+        }
+
+        ret = of_mdiobus_register(bus, np);
+        if (ret) {
+                dev_err(&pdev->dev, "MDIO bus registration failed\n");
+                goto out_mdio_irq;
+        }
+
+        platform_set_drvdata(pdev, priv);
+
+        dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus at 0x%p\n", priv->base);
+
+        return 0;
+
+out_mdio_irq:
+        kfree(bus->irq);
+out_mdio_free:
+        mdiobus_free(bus);
+        return ret;
+}
+
+static int unimac_mdio_remove(struct platform_device *pdev)
+{
+        struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
+
+        mdiobus_unregister(priv->mii_bus);
+        kfree(priv->mii_bus->irq);
+        mdiobus_free(priv->mii_bus);
+
+        return 0;
+}
+
+static struct of_device_id unimac_mdio_ids[] = {
+        { .compatible = "brcm,genet-mdio-v4", },
+        { .compatible = "brcm,genet-mdio-v3", },
+        { .compatible = "brcm,genet-mdio-v2", },
+        { .compatible = "brcm,genet-mdio-v1", },
+        { .compatible = "brcm,unimac-mdio", },
+        { /* sentinel */ },
+};
+
+static struct platform_driver unimac_mdio_driver = {
+        .driver = {
+                .name = "unimac-mdio",
+                .owner = THIS_MODULE,
+                .of_match_table = unimac_mdio_ids,
+        },
+        .probe  = unimac_mdio_probe,
+        .remove = unimac_mdio_remove,
+};
+module_platform_driver(unimac_mdio_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:unimac-mdio");
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 4eaadcfcb0fe..50051f271b10 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -553,8 +553,14 @@ static ssize_t
 phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct phy_device *phydev = to_phy_device(dev);
+        const char *mode = NULL;
 
-        return sprintf(buf, "%s\n", phy_modes(phydev->interface));
+        if (phy_is_internal(phydev))
+                mode = "internal";
+        else
+                mode = phy_modes(phydev->interface);
+
+        return sprintf(buf, "%s\n", mode);
 }
 static DEVICE_ATTR_RO(phy_interface);
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index a854d38c231d..1dfffdc9dfc3 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -955,7 +955,7 @@ static inline void mmd_phy_indirect(struct mii_bus *bus, int prtad, int devad,
  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
  * 3) Read  reg 14 // Read MMD data
  */
-static int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
+int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
                                  int devad, int addr)
 {
         struct phy_driver *phydrv = phydev->drv;
@@ -971,6 +971,7 @@ static int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
         }
         return value;
 }
+EXPORT_SYMBOL(phy_read_mmd_indirect);
 
 /**
  * phy_write_mmd_indirect - writes data to the MMD registers
@@ -988,7 +989,7 @@ static int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
  * 3) Write reg 14 // Write MMD data
  */
-static void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
+void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
                                    int devad, int addr, u32 data)
 {
         struct phy_driver *phydrv = phydev->drv;
@@ -1002,6 +1003,7 @@ static void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
                 phydrv->write_mmd_indirect(phydev, prtad, devad, addr, data);
         }
 }
+EXPORT_SYMBOL(phy_write_mmd_indirect);
 
 /**
  * phy_init_eee - init and check the EEE feature
@@ -1017,12 +1019,14 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
 {
         /* According to 802.3az,the EEE is supported only in full duplex-mode.
          * Also EEE feature is active when core is operating with MII, GMII
-         * or RGMII.
+         * or RGMII. Internal PHYs are also allowed to proceed and should
+         * return an error if they do not support EEE.
          */
         if ((phydev->duplex == DUPLEX_FULL) &&
             ((phydev->interface == PHY_INTERFACE_MODE_MII) ||
             (phydev->interface == PHY_INTERFACE_MODE_GMII) ||
-            (phydev->interface == PHY_INTERFACE_MODE_RGMII))) {
+            (phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
+             phy_is_internal(phydev))) {
                 int eee_lp, eee_cap, eee_adv;
                 u32 lp, cap, adv;
                 int status;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index ca5ec3e18d36..3fc91e89f5a5 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -230,13 +230,13 @@ static int get_phy_c45_ids(struct mii_bus *bus, int addr, u32 *phy_id,
         for (i = 1;
              i < num_ids && c45_ids->devices_in_package == 0;
              i++) {
-                reg_addr = MII_ADDR_C45 | i << 16 | 6;
+                reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS2;
                 phy_reg = mdiobus_read(bus, addr, reg_addr);
                 if (phy_reg < 0)
                         return -EIO;
                 c45_ids->devices_in_package = (phy_reg & 0xffff) << 16;
 
-                reg_addr = MII_ADDR_C45 | i << 16 | 5;
+                reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS1;
                 phy_reg = mdiobus_read(bus, addr, reg_addr);
                 if (phy_reg < 0)
                         return -EIO;