1 files changed, 634 insertions, 347 deletions

diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c
index 903dc3dc9ea7..9e3af54c9010 100644
--- a/drivers/net/phy/amd-xgbe-phy.c
+++ b/drivers/net/phy/amd-xgbe-phy.c
@@ -60,6 +60,7 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/delay.h>
+#include <linux/workqueue.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
@@ -74,6 +75,9 @@
 #include <linux/of_platform.h>
 #include <linux/of_device.h>
 #include <linux/uaccess.h>
+#include <linux/bitops.h>
+#include <linux/property.h>
+#include <linux/acpi.h>
 
 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
 MODULE_LICENSE("Dual BSD/GPL");
@@ -84,22 +88,43 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define XGBE_PHY_MASK   0xfffffff0
 
 #define XGBE_PHY_SPEEDSET_PROPERTY      "amd,speed-set"
+#define XGBE_PHY_BLWC_PROPERTY          "amd,serdes-blwc"
+#define XGBE_PHY_CDR_RATE_PROPERTY      "amd,serdes-cdr-rate"
+#define XGBE_PHY_PQ_SKEW_PROPERTY       "amd,serdes-pq-skew"
+#define XGBE_PHY_TX_AMP_PROPERTY        "amd,serdes-tx-amp"
+
+#define XGBE_PHY_SPEEDS                 3
+#define XGBE_PHY_SPEED_1000             0
+#define XGBE_PHY_SPEED_2500             1
+#define XGBE_PHY_SPEED_10000            2
 
 #define XGBE_AN_INT_CMPLT               0x01
 #define XGBE_AN_INC_LINK                0x02
 #define XGBE_AN_PG_RCV                  0x04
+#define XGBE_AN_INT_MASK                0x07
 
 #define XNP_MCF_NULL_MESSAGE            0x001
-#define XNP_ACK_PROCESSED               (1 << 12)
-#define XNP_MP_FORMATTED                (1 << 13)
-#define XNP_NP_EXCHANGE                 (1 << 15)
+#define XNP_ACK_PROCESSED               BIT(12)
+#define XNP_MP_FORMATTED                BIT(13)
+#define XNP_NP_EXCHANGE                 BIT(15)
 
 #define XGBE_PHY_RATECHANGE_COUNT       500
 
+#define XGBE_PHY_KR_TRAINING_START      0x01
+#define XGBE_PHY_KR_TRAINING_ENABLE     0x02
+
+#define XGBE_PHY_FEC_ENABLE             0x01
+#define XGBE_PHY_FEC_FORWARD            0x02
+#define XGBE_PHY_FEC_MASK               0x03
+
 #ifndef MDIO_PMA_10GBR_PMD_CTRL
 #define MDIO_PMA_10GBR_PMD_CTRL         0x0096
 #endif
 
+#ifndef MDIO_PMA_10GBR_FEC_ABILITY
+#define MDIO_PMA_10GBR_FEC_ABILITY      0x00aa
+#endif
+
 #ifndef MDIO_PMA_10GBR_FEC_CTRL
 #define MDIO_PMA_10GBR_FEC_CTRL         0x00ab
 #endif
@@ -108,6 +133,10 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define MDIO_AN_XNP                     0x0016
 #endif
 
+#ifndef MDIO_AN_LPX
+#define MDIO_AN_LPX                     0x0019
+#endif
+
 #ifndef MDIO_AN_INTMASK
 #define MDIO_AN_INTMASK                 0x8001
 #endif
@@ -116,18 +145,10 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define MDIO_AN_INT                     0x8002
 #endif
 
-#ifndef MDIO_AN_KR_CTRL
-#define MDIO_AN_KR_CTRL                 0x8003
-#endif
-
 #ifndef MDIO_CTRL1_SPEED1G
 #define MDIO_CTRL1_SPEED1G              (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
 #endif
 
-#ifndef MDIO_KR_CTRL_PDETECT
-#define MDIO_KR_CTRL_PDETECT            0x01
-#endif
-
 /* SerDes integration register offsets */
 #define SIR0_KR_RT_1                    0x002c
 #define SIR0_STATUS                     0x0040
@@ -140,10 +161,10 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define SIR0_STATUS_RX_READY_WIDTH      1
 #define SIR0_STATUS_TX_READY_INDEX      8
 #define SIR0_STATUS_TX_READY_WIDTH      1
+#define SIR1_SPEED_CDR_RATE_INDEX       12
+#define SIR1_SPEED_CDR_RATE_WIDTH       4
 #define SIR1_SPEED_DATARATE_INDEX       4
 #define SIR1_SPEED_DATARATE_WIDTH       2
-#define SIR1_SPEED_PI_SPD_SEL_INDEX     12
-#define SIR1_SPEED_PI_SPD_SEL_WIDTH     4
 #define SIR1_SPEED_PLLSEL_INDEX         3
 #define SIR1_SPEED_PLLSEL_WIDTH         1
 #define SIR1_SPEED_RATECHANGE_INDEX     6
@@ -153,20 +174,26 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define SIR1_SPEED_WORDMODE_INDEX       0
 #define SIR1_SPEED_WORDMODE_WIDTH       3
 
+#define SPEED_10000_BLWC                0
 #define SPEED_10000_CDR                 0x7
 #define SPEED_10000_PLL                 0x1
+#define SPEED_10000_PQ                  0x1e
 #define SPEED_10000_RATE                0x0
 #define SPEED_10000_TXAMP               0xa
 #define SPEED_10000_WORD                0x7
 
+#define SPEED_2500_BLWC                 1
 #define SPEED_2500_CDR                  0x2
 #define SPEED_2500_PLL                  0x0
+#define SPEED_2500_PQ                   0xa
 #define SPEED_2500_RATE                 0x1
 #define SPEED_2500_TXAMP                0xf
 #define SPEED_2500_WORD                 0x1
 
+#define SPEED_1000_BLWC                 1
 #define SPEED_1000_CDR                  0x2
 #define SPEED_1000_PLL                  0x0
+#define SPEED_1000_PQ                   0xa
 #define SPEED_1000_RATE                 0x3
 #define SPEED_1000_TXAMP                0xf
 #define SPEED_1000_WORD                 0x1
@@ -181,15 +208,6 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define RXTX_REG114_PQ_REG_INDEX        9
 #define RXTX_REG114_PQ_REG_WIDTH        7
 
-#define RXTX_10000_BLWC                 0
-#define RXTX_10000_PQ                   0x1e
-
-#define RXTX_2500_BLWC                  1
-#define RXTX_2500_PQ                    0xa
-
-#define RXTX_1000_BLWC                  1
-#define RXTX_1000_PQ                    0xa
-
 /* Bit setting and getting macros
  *  The get macro will extract the current bit field value from within
  *  the variable
@@ -291,23 +309,44 @@ do {									\
         XRXTX_IOWRITE((_priv), _reg, reg_val);                          \
 } while (0)
 
+static const u32 amd_xgbe_phy_serdes_blwc[] = {
+        SPEED_1000_BLWC,
+        SPEED_2500_BLWC,
+        SPEED_10000_BLWC,
+};
+
+static const u32 amd_xgbe_phy_serdes_cdr_rate[] = {
+        SPEED_1000_CDR,
+        SPEED_2500_CDR,
+        SPEED_10000_CDR,
+};
+
+static const u32 amd_xgbe_phy_serdes_pq_skew[] = {
+        SPEED_1000_PQ,
+        SPEED_2500_PQ,
+        SPEED_10000_PQ,
+};
+
+static const u32 amd_xgbe_phy_serdes_tx_amp[] = {
+        SPEED_1000_TXAMP,
+        SPEED_2500_TXAMP,
+        SPEED_10000_TXAMP,
+};
+
 enum amd_xgbe_phy_an {
         AMD_XGBE_AN_READY = 0,
-        AMD_XGBE_AN_START,
-        AMD_XGBE_AN_EVENT,
         AMD_XGBE_AN_PAGE_RECEIVED,
         AMD_XGBE_AN_INCOMPAT_LINK,
         AMD_XGBE_AN_COMPLETE,
         AMD_XGBE_AN_NO_LINK,
-        AMD_XGBE_AN_EXIT,
         AMD_XGBE_AN_ERROR,
 };
 
 enum amd_xgbe_phy_rx {
-        AMD_XGBE_RX_READY = 0,
-        AMD_XGBE_RX_BPA,
+        AMD_XGBE_RX_BPA = 0,
         AMD_XGBE_RX_XNP,
         AMD_XGBE_RX_COMPLETE,
+        AMD_XGBE_RX_ERROR,
 };
 
 enum amd_xgbe_phy_mode {
@@ -316,12 +355,13 @@ enum amd_xgbe_phy_mode {
 };
 
 enum amd_xgbe_phy_speedset {
-        AMD_XGBE_PHY_SPEEDSET_1000_10000,
+        AMD_XGBE_PHY_SPEEDSET_1000_10000 = 0,
         AMD_XGBE_PHY_SPEEDSET_2500_10000,
 };
 
 struct amd_xgbe_phy_priv {
         struct platform_device *pdev;
+        struct acpi_device *adev;
         struct device *dev;
 
         struct phy_device *phydev;
@@ -336,10 +376,24 @@ struct amd_xgbe_phy_priv {
         void __iomem *sir0_regs;        /* SerDes integration registers (1/2) */
         void __iomem *sir1_regs;        /* SerDes integration registers (2/2) */
 
-        /* Maintain link status for re-starting auto-negotiation */
-        unsigned int link;
+        int an_irq;
+        char an_irq_name[IFNAMSIZ + 32];
+        struct work_struct an_irq_work;
+        unsigned int an_irq_allocated;
+
         unsigned int speed_set;
 
+        /* SerDes UEFI configurable settings.
+         *   Switching between modes/speeds requires new values for some
+         *   SerDes settings.  The values can be supplied as device
+         *   properties in array format.  The first array entry is for
+         *   1GbE, second for 2.5GbE and third for 10GbE
+         */
+        u32 serdes_blwc[XGBE_PHY_SPEEDS];
+        u32 serdes_cdr_rate[XGBE_PHY_SPEEDS];
+        u32 serdes_pq_skew[XGBE_PHY_SPEEDS];
+        u32 serdes_tx_amp[XGBE_PHY_SPEEDS];
+
         /* Auto-negotiation state machine support */
         struct mutex an_mutex;
         enum amd_xgbe_phy_an an_result;
@@ -348,7 +402,11 @@ struct amd_xgbe_phy_priv {
         enum amd_xgbe_phy_rx kx_state;
         struct work_struct an_work;
         struct workqueue_struct *an_workqueue;
+        unsigned int an_supported;
         unsigned int parallel_detect;
+        unsigned int fec_ability;
+
+        unsigned int lpm_ctrl;          /* CTRL1 for resume */
 };
 
 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
@@ -359,7 +417,7 @@ static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
         if (ret < 0)
                 return ret;
 
-        ret |= 0x02;
+        ret |= XGBE_PHY_KR_TRAINING_ENABLE;
         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
 
         return 0;
@@ -373,7 +431,7 @@ static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
         if (ret < 0)
                 return ret;
 
-        ret &= ~0x02;
+        ret &= ~XGBE_PHY_KR_TRAINING_ENABLE;
         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
 
         return 0;
@@ -466,12 +524,16 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
 
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
-        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
-        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
 
-        XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
-        XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
+        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
+                           priv->serdes_cdr_rate[XGBE_PHY_SPEED_10000]);
+        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
+                           priv->serdes_tx_amp[XGBE_PHY_SPEED_10000]);
+        XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
+                           priv->serdes_blwc[XGBE_PHY_SPEED_10000]);
+        XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
+                           priv->serdes_pq_skew[XGBE_PHY_SPEED_10000]);
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
@@ -514,12 +576,16 @@ static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
 
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
-        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
-        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
 
-        XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
-        XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
+        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
+                           priv->serdes_cdr_rate[XGBE_PHY_SPEED_2500]);
+        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
+                           priv->serdes_tx_amp[XGBE_PHY_SPEED_2500]);
+        XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
+                           priv->serdes_blwc[XGBE_PHY_SPEED_2500]);
+        XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
+                           priv->serdes_pq_skew[XGBE_PHY_SPEED_2500]);
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
@@ -562,12 +628,16 @@ static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
 
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
-        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
-        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
 
-        XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
-        XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
+        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
+                           priv->serdes_cdr_rate[XGBE_PHY_SPEED_1000]);
+        XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
+                           priv->serdes_tx_amp[XGBE_PHY_SPEED_1000]);
+        XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
+                           priv->serdes_blwc[XGBE_PHY_SPEED_1000]);
+        XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
+                           priv->serdes_pq_skew[XGBE_PHY_SPEED_1000]);
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
@@ -635,6 +705,38 @@ static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
         return ret;
 }
 
+static int amd_xgbe_phy_set_an(struct phy_device *phydev, bool enable,
+                               bool restart)
+{
+        int ret;
+
+        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
+        if (ret < 0)
+                return ret;
+
+        ret &= ~MDIO_AN_CTRL1_ENABLE;
+
+        if (enable)
+                ret |= MDIO_AN_CTRL1_ENABLE;
+
+        if (restart)
+                ret |= MDIO_AN_CTRL1_RESTART;
+
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
+
+        return 0;
+}
+
+static int amd_xgbe_phy_restart_an(struct phy_device *phydev)
+{
+        return amd_xgbe_phy_set_an(phydev, true, true);
+}
+
+static int amd_xgbe_phy_disable_an(struct phy_device *phydev)
+{
+        return amd_xgbe_phy_set_an(phydev, false, false);
+}
+
 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
                                                     enum amd_xgbe_phy_rx *state)
 {
@@ -645,7 +747,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
 
         /* If we're not in KR mode then we're done */
         if (!amd_xgbe_phy_in_kr_mode(phydev))
-                return AMD_XGBE_AN_EVENT;
+                return AMD_XGBE_AN_PAGE_RECEIVED;
 
         /* Enable/Disable FEC */
         ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
@@ -660,10 +762,9 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
         if (ret < 0)
                 return AMD_XGBE_AN_ERROR;
 
+        ret &= ~XGBE_PHY_FEC_MASK;
         if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
-                ret |= 0x01;
-        else
-                ret &= ~0x01;
+                ret |= priv->fec_ability;
 
         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
 
@@ -672,14 +773,17 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
         if (ret < 0)
                 return AMD_XGBE_AN_ERROR;
 
-        XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
+        if (ret & XGBE_PHY_KR_TRAINING_ENABLE) {
+                XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
 
-        ret |= 0x01;
-        phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
+                ret |= XGBE_PHY_KR_TRAINING_START;
+                phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
+                              ret);
 
-        XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
+                XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
+        }
 
-        return AMD_XGBE_AN_EVENT;
+        return AMD_XGBE_AN_PAGE_RECEIVED;
 }
 
 static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
@@ -696,7 +800,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
 
-        return AMD_XGBE_AN_EVENT;
+        return AMD_XGBE_AN_PAGE_RECEIVED;
 }
 
 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
@@ -735,11 +839,11 @@ static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
         int ad_reg, lp_reg;
 
         /* Check Extended Next Page support */
-        ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
+        ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP);
         if (ad_reg < 0)
                 return AMD_XGBE_AN_ERROR;
 
-        lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
+        lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX);
         if (lp_reg < 0)
                 return AMD_XGBE_AN_ERROR;
 
@@ -748,226 +852,255 @@ static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
                amd_xgbe_an_tx_training(phydev, state);
 }
 
-static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
+static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
+{
+        struct amd_xgbe_phy_priv *priv = phydev->priv;
+        enum amd_xgbe_phy_rx *state;
+        int ret;
+
+        state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
+                                                : &priv->kx_state;
+
+        switch (*state) {
+        case AMD_XGBE_RX_BPA:
+                ret = amd_xgbe_an_rx_bpa(phydev, state);
+                break;
+
+        case AMD_XGBE_RX_XNP:
+                ret = amd_xgbe_an_rx_xnp(phydev, state);
+                break;
+
+        default:
+                ret = AMD_XGBE_AN_ERROR;
+        }
+
+        return ret;
+}
+
+static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         int ret;
 
         /* Be sure we aren't looping trying to negotiate */
         if (amd_xgbe_phy_in_kr_mode(phydev)) {
-                if (priv->kr_state != AMD_XGBE_RX_READY)
+                priv->kr_state = AMD_XGBE_RX_ERROR;
+
+                if (!(phydev->supported & SUPPORTED_1000baseKX_Full) &&
+                    !(phydev->supported & SUPPORTED_2500baseX_Full))
+                        return AMD_XGBE_AN_NO_LINK;
+
+                if (priv->kx_state != AMD_XGBE_RX_BPA)
                         return AMD_XGBE_AN_NO_LINK;
-                priv->kr_state = AMD_XGBE_RX_BPA;
         } else {
-                if (priv->kx_state != AMD_XGBE_RX_READY)
+                priv->kx_state = AMD_XGBE_RX_ERROR;
+
+                if (!(phydev->supported & SUPPORTED_10000baseKR_Full))
+                        return AMD_XGBE_AN_NO_LINK;
+
+                if (priv->kr_state != AMD_XGBE_RX_BPA)
                         return AMD_XGBE_AN_NO_LINK;
-                priv->kx_state = AMD_XGBE_RX_BPA;
         }
 
-        /* Set up Advertisement register 3 first */
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
-        if (ret < 0)
+        ret = amd_xgbe_phy_disable_an(phydev);
+        if (ret)
                 return AMD_XGBE_AN_ERROR;
 
-        if (phydev->supported & SUPPORTED_10000baseR_FEC)
-                ret |= 0xc000;
-        else
-                ret &= ~0xc000;
-
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
-
-        /* Set up Advertisement register 2 next */
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
-        if (ret < 0)
+        ret = amd_xgbe_phy_switch_mode(phydev);
+        if (ret)
                 return AMD_XGBE_AN_ERROR;
 
-        if (phydev->supported & SUPPORTED_10000baseKR_Full)
-                ret |= 0x80;
-        else
-                ret &= ~0x80;
-
-        if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
-            (phydev->supported & SUPPORTED_2500baseX_Full))
-                ret |= 0x20;
-        else
-                ret &= ~0x20;
-
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
-
-        /* Set up Advertisement register 1 last */
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
-        if (ret < 0)
+        ret = amd_xgbe_phy_restart_an(phydev);
+        if (ret)
                 return AMD_XGBE_AN_ERROR;
 
-        if (phydev->supported & SUPPORTED_Pause)
-                ret |= 0x400;
-        else
-                ret &= ~0x400;
+        return AMD_XGBE_AN_INCOMPAT_LINK;
+}
 
-        if (phydev->supported & SUPPORTED_Asym_Pause)
-                ret |= 0x800;
-        else
-                ret &= ~0x800;
+static irqreturn_t amd_xgbe_an_isr(int irq, void *data)
+{
+        struct amd_xgbe_phy_priv *priv = (struct amd_xgbe_phy_priv *)data;
 
-        /* We don't intend to perform XNP */
-        ret &= ~XNP_NP_EXCHANGE;
+        /* Interrupt reason must be read and cleared outside of IRQ context */
+        disable_irq_nosync(priv->an_irq);
 
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
+        queue_work(priv->an_workqueue, &priv->an_irq_work);
 
-        /* Enable and start auto-negotiation */
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+        return IRQ_HANDLED;
+}
 
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
-        if (ret < 0)
-                return AMD_XGBE_AN_ERROR;
+static void amd_xgbe_an_irq_work(struct work_struct *work)
+{
+        struct amd_xgbe_phy_priv *priv = container_of(work,
+                                                      struct amd_xgbe_phy_priv,
+                                                      an_irq_work);
 
-        ret |= MDIO_KR_CTRL_PDETECT;
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
+        /* Avoid a race between enabling the IRQ and exiting the work by
+         * waiting for the work to finish and then queueing it
+         */
+        flush_work(&priv->an_work);
+        queue_work(priv->an_workqueue, &priv->an_work);
+}
 
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
-        if (ret < 0)
-                return AMD_XGBE_AN_ERROR;
+static void amd_xgbe_an_state_machine(struct work_struct *work)
+{
+        struct amd_xgbe_phy_priv *priv = container_of(work,
+                                                      struct amd_xgbe_phy_priv,
+                                                      an_work);
+        struct phy_device *phydev = priv->phydev;
+        enum amd_xgbe_phy_an cur_state = priv->an_state;
+        int int_reg, int_mask;
 
-        ret |= MDIO_AN_CTRL1_ENABLE;
-        ret |= MDIO_AN_CTRL1_RESTART;
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
+        mutex_lock(&priv->an_mutex);
 
-        return AMD_XGBE_AN_EVENT;
-}
+        /* Read the interrupt */
+        int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
+        if (!int_reg)
+                goto out;
 
-static enum amd_xgbe_phy_an amd_xgbe_an_event(struct phy_device *phydev)
-{
-        enum amd_xgbe_phy_an new_state;
-        int ret;
+next_int:
+        if (int_reg < 0) {
+                priv->an_state = AMD_XGBE_AN_ERROR;
+                int_mask = XGBE_AN_INT_MASK;
+        } else if (int_reg & XGBE_AN_PG_RCV) {
+                priv->an_state = AMD_XGBE_AN_PAGE_RECEIVED;
+                int_mask = XGBE_AN_PG_RCV;
+        } else if (int_reg & XGBE_AN_INC_LINK) {
+                priv->an_state = AMD_XGBE_AN_INCOMPAT_LINK;
+                int_mask = XGBE_AN_INC_LINK;
+        } else if (int_reg & XGBE_AN_INT_CMPLT) {
+                priv->an_state = AMD_XGBE_AN_COMPLETE;
+                int_mask = XGBE_AN_INT_CMPLT;
+        } else {
+                priv->an_state = AMD_XGBE_AN_ERROR;
+                int_mask = 0;
+        }
 
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
-        if (ret < 0)
-                return AMD_XGBE_AN_ERROR;
+        /* Clear the interrupt to be processed */
+        int_reg &= ~int_mask;
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg);
 
-        new_state = AMD_XGBE_AN_EVENT;
-        if (ret & XGBE_AN_PG_RCV)
-                new_state = AMD_XGBE_AN_PAGE_RECEIVED;
-        else if (ret & XGBE_AN_INC_LINK)
-                new_state = AMD_XGBE_AN_INCOMPAT_LINK;
-        else if (ret & XGBE_AN_INT_CMPLT)
-                new_state = AMD_XGBE_AN_COMPLETE;
+        priv->an_result = priv->an_state;
 
-        if (new_state != AMD_XGBE_AN_EVENT)
-                phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+again:
+        cur_state = priv->an_state;
 
-        return new_state;
-}
+        switch (priv->an_state) {
+        case AMD_XGBE_AN_READY:
+                priv->an_supported = 0;
+                break;
 
-static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
-{
-        struct amd_xgbe_phy_priv *priv = phydev->priv;
-        enum amd_xgbe_phy_rx *state;
-        int ret;
+        case AMD_XGBE_AN_PAGE_RECEIVED:
+                priv->an_state = amd_xgbe_an_page_received(phydev);
+                priv->an_supported++;
+                break;
 
-        state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
-                                                : &priv->kx_state;
+        case AMD_XGBE_AN_INCOMPAT_LINK:
+                priv->an_supported = 0;
+                priv->parallel_detect = 0;
+                priv->an_state = amd_xgbe_an_incompat_link(phydev);
+                break;
 
-        switch (*state) {
-        case AMD_XGBE_RX_BPA:
-                ret = amd_xgbe_an_rx_bpa(phydev, state);
+        case AMD_XGBE_AN_COMPLETE:
+                priv->parallel_detect = priv->an_supported ? 0 : 1;
+                netdev_dbg(phydev->attached_dev, "%s successful\n",
+                           priv->an_supported ? "Auto negotiation"
+                                              : "Parallel detection");
                 break;
 
-        case AMD_XGBE_RX_XNP:
-                ret = amd_xgbe_an_rx_xnp(phydev, state);
+        case AMD_XGBE_AN_NO_LINK:
                 break;
 
         default:
-                ret = AMD_XGBE_AN_ERROR;
+                priv->an_state = AMD_XGBE_AN_ERROR;
         }
 
-        return ret;
-}
+        if (priv->an_state == AMD_XGBE_AN_NO_LINK) {
+                int_reg = 0;
+                phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+        } else if (priv->an_state == AMD_XGBE_AN_ERROR) {
+                netdev_err(phydev->attached_dev,
+                           "error during auto-negotiation, state=%u\n",
+                           cur_state);
 
-static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
-{
-        int ret;
+                int_reg = 0;
+                phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+        }
 
-        ret = amd_xgbe_phy_switch_mode(phydev);
-        if (ret)
-                return AMD_XGBE_AN_ERROR;
+        if (priv->an_state >= AMD_XGBE_AN_COMPLETE) {
+                priv->an_result = priv->an_state;
+                priv->an_state = AMD_XGBE_AN_READY;
+                priv->kr_state = AMD_XGBE_RX_BPA;
+                priv->kx_state = AMD_XGBE_RX_BPA;
+        }
 
-        return AMD_XGBE_AN_START;
-}
+        if (cur_state != priv->an_state)
+                goto again;
 
-static void amd_xgbe_an_state_machine(struct work_struct *work)
-{
-        struct amd_xgbe_phy_priv *priv = container_of(work,
-                                                      struct amd_xgbe_phy_priv,
-                                                      an_work);
-        struct phy_device *phydev = priv->phydev;
-        enum amd_xgbe_phy_an cur_state;
-        int sleep;
-        unsigned int an_supported = 0;
+        if (int_reg)
+                goto next_int;
 
-        /* Start in KX mode */
-        if (amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX))
-                priv->an_state = AMD_XGBE_AN_ERROR;
+out:
+        enable_irq(priv->an_irq);
 
-        while (1) {
-                mutex_lock(&priv->an_mutex);
+        mutex_unlock(&priv->an_mutex);
+}
 
-                cur_state = priv->an_state;
+static int amd_xgbe_an_init(struct phy_device *phydev)
+{
+        int ret;
 
-                switch (priv->an_state) {
-                case AMD_XGBE_AN_START:
-                        an_supported = 0;
-                        priv->parallel_detect = 0;
-                        priv->an_state = amd_xgbe_an_start(phydev);
-                        break;
+        /* Set up Advertisement register 3 first */
+        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
+        if (ret < 0)
+                return ret;
 
-                case AMD_XGBE_AN_EVENT:
-                        priv->an_state = amd_xgbe_an_event(phydev);
-                        break;
+        if (phydev->supported & SUPPORTED_10000baseR_FEC)
+                ret |= 0xc000;
+        else
+                ret &= ~0xc000;
 
-                case AMD_XGBE_AN_PAGE_RECEIVED:
-                        priv->an_state = amd_xgbe_an_page_received(phydev);
-                        an_supported++;
-                        break;
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
 
-                case AMD_XGBE_AN_INCOMPAT_LINK:
-                        priv->an_state = amd_xgbe_an_incompat_link(phydev);
-                        break;
+        /* Set up Advertisement register 2 next */
+        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
+        if (ret < 0)
+                return ret;
 
-                case AMD_XGBE_AN_COMPLETE:
-                        priv->parallel_detect = an_supported ? 0 : 1;
-                        netdev_info(phydev->attached_dev, "%s successful\n",
-                                    an_supported ? "Auto negotiation"
-                                                 : "Parallel detection");
-                        /* fall through */
+        if (phydev->supported & SUPPORTED_10000baseKR_Full)
+                ret |= 0x80;
+        else
+                ret &= ~0x80;
 
-                case AMD_XGBE_AN_NO_LINK:
-                case AMD_XGBE_AN_EXIT:
-                        goto exit_unlock;
+        if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
+            (phydev->supported & SUPPORTED_2500baseX_Full))
+                ret |= 0x20;
+        else
+                ret &= ~0x20;
 
-                default:
-                        priv->an_state = AMD_XGBE_AN_ERROR;
-                }
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
 
-                if (priv->an_state == AMD_XGBE_AN_ERROR) {
-                        netdev_err(phydev->attached_dev,
-                                   "error during auto-negotiation, state=%u\n",
-                                   cur_state);
-                        goto exit_unlock;
-                }
+        /* Set up Advertisement register 1 last */
+        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
+        if (ret < 0)
+                return ret;
 
-                sleep = (priv->an_state == AMD_XGBE_AN_EVENT) ? 1 : 0;
+        if (phydev->supported & SUPPORTED_Pause)
+                ret |= 0x400;
+        else
+                ret &= ~0x400;
 
-                mutex_unlock(&priv->an_mutex);
+        if (phydev->supported & SUPPORTED_Asym_Pause)
+                ret |= 0x800;
+        else
+                ret &= ~0x800;
 
-                if (sleep)
-                        usleep_range(20, 50);
-        }
+        /* We don't intend to perform XNP */
+        ret &= ~XNP_NP_EXCHANGE;
 
-exit_unlock:
-        priv->an_result = priv->an_state;
-        priv->an_state = AMD_XGBE_AN_READY;
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
 
-        mutex_unlock(&priv->an_mutex);
+        return 0;
 }
 
 static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
@@ -992,20 +1125,57 @@ static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
         if (ret & MDIO_CTRL1_RESET)
                 return -ETIMEDOUT;
 
-        /* Make sure the XPCS and SerDes are in compatible states */
-        return amd_xgbe_phy_xgmii_mode(phydev);
+        /* Disable auto-negotiation for now */
+        ret = amd_xgbe_phy_disable_an(phydev);
+        if (ret < 0)
+                return ret;
+
+        /* Clear auto-negotiation interrupts */
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+
+        return 0;
 }
 
 static int amd_xgbe_phy_config_init(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
+        struct net_device *netdev = phydev->attached_dev;
+        int ret;
+
+        if (!priv->an_irq_allocated) {
+                /* Allocate the auto-negotiation workqueue and interrupt */
+                snprintf(priv->an_irq_name, sizeof(priv->an_irq_name) - 1,
+                         "%s-pcs", netdev_name(netdev));
+
+                priv->an_workqueue =
+                        create_singlethread_workqueue(priv->an_irq_name);
+                if (!priv->an_workqueue) {
+                        netdev_err(netdev, "phy workqueue creation failed\n");
+                        return -ENOMEM;
+                }
+
+                ret = devm_request_irq(priv->dev, priv->an_irq,
+                                       amd_xgbe_an_isr, 0, priv->an_irq_name,
+                                       priv);
+                if (ret) {
+                        netdev_err(netdev, "phy irq request failed\n");
+                        destroy_workqueue(priv->an_workqueue);
+                        return ret;
+                }
+
+                priv->an_irq_allocated = 1;
+        }
+
+        ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY);
+        if (ret < 0)
+                return ret;
+        priv->fec_ability = ret & XGBE_PHY_FEC_MASK;
 
         /* Initialize supported features */
         phydev->supported = SUPPORTED_Autoneg;
         phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
         phydev->supported |= SUPPORTED_Backplane;
-        phydev->supported |= SUPPORTED_10000baseKR_Full |
-                             SUPPORTED_10000baseR_FEC;
+        phydev->supported |= SUPPORTED_10000baseKR_Full;
         switch (priv->speed_set) {
         case AMD_XGBE_PHY_SPEEDSET_1000_10000:
                 phydev->supported |= SUPPORTED_1000baseKX_Full;
@@ -1014,11 +1184,33 @@ static int amd_xgbe_phy_config_init(struct phy_device *phydev)
                 phydev->supported |= SUPPORTED_2500baseX_Full;
                 break;
         }
+
+        if (priv->fec_ability & XGBE_PHY_FEC_ENABLE)
+                phydev->supported |= SUPPORTED_10000baseR_FEC;
+
         phydev->advertising = phydev->supported;
 
-        /* Turn off and clear interrupts */
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+        /* Set initial mode - call the mode setting routines
+         * directly to insure we are properly configured
+         */
+        if (phydev->supported & SUPPORTED_10000baseKR_Full)
+                ret = amd_xgbe_phy_xgmii_mode(phydev);
+        else if (phydev->supported & SUPPORTED_1000baseKX_Full)
+                ret = amd_xgbe_phy_gmii_mode(phydev);
+        else if (phydev->supported & SUPPORTED_2500baseX_Full)
+                ret = amd_xgbe_phy_gmii_2500_mode(phydev);
+        else
+                ret = -EINVAL;
+        if (ret < 0)
+                return ret;
+
+        /* Set up advertisement registers based on current settings */
+        ret = amd_xgbe_an_init(phydev);
+        if (ret)
+                return ret;
+
+        /* Enable auto-negotiation interrupts */
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
 
         return 0;
 }
@@ -1028,25 +1220,19 @@ static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
         int ret;
 
         /* Disable auto-negotiation */
-        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
+        ret = amd_xgbe_phy_disable_an(phydev);
         if (ret < 0)
                 return ret;
 
-        ret &= ~MDIO_AN_CTRL1_ENABLE;
-        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
-
         /* Validate/Set specified speed */
         switch (phydev->speed) {
         case SPEED_10000:
-                ret = amd_xgbe_phy_xgmii_mode(phydev);
+                ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
                 break;
 
         case SPEED_2500:
-                ret = amd_xgbe_phy_gmii_2500_mode(phydev);
-                break;
-
         case SPEED_1000:
-                ret = amd_xgbe_phy_gmii_mode(phydev);
+                ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
                 break;
 
         default:
@@ -1066,10 +1252,11 @@ static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
         return 0;
 }
 
-static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
+static int __amd_xgbe_phy_config_aneg(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         u32 mmd_mask = phydev->c45_ids.devices_in_package;
+        int ret;
 
         if (phydev->autoneg != AUTONEG_ENABLE)
                 return amd_xgbe_phy_setup_forced(phydev);
@@ -1078,56 +1265,79 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
         if (!(mmd_mask & MDIO_DEVS_AN))
                 return -EINVAL;
 
-        /* Start/Restart the auto-negotiation state machine */
-        mutex_lock(&priv->an_mutex);
+        /* Disable auto-negotiation interrupt */
+        disable_irq(priv->an_irq);
+
+        /* Start auto-negotiation in a supported mode */
+        if (phydev->supported & SUPPORTED_10000baseKR_Full)
+                ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
+        else if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
+                 (phydev->supported & SUPPORTED_2500baseX_Full))
+                ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
+        else
+                ret = -EINVAL;
+        if (ret < 0) {
+                enable_irq(priv->an_irq);
+                return ret;
+        }
+
+        /* Disable and stop any in progress auto-negotiation */
+        ret = amd_xgbe_phy_disable_an(phydev);
+        if (ret < 0)
+                return ret;
+
+        /* Clear any auto-negotitation interrupts */
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
+
         priv->an_result = AMD_XGBE_AN_READY;
-        priv->an_state = AMD_XGBE_AN_START;
-        priv->kr_state = AMD_XGBE_RX_READY;
-        priv->kx_state = AMD_XGBE_RX_READY;
-        mutex_unlock(&priv->an_mutex);
+        priv->an_state = AMD_XGBE_AN_READY;
+        priv->kr_state = AMD_XGBE_RX_BPA;
+        priv->kx_state = AMD_XGBE_RX_BPA;
 
-        queue_work(priv->an_workqueue, &priv->an_work);
+        /* Re-enable auto-negotiation interrupt */
+        enable_irq(priv->an_irq);
 
-        return 0;
+        /* Set up advertisement registers based on current settings */
+        ret = amd_xgbe_an_init(phydev);
+        if (ret)
+                return ret;
+
+        /* Enable and start auto-negotiation */
+        return amd_xgbe_phy_restart_an(phydev);
 }
 
-static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
+static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
-        enum amd_xgbe_phy_an state;
+        int ret;
 
         mutex_lock(&priv->an_mutex);
-        state = priv->an_result;
+
+        ret = __amd_xgbe_phy_config_aneg(phydev);
+
         mutex_unlock(&priv->an_mutex);
 
-        return (state == AMD_XGBE_AN_COMPLETE);
+        return ret;
+}
+
+static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
+{
+        struct amd_xgbe_phy_priv *priv = phydev->priv;
+
+        return (priv->an_result == AMD_XGBE_AN_COMPLETE);
 }
 
 static int amd_xgbe_phy_update_link(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
-        enum amd_xgbe_phy_an state;
-        unsigned int check_again, autoneg;
         int ret;
 
         /* If we're doing auto-negotiation don't report link down */
-        mutex_lock(&priv->an_mutex);
-        state = priv->an_state;
-        mutex_unlock(&priv->an_mutex);
-
-        if (state != AMD_XGBE_AN_READY) {
+        if (priv->an_state != AMD_XGBE_AN_READY) {
                 phydev->link = 1;
                 return 0;
         }
 
-        /* Since the device can be in the wrong mode when a link is
-         * (re-)established (cable connected after the interface is
-         * up, etc.), the link status may report no link. If there
-         * is no link, try switching modes and checking the status
-         * again if auto negotiation is enabled.
-         */
-        check_again = (phydev->autoneg == AUTONEG_ENABLE) ? 1 : 0;
-again:
         /* Link status is latched low, so read once to clear
          * and then read again to get current state
          */
@@ -1141,25 +1351,6 @@ again:
 
         phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
 
-        if (!phydev->link) {
-                if (check_again) {
-                        ret = amd_xgbe_phy_switch_mode(phydev);
-                        if (ret < 0)
-                                return ret;
-                        check_again = 0;
-                        goto again;
-                }
-        }
-
-        autoneg = (phydev->link && !priv->link) ? 1 : 0;
-        priv->link = phydev->link;
-        if (autoneg) {
-                /* Link is (back) up, re-start auto-negotiation */
-                ret = amd_xgbe_phy_config_aneg(phydev);
-                if (ret < 0)
-                        return ret;
-        }
-
         return 0;
 }
 
@@ -1249,6 +1440,7 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
 
 static int amd_xgbe_phy_suspend(struct phy_device *phydev)
 {
+        struct amd_xgbe_phy_priv *priv = phydev->priv;
         int ret;
 
         mutex_lock(&phydev->lock);
@@ -1257,6 +1449,8 @@ static int amd_xgbe_phy_suspend(struct phy_device *phydev)
         if (ret < 0)
                 goto unlock;
 
+        priv->lpm_ctrl = ret;
+
         ret |= MDIO_CTRL1_LPOWER;
         phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
 
@@ -1270,69 +1464,106 @@ unlock:
 
 static int amd_xgbe_phy_resume(struct phy_device *phydev)
 {
-        int ret;
+        struct amd_xgbe_phy_priv *priv = phydev->priv;
 
         mutex_lock(&phydev->lock);
 
-        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
-        if (ret < 0)
-                goto unlock;
+        priv->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
+        phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, priv->lpm_ctrl);
 
-        ret &= ~MDIO_CTRL1_LPOWER;
-        phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
+        mutex_unlock(&phydev->lock);
 
-        ret = 0;
+        return 0;
+}
 
-unlock:
-        mutex_unlock(&phydev->lock);
+static unsigned int amd_xgbe_phy_resource_count(struct platform_device *pdev,
+                                                unsigned int type)
+{
+        unsigned int count;
+        int i;
 
-        return ret;
+        for (i = 0, count = 0; i < pdev->num_resources; i++) {
+                struct resource *r = &pdev->resource[i];
+
+                if (type == resource_type(r))
+                        count++;
+        }
+
+        return count;
 }
 
 static int amd_xgbe_phy_probe(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv;
-        struct platform_device *pdev;
-        struct device *dev;
-        char *wq_name;
-        const __be32 *property;
-        unsigned int speed_set;
+        struct platform_device *phy_pdev;
+        struct device *dev, *phy_dev;
+        unsigned int phy_resnum, phy_irqnum;
         int ret;
 
-        if (!phydev->dev.of_node)
+        if (!phydev->bus || !phydev->bus->parent)
                 return -EINVAL;
 
-        pdev = of_find_device_by_node(phydev->dev.of_node);
-        if (!pdev)
-                return -EINVAL;
-        dev = &pdev->dev;
-
-        wq_name = kasprintf(GFP_KERNEL, "%s-amd-xgbe-phy", phydev->bus->name);
-        if (!wq_name) {
-                ret = -ENOMEM;
-                goto err_pdev;
-        }
+        dev = phydev->bus->parent;
 
         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-        if (!priv) {
-                ret = -ENOMEM;
-                goto err_name;
-        }
+        if (!priv)
+                return -ENOMEM;
 
-        priv->pdev = pdev;
+        priv->pdev = to_platform_device(dev);
+        priv->adev = ACPI_COMPANION(dev);
         priv->dev = dev;
         priv->phydev = phydev;
+        mutex_init(&priv->an_mutex);
+        INIT_WORK(&priv->an_irq_work, amd_xgbe_an_irq_work);
+        INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
+
+        if (!priv->adev || acpi_disabled) {
+                struct device_node *bus_node;
+                struct device_node *phy_node;
+
+                bus_node = priv->dev->of_node;
+                phy_node = of_parse_phandle(bus_node, "phy-handle", 0);
+                if (!phy_node) {
+                        dev_err(dev, "unable to parse phy-handle\n");
+                        ret = -EINVAL;
+                        goto err_priv;
+                }
+
+                phy_pdev = of_find_device_by_node(phy_node);
+                of_node_put(phy_node);
+
+                if (!phy_pdev) {
+                        dev_err(dev, "unable to obtain phy device\n");
+                        ret = -EINVAL;
+                        goto err_priv;
+                }
+
+                phy_resnum = 0;
+                phy_irqnum = 0;
+        } else {
+                /* In ACPI, the XGBE and PHY resources are the grouped
+                 * together with the PHY resources at the end
+                 */
+                phy_pdev = priv->pdev;
+                phy_resnum = amd_xgbe_phy_resource_count(phy_pdev,
+                                                         IORESOURCE_MEM) - 3;
+                phy_irqnum = amd_xgbe_phy_resource_count(phy_pdev,
+                                                         IORESOURCE_IRQ) - 1;
+        }
+        phy_dev = &phy_pdev->dev;
 
         /* Get the device mmio areas */
-        priv->rxtx_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
+                                               phy_resnum++);
         priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
         if (IS_ERR(priv->rxtx_regs)) {
                 dev_err(dev, "rxtx ioremap failed\n");
                 ret = PTR_ERR(priv->rxtx_regs);
-                goto err_priv;
+                goto err_put;
         }
 
-        priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        priv->sir0_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
+                                               phy_resnum++);
         priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
         if (IS_ERR(priv->sir0_regs)) {
                 dev_err(dev, "sir0 ioremap failed\n");
@@ -1340,7 +1571,8 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
                 goto err_rxtx;
         }
 
-        priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+        priv->sir1_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
+                                               phy_resnum++);
         priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
         if (IS_ERR(priv->sir1_regs)) {
                 dev_err(dev, "sir1 ioremap failed\n");
@@ -1348,40 +1580,98 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
                 goto err_sir0;
         }
 
+        /* Get the auto-negotiation interrupt */
+        ret = platform_get_irq(phy_pdev, phy_irqnum);
+        if (ret < 0) {
+                dev_err(dev, "platform_get_irq failed\n");
+                goto err_sir1;
+        }
+        priv->an_irq = ret;
+
         /* Get the device speed set property */
-        speed_set = 0;
-        property = of_get_property(dev->of_node, XGBE_PHY_SPEEDSET_PROPERTY,
-                                   NULL);
-        if (property)
-                speed_set = be32_to_cpu(*property);
-
-        switch (speed_set) {
-        case 0:
-                priv->speed_set = AMD_XGBE_PHY_SPEEDSET_1000_10000;
-                break;
-        case 1:
-                priv->speed_set = AMD_XGBE_PHY_SPEEDSET_2500_10000;
+        ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY,
+                                       &priv->speed_set);
+        if (ret) {
+                dev_err(dev, "invalid %s property\n",
+                        XGBE_PHY_SPEEDSET_PROPERTY);
+                goto err_sir1;
+        }
+
+        switch (priv->speed_set) {
+        case AMD_XGBE_PHY_SPEEDSET_1000_10000:
+        case AMD_XGBE_PHY_SPEEDSET_2500_10000:
                 break;
         default:
-                dev_err(dev, "invalid amd,speed-set property\n");
+                dev_err(dev, "invalid %s property\n",
+                        XGBE_PHY_SPEEDSET_PROPERTY);
                 ret = -EINVAL;
                 goto err_sir1;
         }
 
-        priv->link = 1;
+        if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) {
+                ret = device_property_read_u32_array(phy_dev,
+                                                     XGBE_PHY_BLWC_PROPERTY,
+                                                     priv->serdes_blwc,
+                                                     XGBE_PHY_SPEEDS);
+                if (ret) {
+                        dev_err(dev, "invalid %s property\n",
+                                XGBE_PHY_BLWC_PROPERTY);
+                        goto err_sir1;
+                }
+        } else {
+                memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc,
+                       sizeof(priv->serdes_blwc));
+        }
 
-        mutex_init(&priv->an_mutex);
-        INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
-        priv->an_workqueue = create_singlethread_workqueue(wq_name);
-        if (!priv->an_workqueue) {
-                ret = -ENOMEM;
-                goto err_sir1;
+        if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) {
+                ret = device_property_read_u32_array(phy_dev,
+                                                     XGBE_PHY_CDR_RATE_PROPERTY,
+                                                     priv->serdes_cdr_rate,
+                                                     XGBE_PHY_SPEEDS);
+                if (ret) {
+                        dev_err(dev, "invalid %s property\n",
+                                XGBE_PHY_CDR_RATE_PROPERTY);
+                        goto err_sir1;
+                }
+        } else {
+                memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate,
+                       sizeof(priv->serdes_cdr_rate));
+        }
+
+        if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) {
+                ret = device_property_read_u32_array(phy_dev,
+                                                     XGBE_PHY_PQ_SKEW_PROPERTY,
+                                                     priv->serdes_pq_skew,
+                                                     XGBE_PHY_SPEEDS);
+                if (ret) {
+                        dev_err(dev, "invalid %s property\n",
+                                XGBE_PHY_PQ_SKEW_PROPERTY);
+                        goto err_sir1;
+                }
+        } else {
+                memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew,
+                       sizeof(priv->serdes_pq_skew));
+        }
+
+        if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) {
+                ret = device_property_read_u32_array(phy_dev,
+                                                     XGBE_PHY_TX_AMP_PROPERTY,
+                                                     priv->serdes_tx_amp,
+                                                     XGBE_PHY_SPEEDS);
+                if (ret) {
+                        dev_err(dev, "invalid %s property\n",
+                                XGBE_PHY_TX_AMP_PROPERTY);
+                        goto err_sir1;
+                }
+        } else {
+                memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp,
+                       sizeof(priv->serdes_tx_amp));
         }
 
         phydev->priv = priv;
 
-        kfree(wq_name);
-        of_dev_put(pdev);
+        if (!priv->adev || acpi_disabled)
+                platform_device_put(phy_pdev);
 
         return 0;
 
@@ -1400,15 +1690,13 @@ err_rxtx:
         devm_release_mem_region(dev, priv->rxtx_res->start,
                                 resource_size(priv->rxtx_res));
 
+err_put:
+        if (!priv->adev || acpi_disabled)
+                platform_device_put(phy_pdev);
+
 err_priv:
         devm_kfree(dev, priv);
 
-err_name:
-        kfree(wq_name);
-
-err_pdev:
-        of_dev_put(pdev);
-
         return ret;
 }
 
@@ -1417,13 +1705,12 @@ static void amd_xgbe_phy_remove(struct phy_device *phydev)
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         struct device *dev = priv->dev;
 
-        /* Stop any in process auto-negotiation */
-        mutex_lock(&priv->an_mutex);
-        priv->an_state = AMD_XGBE_AN_EXIT;
-        mutex_unlock(&priv->an_mutex);
+        if (priv->an_irq_allocated) {
+                devm_free_irq(dev, priv->an_irq, priv);
 
-        flush_workqueue(priv->an_workqueue);
-        destroy_workqueue(priv->an_workqueue);
+                flush_workqueue(priv->an_workqueue);
+                destroy_workqueue(priv->an_workqueue);
+        }
 
         /* Release resources */
         devm_iounmap(dev, priv->sir1_regs);