diff options
Diffstat (limited to 'drivers/net/niu.h')
| -rw-r--r-- | drivers/net/niu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/niu.h b/drivers/net/niu.h index c6fa883daa22..180ca8ae93de 100644 --- a/drivers/net/niu.h +++ b/drivers/net/niu.h | |||
| @@ -1048,6 +1048,13 @@ | |||
| 1048 | #define PLL_CFG_LD_SHIFT 8 | 1048 | #define PLL_CFG_LD_SHIFT 8 |
| 1049 | #define PLL_CFG_MPY 0x0000001e | 1049 | #define PLL_CFG_MPY 0x0000001e |
| 1050 | #define PLL_CFG_MPY_SHIFT 1 | 1050 | #define PLL_CFG_MPY_SHIFT 1 |
| 1051 | #define PLL_CFG_MPY_4X 0x0 | ||
| 1052 | #define PLL_CFG_MPY_5X 0x00000002 | ||
| 1053 | #define PLL_CFG_MPY_6X 0x00000004 | ||
| 1054 | #define PLL_CFG_MPY_8X 0x00000008 | ||
| 1055 | #define PLL_CFG_MPY_10X 0x0000000a | ||
| 1056 | #define PLL_CFG_MPY_12X 0x0000000c | ||
| 1057 | #define PLL_CFG_MPY_12P5X 0x0000000e | ||
| 1051 | #define PLL_CFG_ENPLL 0x00000001 | 1058 | #define PLL_CFG_ENPLL 0x00000001 |
| 1052 | 1059 | ||
| 1053 | #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002) | 1060 | #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002) |
| @@ -1093,6 +1100,9 @@ | |||
| 1093 | #define PLL_TX_CFG_INVPAIR 0x00000080 | 1100 | #define PLL_TX_CFG_INVPAIR 0x00000080 |
| 1094 | #define PLL_TX_CFG_RATE 0x00000060 | 1101 | #define PLL_TX_CFG_RATE 0x00000060 |
| 1095 | #define PLL_TX_CFG_RATE_SHIFT 5 | 1102 | #define PLL_TX_CFG_RATE_SHIFT 5 |
| 1103 | #define PLL_TX_CFG_RATE_FULL 0x0 | ||
| 1104 | #define PLL_TX_CFG_RATE_HALF 0x20 | ||
| 1105 | #define PLL_TX_CFG_RATE_QUAD 0x40 | ||
| 1096 | #define PLL_TX_CFG_BUSWIDTH 0x0000001c | 1106 | #define PLL_TX_CFG_BUSWIDTH 0x0000001c |
| 1097 | #define PLL_TX_CFG_BUSWIDTH_SHIFT 2 | 1107 | #define PLL_TX_CFG_BUSWIDTH_SHIFT 2 |
| 1098 | #define PLL_TX_CFG_ENTEST 0x00000002 | 1108 | #define PLL_TX_CFG_ENTEST 0x00000002 |
| @@ -1132,6 +1142,9 @@ | |||
| 1132 | #define PLL_RX_CFG_INVPAIR 0x00000080 | 1142 | #define PLL_RX_CFG_INVPAIR 0x00000080 |
| 1133 | #define PLL_RX_CFG_RATE 0x00000060 | 1143 | #define PLL_RX_CFG_RATE 0x00000060 |
| 1134 | #define PLL_RX_CFG_RATE_SHIFT 5 | 1144 | #define PLL_RX_CFG_RATE_SHIFT 5 |
| 1145 | #define PLL_RX_CFG_RATE_FULL 0x0 | ||
| 1146 | #define PLL_RX_CFG_RATE_HALF 0x20 | ||
| 1147 | #define PLL_RX_CFG_RATE_QUAD 0x40 | ||
| 1135 | #define PLL_RX_CFG_BUSWIDTH 0x0000001c | 1148 | #define PLL_RX_CFG_BUSWIDTH 0x0000001c |
| 1136 | #define PLL_RX_CFG_BUSWIDTH_SHIFT 2 | 1149 | #define PLL_RX_CFG_BUSWIDTH_SHIFT 2 |
| 1137 | #define PLL_RX_CFG_ENTEST 0x00000002 | 1150 | #define PLL_RX_CFG_ENTEST 0x00000002 |