aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/netxen
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/netxen')
-rw-r--r--drivers/net/netxen/netxen_nic.h594
-rw-r--r--drivers/net/netxen/netxen_nic_ctx.c204
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c105
-rw-r--r--drivers/net/netxen/netxen_nic_hdr.h8
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c393
-rw-r--r--drivers/net/netxen/netxen_nic_hw.h66
-rw-r--r--drivers/net/netxen/netxen_nic_init.c291
-rw-r--r--drivers/net/netxen/netxen_nic_main.c268
-rw-r--r--drivers/net/netxen/netxen_nic_niu.c203
-rw-r--r--drivers/net/netxen/netxen_nic_phan_reg.h27
10 files changed, 1023 insertions, 1136 deletions
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index c40815169f35..ebd6c2edc343 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -34,10 +34,6 @@
34#include <linux/module.h> 34#include <linux/module.h>
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/types.h> 36#include <linux/types.h>
37#include <linux/compiler.h>
38#include <linux/slab.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41#include <linux/ioport.h> 37#include <linux/ioport.h>
42#include <linux/pci.h> 38#include <linux/pci.h>
43#include <linux/netdevice.h> 39#include <linux/netdevice.h>
@@ -49,18 +45,12 @@
49 45
50#include <linux/ethtool.h> 46#include <linux/ethtool.h>
51#include <linux/mii.h> 47#include <linux/mii.h>
52#include <linux/interrupt.h>
53#include <linux/timer.h> 48#include <linux/timer.h>
54 49
55#include <linux/mm.h>
56#include <linux/mman.h>
57#include <linux/vmalloc.h> 50#include <linux/vmalloc.h>
58 51
59#include <asm/system.h>
60#include <asm/io.h> 52#include <asm/io.h>
61#include <asm/byteorder.h> 53#include <asm/byteorder.h>
62#include <asm/uaccess.h>
63#include <asm/pgtable.h>
64 54
65#include "netxen_nic_hw.h" 55#include "netxen_nic_hw.h"
66 56
@@ -84,10 +74,10 @@
84 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) 74 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
85#define STATUS_DESC_RINGSIZE(sds_ring) \ 75#define STATUS_DESC_RINGSIZE(sds_ring) \
86 (sizeof(struct status_desc) * (sds_ring)->num_desc) 76 (sizeof(struct status_desc) * (sds_ring)->num_desc)
87#define TX_BUFF_RINGSIZE(adapter) \ 77#define TX_BUFF_RINGSIZE(tx_ring) \
88 (sizeof(struct netxen_cmd_buffer) * adapter->num_txd) 78 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
89#define TX_DESC_RINGSIZE(adapter) \ 79#define TX_DESC_RINGSIZE(tx_ring) \
90 (sizeof(struct cmd_desc_type0) * adapter->num_txd) 80 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
91 81
92#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) 82#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
93 83
@@ -118,6 +108,7 @@
118#define NX_P3_A2 0x30 108#define NX_P3_A2 0x30
119#define NX_P3_B0 0x40 109#define NX_P3_B0 0x40
120#define NX_P3_B1 0x41 110#define NX_P3_B1 0x41
111#define NX_P3_B2 0x42
121 112
122#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) 113#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
123#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) 114#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
@@ -203,18 +194,10 @@
203#define MAX_RCV_DESCRIPTORS_10G 4096 194#define MAX_RCV_DESCRIPTORS_10G 4096
204#define MAX_JUMBO_RCV_DESCRIPTORS 1024 195#define MAX_JUMBO_RCV_DESCRIPTORS 1024
205#define MAX_LRO_RCV_DESCRIPTORS 8 196#define MAX_LRO_RCV_DESCRIPTORS 8
206#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
207#define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
208#define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
209#define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
210#define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
211#define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
212 MAX_LRO_RCV_DESCRIPTORS)
213#define MIN_TX_COUNT 4096
214#define MIN_RX_COUNT 4096
215#define NETXEN_CTX_SIGNATURE 0xdee0 197#define NETXEN_CTX_SIGNATURE 0xdee0
198#define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
199#define NETXEN_CTX_RESET 0xbad0
216#define NETXEN_RCV_PRODUCER(ringid) (ringid) 200#define NETXEN_RCV_PRODUCER(ringid) (ringid)
217#define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
218 201
219#define PHAN_PEG_RCV_INITIALIZED 0xff01 202#define PHAN_PEG_RCV_INITIALIZED 0xff01
220#define PHAN_PEG_RCV_START_INITIALIZE 0xff00 203#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
@@ -253,12 +236,19 @@ typedef u32 netxen_ctx_msg;
253#define netxen_set_msg_opcode(config_word, val) \ 236#define netxen_set_msg_opcode(config_word, val) \
254 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) 237 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
255 238
256struct netxen_rcv_context { 239struct netxen_rcv_ring {
257 __le64 rcv_ring_addr; 240 __le64 addr;
258 __le32 rcv_ring_size; 241 __le32 size;
259 __le32 rsrvd; 242 __le32 rsrvd;
260}; 243};
261 244
245struct netxen_sts_ring {
246 __le64 addr;
247 __le32 size;
248 __le16 msi_index;
249 __le16 rsvd;
250} ;
251
262struct netxen_ring_ctx { 252struct netxen_ring_ctx {
263 253
264 /* one command ring */ 254 /* one command ring */
@@ -268,13 +258,18 @@ struct netxen_ring_ctx {
268 __le32 rsrvd; 258 __le32 rsrvd;
269 259
270 /* three receive rings */ 260 /* three receive rings */
271 struct netxen_rcv_context rcv_ctx[3]; 261 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
272 262
273 /* one status ring */
274 __le64 sts_ring_addr; 263 __le64 sts_ring_addr;
275 __le32 sts_ring_size; 264 __le32 sts_ring_size;
276 265
277 __le32 ctx_id; 266 __le32 ctx_id;
267
268 __le64 rsrvd_2[3];
269 __le32 sts_ring_count;
270 __le32 rsrvd_3;
271 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
272
278} __attribute__ ((aligned(64))); 273} __attribute__ ((aligned(64)));
279 274
280/* 275/*
@@ -373,6 +368,7 @@ struct rcv_desc {
373/* opcode field in status_desc */ 368/* opcode field in status_desc */
374#define NETXEN_NIC_RXPKT_DESC 0x04 369#define NETXEN_NIC_RXPKT_DESC 0x04
375#define NETXEN_OLD_RXPKT_DESC 0x3f 370#define NETXEN_OLD_RXPKT_DESC 0x3f
371#define NETXEN_NIC_RESPONSE_DESC 0x05
376 372
377/* for status field in status_desc */ 373/* for status field in status_desc */
378#define STATUS_NEED_CKSUM (1) 374#define STATUS_NEED_CKSUM (1)
@@ -382,13 +378,11 @@ struct rcv_desc {
382#define STATUS_OWNER_HOST (0x1ULL << 56) 378#define STATUS_OWNER_HOST (0x1ULL << 56)
383#define STATUS_OWNER_PHANTOM (0x2ULL << 56) 379#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
384 380
385/* Note: sizeof(status_desc) should always be a mutliple of 2 */ 381/* Status descriptor:
386 382 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
387#define netxen_get_sts_desc_lro_cnt(status_desc) \ 383 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
388 ((status_desc)->lro & 0x7F) 384 53-55 desc_cnt, 56-57 owner, 58-63 opcode
389#define netxen_get_sts_desc_lro_last_frag(status_desc) \ 385 */
390 (((status_desc)->lro & 0x80) >> 7)
391
392#define netxen_get_sts_port(sts_data) \ 386#define netxen_get_sts_port(sts_data) \
393 ((sts_data) & 0x0F) 387 ((sts_data) & 0x0F)
394#define netxen_get_sts_status(sts_data) \ 388#define netxen_get_sts_status(sts_data) \
@@ -403,41 +397,15 @@ struct rcv_desc {
403 (((sts_data) >> 44) & 0x0F) 397 (((sts_data) >> 44) & 0x0F)
404#define netxen_get_sts_pkt_offset(sts_data) \ 398#define netxen_get_sts_pkt_offset(sts_data) \
405 (((sts_data) >> 48) & 0x1F) 399 (((sts_data) >> 48) & 0x1F)
400#define netxen_get_sts_desc_cnt(sts_data) \
401 (((sts_data) >> 53) & 0x7)
406#define netxen_get_sts_opcode(sts_data) \ 402#define netxen_get_sts_opcode(sts_data) \
407 (((sts_data) >> 58) & 0x03F) 403 (((sts_data) >> 58) & 0x03F)
408 404
409struct status_desc { 405struct status_desc {
410 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length 406 __le64 status_desc_data[2];
411 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
412 53-55 desc_cnt, 56-57 owner, 58-63 opcode
413 */
414 __le64 status_desc_data;
415 union {
416 struct {
417 __le32 hash_value;
418 u8 hash_type;
419 u8 msg_type;
420 u8 unused;
421 union {
422 /* Bit pattern: 0-6 lro_count indicates frag
423 * sequence, 7 last_frag indicates last frag
424 */
425 u8 lro;
426
427 /* chained buffers */
428 u8 nr_frags;
429 };
430 };
431 struct {
432 __le16 frag_handles[4];
433 };
434 };
435} __attribute__ ((aligned(16))); 407} __attribute__ ((aligned(16)));
436 408
437enum {
438 NETXEN_RCV_PEG_0 = 0,
439 NETXEN_RCV_PEG_1
440};
441/* The version of the main data structure */ 409/* The version of the main data structure */
442#define NETXEN_BDINFO_VERSION 1 410#define NETXEN_BDINFO_VERSION 1
443 411
@@ -447,85 +415,35 @@ enum {
447/* Max number of Gig ports on a Phantom board */ 415/* Max number of Gig ports on a Phantom board */
448#define NETXEN_MAX_PORTS 4 416#define NETXEN_MAX_PORTS 4
449 417
450typedef enum { 418#define NETXEN_BRDTYPE_P1_BD 0x0000
451 NETXEN_BRDTYPE_P1_BD = 0x0000, 419#define NETXEN_BRDTYPE_P1_SB 0x0001
452 NETXEN_BRDTYPE_P1_SB = 0x0001, 420#define NETXEN_BRDTYPE_P1_SMAX 0x0002
453 NETXEN_BRDTYPE_P1_SMAX = 0x0002, 421#define NETXEN_BRDTYPE_P1_SOCK 0x0003
454 NETXEN_BRDTYPE_P1_SOCK = 0x0003, 422
455 423#define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
456 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, 424#define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
457 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, 425#define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
458 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, 426#define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
459 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, 427#define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
460 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, 428
461 429#define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
462 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, 430#define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
463 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, 431#define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
464 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f, 432
465 433#define NETXEN_BRDTYPE_P3_REF_QG 0x0021
466 NETXEN_BRDTYPE_P3_REF_QG = 0x0021, 434#define NETXEN_BRDTYPE_P3_HMEZ 0x0022
467 NETXEN_BRDTYPE_P3_HMEZ = 0x0022, 435#define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
468 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023, 436#define NETXEN_BRDTYPE_P3_4_GB 0x0024
469 NETXEN_BRDTYPE_P3_4_GB = 0x0024, 437#define NETXEN_BRDTYPE_P3_IMEZ 0x0025
470 NETXEN_BRDTYPE_P3_IMEZ = 0x0025, 438#define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
471 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026, 439#define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
472 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027, 440#define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
473 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028, 441#define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
474 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029, 442#define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
475 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a, 443#define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
476 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b, 444#define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
477 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031, 445#define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
478 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032, 446#define NETXEN_BRDTYPE_P3_10G_TP 0x0080
479 NETXEN_BRDTYPE_P3_10G_TP = 0x0080
480
481} netxen_brdtype_t;
482
483typedef enum {
484 NETXEN_BRDMFG_INVENTEC = 1
485} netxen_brdmfg;
486
487typedef enum {
488 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
489 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
490 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
491 MEM_ORG_256Mbx4 = 0x3,
492 MEM_ORG_256Mbx8 = 0x4,
493 MEM_ORG_256Mbx16 = 0x5,
494 MEM_ORG_512Mbx4 = 0x6,
495 MEM_ORG_512Mbx8 = 0x7,
496 MEM_ORG_512Mbx16 = 0x8,
497 MEM_ORG_1Gbx4 = 0x9,
498 MEM_ORG_1Gbx8 = 0xa,
499 MEM_ORG_1Gbx16 = 0xb,
500 MEM_ORG_2Gbx4 = 0xc,
501 MEM_ORG_2Gbx8 = 0xd,
502 MEM_ORG_2Gbx16 = 0xe,
503 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
504 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
505} netxen_mn_mem_org_t;
506
507typedef enum {
508 MEM_ORG_512Kx36 = 0x0,
509 MEM_ORG_1Mx36 = 0x1,
510 MEM_ORG_2Mx36 = 0x2
511} netxen_sn_mem_org_t;
512
513typedef enum {
514 MEM_DEPTH_4MB = 0x1,
515 MEM_DEPTH_8MB = 0x2,
516 MEM_DEPTH_16MB = 0x3,
517 MEM_DEPTH_32MB = 0x4,
518 MEM_DEPTH_64MB = 0x5,
519 MEM_DEPTH_128MB = 0x6,
520 MEM_DEPTH_256MB = 0x7,
521 MEM_DEPTH_512MB = 0x8,
522 MEM_DEPTH_1GB = 0x9,
523 MEM_DEPTH_2GB = 0xa,
524 MEM_DEPTH_4GB = 0xb,
525 MEM_DEPTH_8GB = 0xc,
526 MEM_DEPTH_16GB = 0xd,
527 MEM_DEPTH_32GB = 0xe
528} netxen_mem_depth_t;
529 447
530struct netxen_board_info { 448struct netxen_board_info {
531 u32 header_version; 449 u32 header_version;
@@ -676,17 +594,15 @@ struct netxen_new_user_info {
676#define PRIMARY_IMAGE_BAD 0xffffffff 594#define PRIMARY_IMAGE_BAD 0xffffffff
677 595
678/* Flash memory map */ 596/* Flash memory map */
679typedef enum { 597#define NETXEN_CRBINIT_START 0 /* crbinit section */
680 NETXEN_CRBINIT_START = 0, /* Crbinit section */ 598#define NETXEN_BRDCFG_START 0x4000 /* board config */
681 NETXEN_BRDCFG_START = 0x4000, /* board config */ 599#define NETXEN_INITCODE_START 0x6000 /* pegtune code */
682 NETXEN_INITCODE_START = 0x6000, /* pegtune code */ 600#define NETXEN_BOOTLD_START 0x10000 /* bootld */
683 NETXEN_BOOTLD_START = 0x10000, /* bootld */ 601#define NETXEN_IMAGE_START 0x43000 /* compressed image */
684 NETXEN_IMAGE_START = 0x43000, /* compressed image */ 602#define NETXEN_SECONDARY_START 0x200000 /* backup images */
685 NETXEN_SECONDARY_START = 0x200000, /* backup images */ 603#define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
686 NETXEN_PXE_START = 0x3E0000, /* user defined region */ 604#define NETXEN_USER_START 0x3E8000 /* Firmare info */
687 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */ 605#define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
688 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
689} netxen_flash_map_t;
690 606
691#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) 607#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
692#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) 608#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
@@ -708,21 +624,8 @@ typedef enum {
708#define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) 624#define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
709#define NETXEN_NUM_PRIMARY_SECTORS (0x20) 625#define NETXEN_NUM_PRIMARY_SECTORS (0x20)
710#define NETXEN_NUM_CONFIG_SECTORS (1) 626#define NETXEN_NUM_CONFIG_SECTORS (1)
711#define PFX "NetXen: "
712extern char netxen_nic_driver_name[]; 627extern char netxen_nic_driver_name[];
713 628
714/* Note: Make sure to not call this before adapter->port is valid */
715#if !defined(NETXEN_DEBUG)
716#define DPRINTK(klevel, fmt, args...) do { \
717 } while (0)
718#else
719#define DPRINTK(klevel, fmt, args...) do { \
720 printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
721 (adapter != NULL && adapter->netdev != NULL) ? \
722 adapter->netdev->name : NULL, \
723 ## args); } while(0)
724#endif
725
726/* Number of status descriptors to handle per interrupt */ 629/* Number of status descriptors to handle per interrupt */
727#define MAX_STATUS_HANDLE (64) 630#define MAX_STATUS_HANDLE (64)
728 631
@@ -732,7 +635,7 @@ extern char netxen_nic_driver_name[];
732 */ 635 */
733struct netxen_skb_frag { 636struct netxen_skb_frag {
734 u64 dma; 637 u64 dma;
735 ulong length; 638 u64 length;
736}; 639};
737 640
738#define _netxen_set_bits(config_word, start, bits, val) {\ 641#define _netxen_set_bits(config_word, start, bits, val) {\
@@ -793,34 +696,24 @@ struct netxen_hardware_context {
793 696
794 u8 cut_through; 697 u8 cut_through;
795 u8 revision_id; 698 u8 revision_id;
699 u8 pci_func;
700 u8 linkup;
796 u16 port_type; 701 u16 port_type;
797 int board_type; 702 u16 board_type;
798 u32 linkup;
799 /* Address of cmd ring in Phantom */
800 struct cmd_desc_type0 *cmd_desc_head;
801 dma_addr_t cmd_desc_phys_addr;
802 struct netxen_adapter *adapter;
803 int pci_func;
804}; 703};
805 704
806#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 705#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
807#define ETHERNET_FCS_SIZE 4 706#define ETHERNET_FCS_SIZE 4
808 707
809struct netxen_adapter_stats { 708struct netxen_adapter_stats {
810 u64 rcvdbadskb;
811 u64 xmitcalled; 709 u64 xmitcalled;
812 u64 xmitedframes;
813 u64 xmitfinished; 710 u64 xmitfinished;
814 u64 badskblen;
815 u64 nocmddescriptor;
816 u64 polled;
817 u64 rxdropped; 711 u64 rxdropped;
818 u64 txdropped; 712 u64 txdropped;
819 u64 csummed; 713 u64 csummed;
820 u64 no_rcv; 714 u64 no_rcv;
821 u64 rxbytes; 715 u64 rxbytes;
822 u64 txbytes; 716 u64 txbytes;
823 u64 ints;
824}; 717};
825 718
826/* 719/*
@@ -852,14 +745,25 @@ struct nx_host_sds_ring {
852 struct napi_struct napi; 745 struct napi_struct napi;
853 struct list_head free_list[NUM_RCV_DESC_RINGS]; 746 struct list_head free_list[NUM_RCV_DESC_RINGS];
854 747
855 u16 clean_tx;
856 u16 post_rxd;
857 int irq; 748 int irq;
858 749
859 dma_addr_t phys_addr; 750 dma_addr_t phys_addr;
860 char name[IFNAMSIZ+4]; 751 char name[IFNAMSIZ+4];
861}; 752};
862 753
754struct nx_host_tx_ring {
755 u32 producer;
756 __le32 *hw_consumer;
757 u32 sw_consumer;
758 u32 crb_cmd_producer;
759 u32 crb_cmd_consumer;
760 u32 num_desc;
761
762 struct netxen_cmd_buffer *cmd_buf_arr;
763 struct cmd_desc_type0 *desc_head;
764 dma_addr_t phys_addr;
765};
766
863/* 767/*
864 * Receive context. There is one such structure per instance of the 768 * Receive context. There is one such structure per instance of the
865 * receive processing. Any state information that is relevant to 769 * receive processing. Any state information that is relevant to
@@ -872,7 +776,7 @@ struct netxen_recv_context {
872 u16 virt_port; 776 u16 virt_port;
873 777
874 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS]; 778 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
875 struct nx_host_sds_ring sds_rings[NUM_STS_DESC_RINGS]; 779 struct nx_host_sds_ring *sds_rings;
876}; 780};
877 781
878/* New HW context creation */ 782/* New HW context creation */
@@ -1154,31 +1058,118 @@ typedef struct {
1154 1058
1155#define NX_MAC_EVENT 0x1 1059#define NX_MAC_EVENT 0x1
1156 1060
1157enum { 1061/*
1158 NX_NIC_H2C_OPCODE_START = 0, 1062 * Driver --> Firmware
1159 NX_NIC_H2C_OPCODE_CONFIG_RSS, 1063 */
1160 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL, 1064#define NX_NIC_H2C_OPCODE_START 0
1161 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE, 1065#define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1162 NX_NIC_H2C_OPCODE_CONFIG_LED, 1066#define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1163 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS, 1067#define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1164 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC, 1068#define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1165 NX_NIC_H2C_OPCODE_LRO_REQUEST, 1069#define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1166 NX_NIC_H2C_OPCODE_GET_SNMP_STATS, 1070#define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1167 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST, 1071#define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1168 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST, 1072#define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1169 NX_NIC_H2C_OPCODE_PROXY_SET_MTU, 1073#define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1170 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE, 1074#define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1171 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST, 1075#define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1172 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST, 1076#define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1173 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST, 1077#define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1174 NX_NIC_H2C_OPCODE_GET_NET_STATS, 1078#define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1175 NX_NIC_H2C_OPCODE_LAST 1079#define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1176}; 1080#define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1081#define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1082#define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1083#define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1084#define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1085#define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1086#define NX_NIC_C2C_OPCODE 22
1087#define NX_NIC_H2C_OPCODE_LAST 23
1088
1089/*
1090 * Firmware --> Driver
1091 */
1092
1093#define NX_NIC_C2H_OPCODE_START 128
1094#define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1095#define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1096#define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1097#define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1098#define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1099#define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1100#define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1101#define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1102#define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1103#define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1104#define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1105#define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1106#define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1107#define NX_NIC_C2H_OPCODE_LAST 142
1177 1108
1178#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 1109#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1179#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 1110#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1180#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 1111#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1181 1112
1113#define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1114#define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1115
1116/* module types */
1117#define LINKEVENT_MODULE_NOT_PRESENT 1
1118#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1119#define LINKEVENT_MODULE_OPTICAL_SRLR 3
1120#define LINKEVENT_MODULE_OPTICAL_LRM 4
1121#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1122#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1123#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1124#define LINKEVENT_MODULE_TWINAX 8
1125
1126#define LINKSPEED_10GBPS 10000
1127#define LINKSPEED_1GBPS 1000
1128#define LINKSPEED_100MBPS 100
1129#define LINKSPEED_10MBPS 10
1130
1131#define LINKSPEED_ENCODED_10MBPS 0
1132#define LINKSPEED_ENCODED_100MBPS 1
1133#define LINKSPEED_ENCODED_1GBPS 2
1134
1135#define LINKEVENT_AUTONEG_DISABLED 0
1136#define LINKEVENT_AUTONEG_ENABLED 1
1137
1138#define LINKEVENT_HALF_DUPLEX 0
1139#define LINKEVENT_FULL_DUPLEX 1
1140
1141#define LINKEVENT_LINKSPEED_MBPS 0
1142#define LINKEVENT_LINKSPEED_ENCODED 1
1143
1144/* firmware response header:
1145 * 63:58 - message type
1146 * 57:56 - owner
1147 * 55:53 - desc count
1148 * 52:48 - reserved
1149 * 47:40 - completion id
1150 * 39:32 - opcode
1151 * 31:16 - error code
1152 * 15:00 - reserved
1153 */
1154#define netxen_get_nic_msgtype(msg_hdr) \
1155 ((msg_hdr >> 58) & 0x3F)
1156#define netxen_get_nic_msg_compid(msg_hdr) \
1157 ((msg_hdr >> 40) & 0xFF)
1158#define netxen_get_nic_msg_opcode(msg_hdr) \
1159 ((msg_hdr >> 32) & 0xFF)
1160#define netxen_get_nic_msg_errcode(msg_hdr) \
1161 ((msg_hdr >> 16) & 0xFFFF)
1162
1163typedef struct {
1164 union {
1165 struct {
1166 u64 hdr;
1167 u64 body[7];
1168 };
1169 u64 words[8];
1170 };
1171} nx_fw_msg_t;
1172
1182typedef struct { 1173typedef struct {
1183 __le64 qhdr; 1174 __le64 qhdr;
1184 __le64 req_hdr; 1175 __le64 req_hdr;
@@ -1218,78 +1209,60 @@ struct netxen_adapter {
1218 1209
1219 struct net_device *netdev; 1210 struct net_device *netdev;
1220 struct pci_dev *pdev; 1211 struct pci_dev *pdev;
1221 int pci_using_dac;
1222 struct net_device_stats net_stats;
1223 int mtu;
1224 int portnum;
1225 u8 physical_port;
1226 u16 tx_context_id;
1227
1228 uint8_t mc_enabled;
1229 uint8_t max_mc_count;
1230 nx_mac_list_t *mac_list; 1212 nx_mac_list_t *mac_list;
1231 1213
1232 struct netxen_legacy_intr_set legacy_intr;
1233
1234 struct work_struct watchdog_task;
1235 struct timer_list watchdog_timer;
1236 struct work_struct tx_timeout_task;
1237
1238 u32 curr_window; 1214 u32 curr_window;
1239 u32 crb_win; 1215 u32 crb_win;
1240 rwlock_t adapter_lock; 1216 rwlock_t adapter_lock;
1241 1217
1242 u32 cmd_producer;
1243 __le32 *cmd_consumer;
1244 u32 last_cmd_consumer;
1245 u32 crb_addr_cmd_producer;
1246 u32 crb_addr_cmd_consumer;
1247 spinlock_t tx_clean_lock; 1218 spinlock_t tx_clean_lock;
1248 1219
1249 u32 num_txd; 1220 u16 num_txd;
1250 u32 num_rxd; 1221 u16 num_rxd;
1251 u32 num_jumbo_rxd; 1222 u16 num_jumbo_rxd;
1252 u32 num_lro_rxd; 1223 u16 num_lro_rxd;
1224
1225 u8 max_rds_rings;
1226 u8 max_sds_rings;
1227 u8 driver_mismatch;
1228 u8 msix_supported;
1229 u8 rx_csum;
1230 u8 pci_using_dac;
1231 u8 portnum;
1232 u8 physical_port;
1233
1234 u8 mc_enabled;
1235 u8 max_mc_count;
1236 u8 rss_supported;
1237 u8 resv2;
1238 u32 resv3;
1253 1239
1254 int max_rds_rings; 1240 u8 has_link_events;
1255 int max_sds_rings; 1241 u8 resv1;
1242 u16 tx_context_id;
1243 u16 mtu;
1244 u16 is_up;
1245
1246 u16 link_speed;
1247 u16 link_duplex;
1248 u16 link_autoneg;
1249 u16 module_type;
1256 1250
1251 u32 capabilities;
1257 u32 flags; 1252 u32 flags;
1258 u32 irq; 1253 u32 irq;
1259 int driver_mismatch;
1260 u32 temp; 1254 u32 temp;
1261
1262 u32 fw_major; 1255 u32 fw_major;
1263 u32 fw_version; 1256 u32 fw_version;
1264 1257
1265 int msix_supported;
1266 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1267
1268 struct netxen_adapter_stats stats; 1258 struct netxen_adapter_stats stats;
1269 1259
1270 u16 link_speed;
1271 u16 link_duplex;
1272 u16 state;
1273 u16 link_autoneg;
1274 int rx_csum;
1275
1276 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1277
1278 /*
1279 * Receive instances. These can be either one per port,
1280 * or one per peg, etc.
1281 */
1282 struct netxen_recv_context recv_ctx; 1260 struct netxen_recv_context recv_ctx;
1283 1261 struct nx_host_tx_ring tx_ring;
1284 int is_up;
1285 struct netxen_dummy_dma dummy_dma;
1286 nx_nic_intr_coalesce_t coal;
1287 1262
1288 /* Context interface shared between card and host */ 1263 /* Context interface shared between card and host */
1289 struct netxen_ring_ctx *ctx_desc; 1264 struct netxen_ring_ctx *ctx_desc;
1290 dma_addr_t ctx_desc_phys_addr; 1265 dma_addr_t ctx_desc_phys_addr;
1291 int intr_scheme;
1292 int msi_mode;
1293 int (*enable_phy_interrupts) (struct netxen_adapter *); 1266 int (*enable_phy_interrupts) (struct netxen_adapter *);
1294 int (*disable_phy_interrupts) (struct netxen_adapter *); 1267 int (*disable_phy_interrupts) (struct netxen_adapter *);
1295 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); 1268 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
@@ -1300,17 +1273,29 @@ struct netxen_adapter {
1300 int (*init_port) (struct netxen_adapter *, int); 1273 int (*init_port) (struct netxen_adapter *, int);
1301 int (*stop_port) (struct netxen_adapter *); 1274 int (*stop_port) (struct netxen_adapter *);
1302 1275
1303 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int); 1276 u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1304 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int); 1277 int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1305 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int); 1278 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1306 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int); 1279 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1307 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32); 1280 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1308 u32 (*pci_read_immediate)(struct netxen_adapter *, u64); 1281 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1309 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1310 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1311 unsigned long (*pci_set_window)(struct netxen_adapter *, 1282 unsigned long (*pci_set_window)(struct netxen_adapter *,
1312 unsigned long long); 1283 unsigned long long);
1313}; /* netxen_adapter structure */ 1284
1285 struct netxen_legacy_intr_set legacy_intr;
1286
1287 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1288
1289 struct netxen_dummy_dma dummy_dma;
1290
1291 struct work_struct watchdog_task;
1292 struct timer_list watchdog_timer;
1293 struct work_struct tx_timeout_task;
1294
1295 struct net_device_stats net_stats;
1296
1297 nx_nic_intr_coalesce_t coal;
1298};
1314 1299
1315/* 1300/*
1316 * NetXen dma watchdog control structure 1301 * NetXen dma watchdog control structure
@@ -1330,46 +1315,6 @@ struct netxen_adapter {
1330#define netxen_get_dma_watchdog_disabled(config_word) \ 1315#define netxen_get_dma_watchdog_disabled(config_word) \
1331 (((config_word) >> 1) & 0x1) 1316 (((config_word) >> 1) & 0x1)
1332 1317
1333/* Max number of xmit producer threads that can run simultaneously */
1334#define MAX_XMIT_PRODUCERS 16
1335
1336#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1337 ((adapter)->ahw.pci_base0 + (off))
1338#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1339 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1340#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1341 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1342
1343static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1344 unsigned long off)
1345{
1346 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1347 return (adapter->ahw.pci_base0 + off);
1348 } else if ((off < SECOND_PAGE_GROUP_END) &&
1349 (off >= SECOND_PAGE_GROUP_START)) {
1350 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1351 } else if ((off < THIRD_PAGE_GROUP_END) &&
1352 (off >= THIRD_PAGE_GROUP_START)) {
1353 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1354 }
1355 return NULL;
1356}
1357
1358static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1359 unsigned long off)
1360{
1361 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1362 return adapter->ahw.pci_base0;
1363 } else if ((off < SECOND_PAGE_GROUP_END) &&
1364 (off >= SECOND_PAGE_GROUP_START)) {
1365 return adapter->ahw.pci_base1;
1366 } else if ((off < THIRD_PAGE_GROUP_END) &&
1367 (off >= THIRD_PAGE_GROUP_START)) {
1368 return adapter->ahw.pci_base2;
1369 }
1370 return NULL;
1371}
1372
1373int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); 1318int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1374int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); 1319int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1375int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); 1320int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
@@ -1382,21 +1327,19 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1382/* Functions available from netxen_nic_hw.c */ 1327/* Functions available from netxen_nic_hw.c */
1383int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); 1328int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1384int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); 1329int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1385void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); 1330
1386int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); 1331#define NXRD32(adapter, off) \
1387void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); 1332 (adapter->hw_read_wx(adapter, off))
1388void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value); 1333#define NXWR32(adapter, off, val) \
1389void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value); 1334 (adapter->hw_write_wx(adapter, off, val))
1390void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1391 1335
1392int netxen_nic_get_board_info(struct netxen_adapter *adapter); 1336int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1393void netxen_nic_get_firmware_info(struct netxen_adapter *adapter); 1337void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1394int netxen_nic_wol_supported(struct netxen_adapter *adapter); 1338int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1395 1339
1396int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, 1340u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1397 ulong off, void *data, int len);
1398int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, 1341int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1399 ulong off, void *data, int len); 1342 ulong off, u32 data);
1400int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, 1343int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1401 u64 off, void *data, int size); 1344 u64 off, void *data, int size);
1402int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, 1345int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
@@ -1412,16 +1355,13 @@ unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1412void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, 1355void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1413 u32 wndw); 1356 u32 wndw);
1414 1357
1415int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, 1358u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1416 ulong off, void *data, int len);
1417int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, 1359int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1418 ulong off, void *data, int len); 1360 ulong off, u32 data);
1419int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, 1361int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1420 u64 off, void *data, int size); 1362 u64 off, void *data, int size);
1421int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, 1363int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1422 u64 off, void *data, int size); 1364 u64 off, void *data, int size);
1423void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1424 unsigned long off, int data);
1425int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, 1365int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1426 u64 off, u32 data); 1366 u64 off, u32 data);
1427u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); 1367u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
@@ -1435,7 +1375,6 @@ unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1435void netxen_free_adapter_offload(struct netxen_adapter *adapter); 1375void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1436int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); 1376int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1437int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); 1377int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1438int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1439int netxen_load_firmware(struct netxen_adapter *adapter); 1378int netxen_load_firmware(struct netxen_adapter *adapter);
1440int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); 1379int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1441 1380
@@ -1475,6 +1414,8 @@ void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1475int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); 1414int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1476int netxen_config_intr_coalesce(struct netxen_adapter *adapter); 1415int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1477int netxen_config_rss(struct netxen_adapter *adapter, int enable); 1416int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1417int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1418void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1478 1419
1479int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); 1420int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1480int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); 1421int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
@@ -1483,7 +1424,7 @@ int netxen_nic_set_mac(struct net_device *netdev, void *p);
1483struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); 1424struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1484 1425
1485void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, 1426void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1486 uint32_t crb_producer); 1427 struct nx_host_tx_ring *tx_ring, uint32_t crb_producer);
1487 1428
1488/* 1429/*
1489 * NetXen Board information 1430 * NetXen Board information
@@ -1491,7 +1432,7 @@ void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1491 1432
1492#define NETXEN_MAX_SHORT_NAME 32 1433#define NETXEN_MAX_SHORT_NAME 32
1493struct netxen_brdinfo { 1434struct netxen_brdinfo {
1494 netxen_brdtype_t brdtype; /* type of board */ 1435 int brdtype; /* type of board */
1495 long ports; /* max no of physical ports */ 1436 long ports; /* max no of physical ports */
1496 char short_name[NETXEN_MAX_SHORT_NAME]; 1437 char short_name[NETXEN_MAX_SHORT_NAME];
1497}; 1438};
@@ -1541,17 +1482,15 @@ dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1541 u32 ctrl; 1482 u32 ctrl;
1542 1483
1543 /* check if already inactive */ 1484 /* check if already inactive */
1544 if (adapter->hw_read_wx(adapter, 1485 ctrl = adapter->hw_read_wx(adapter,
1545 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) 1486 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1546 printk(KERN_ERR "failed to read dma watchdog status\n");
1547 1487
1548 if (netxen_get_dma_watchdog_enabled(ctrl) == 0) 1488 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1549 return 1; 1489 return 1;
1550 1490
1551 /* Send the disable request */ 1491 /* Send the disable request */
1552 netxen_set_dma_watchdog_disable_req(ctrl); 1492 netxen_set_dma_watchdog_disable_req(ctrl);
1553 netxen_crb_writelit_adapter(adapter, 1493 NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1554 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1555 1494
1556 return 0; 1495 return 0;
1557} 1496}
@@ -1561,9 +1500,8 @@ dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1561{ 1500{
1562 u32 ctrl; 1501 u32 ctrl;
1563 1502
1564 if (adapter->hw_read_wx(adapter, 1503 ctrl = adapter->hw_read_wx(adapter,
1565 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) 1504 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1566 printk(KERN_ERR "failed to read dma watchdog status\n");
1567 1505
1568 return (netxen_get_dma_watchdog_enabled(ctrl) == 0); 1506 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1569} 1507}
@@ -1573,9 +1511,8 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter)
1573{ 1511{
1574 u32 ctrl; 1512 u32 ctrl;
1575 1513
1576 if (adapter->hw_read_wx(adapter, 1514 ctrl = adapter->hw_read_wx(adapter,
1577 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) 1515 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1578 printk(KERN_ERR "failed to read dma watchdog status\n");
1579 1516
1580 if (netxen_get_dma_watchdog_enabled(ctrl)) 1517 if (netxen_get_dma_watchdog_enabled(ctrl))
1581 return 1; 1518 return 1;
@@ -1583,8 +1520,7 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter)
1583 /* send the wakeup request */ 1520 /* send the wakeup request */
1584 netxen_set_dma_watchdog_enable_req(ctrl); 1521 netxen_set_dma_watchdog_enable_req(ctrl);
1585 1522
1586 netxen_crb_writelit_adapter(adapter, 1523 NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1587 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1588 1524
1589 return 0; 1525 return 0;
1590} 1526}
diff --git a/drivers/net/netxen/netxen_nic_ctx.c b/drivers/net/netxen/netxen_nic_ctx.c
index 9234473bc08a..fd82adf4f876 100644
--- a/drivers/net/netxen/netxen_nic_ctx.c
+++ b/drivers/net/netxen/netxen_nic_ctx.c
@@ -41,8 +41,7 @@ netxen_api_lock(struct netxen_adapter *adapter)
41 41
42 for (;;) { 42 for (;;) {
43 /* Acquire PCIE HW semaphore5 */ 43 /* Acquire PCIE HW semaphore5 */
44 netxen_nic_read_w0(adapter, 44 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_LOCK));
45 NETXEN_PCIE_REG(PCIE_SEM5_LOCK), &done);
46 45
47 if (done == 1) 46 if (done == 1)
48 break; 47 break;
@@ -56,7 +55,7 @@ netxen_api_lock(struct netxen_adapter *adapter)
56 } 55 }
57 56
58#if 0 57#if 0
59 netxen_nic_write_w1(adapter, 58 NXWR32(adapter,
60 NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER); 59 NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER);
61#endif 60#endif
62 return 0; 61 return 0;
@@ -65,11 +64,8 @@ netxen_api_lock(struct netxen_adapter *adapter)
65static int 64static int
66netxen_api_unlock(struct netxen_adapter *adapter) 65netxen_api_unlock(struct netxen_adapter *adapter)
67{ 66{
68 u32 val;
69
70 /* Release PCIE HW semaphore5 */ 67 /* Release PCIE HW semaphore5 */
71 netxen_nic_read_w0(adapter, 68 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK));
72 NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK), &val);
73 return 0; 69 return 0;
74} 70}
75 71
@@ -86,7 +82,7 @@ netxen_poll_rsp(struct netxen_adapter *adapter)
86 if (++timeout > NX_OS_CRB_RETRY_COUNT) 82 if (++timeout > NX_OS_CRB_RETRY_COUNT)
87 return NX_CDRP_RSP_TIMEOUT; 83 return NX_CDRP_RSP_TIMEOUT;
88 84
89 netxen_nic_read_w1(adapter, NX_CDRP_CRB_OFFSET, &rsp); 85 rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
90 } while (!NX_CDRP_IS_RSP(rsp)); 86 } while (!NX_CDRP_IS_RSP(rsp));
91 87
92 return rsp; 88 return rsp;
@@ -106,16 +102,15 @@ netxen_issue_cmd(struct netxen_adapter *adapter,
106 if (netxen_api_lock(adapter)) 102 if (netxen_api_lock(adapter))
107 return NX_RCODE_TIMEOUT; 103 return NX_RCODE_TIMEOUT;
108 104
109 netxen_nic_write_w1(adapter, NX_SIGN_CRB_OFFSET, signature); 105 NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
110 106
111 netxen_nic_write_w1(adapter, NX_ARG1_CRB_OFFSET, arg1); 107 NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1);
112 108
113 netxen_nic_write_w1(adapter, NX_ARG2_CRB_OFFSET, arg2); 109 NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2);
114 110
115 netxen_nic_write_w1(adapter, NX_ARG3_CRB_OFFSET, arg3); 111 NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3);
116 112
117 netxen_nic_write_w1(adapter, NX_CDRP_CRB_OFFSET, 113 NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd));
118 NX_CDRP_FORM_CMD(cmd));
119 114
120 rsp = netxen_poll_rsp(adapter); 115 rsp = netxen_poll_rsp(adapter);
121 116
@@ -125,7 +120,7 @@ netxen_issue_cmd(struct netxen_adapter *adapter,
125 120
126 rcode = NX_RCODE_TIMEOUT; 121 rcode = NX_RCODE_TIMEOUT;
127 } else if (rsp == NX_CDRP_RSP_FAIL) { 122 } else if (rsp == NX_CDRP_RSP_FAIL) {
128 netxen_nic_read_w1(adapter, NX_ARG1_CRB_OFFSET, &rcode); 123 rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
129 124
130 printk(KERN_ERR "%s: failed card response code:0x%x\n", 125 printk(KERN_ERR "%s: failed card response code:0x%x\n",
131 netxen_nic_driver_name, rcode); 126 netxen_nic_driver_name, rcode);
@@ -328,6 +323,7 @@ nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
328 int err = 0; 323 int err = 0;
329 u64 offset, phys_addr; 324 u64 offset, phys_addr;
330 dma_addr_t rq_phys_addr, rsp_phys_addr; 325 dma_addr_t rq_phys_addr, rsp_phys_addr;
326 struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
331 327
332 rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t); 328 rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
333 rq_addr = pci_alloc_consistent(adapter->pdev, 329 rq_addr = pci_alloc_consistent(adapter->pdev,
@@ -367,10 +363,8 @@ nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
367 363
368 prq_cds = &prq->cds_ring; 364 prq_cds = &prq->cds_ring;
369 365
370 prq_cds->host_phys_addr = 366 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
371 cpu_to_le64(adapter->ahw.cmd_desc_phys_addr); 367 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
372
373 prq_cds->ring_size = cpu_to_le32(adapter->num_txd);
374 368
375 phys_addr = rq_phys_addr; 369 phys_addr = rq_phys_addr;
376 err = netxen_issue_cmd(adapter, 370 err = netxen_issue_cmd(adapter,
@@ -383,8 +377,7 @@ nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
383 377
384 if (err == NX_RCODE_SUCCESS) { 378 if (err == NX_RCODE_SUCCESS) {
385 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb); 379 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
386 adapter->crb_addr_cmd_producer = 380 tx_ring->crb_cmd_producer = NETXEN_NIC_REG(temp - 0x200);
387 NETXEN_NIC_REG(temp - 0x200);
388#if 0 381#if 0
389 adapter->tx_state = 382 adapter->tx_state =
390 le32_to_cpu(prsp->host_ctx_state); 383 le32_to_cpu(prsp->host_ctx_state);
@@ -448,7 +441,19 @@ static struct netxen_recv_crb recv_crb_registers[] = {
448 NETXEN_NIC_REG(0x120) 441 NETXEN_NIC_REG(0x120)
449 }, 442 },
450 /* crb_sts_consumer: */ 443 /* crb_sts_consumer: */
451 NETXEN_NIC_REG(0x138), 444 {
445 NETXEN_NIC_REG(0x138),
446 NETXEN_NIC_REG_2(0x000),
447 NETXEN_NIC_REG_2(0x004),
448 NETXEN_NIC_REG_2(0x008),
449 },
450 /* sw_int_mask */
451 {
452 CRB_SW_INT_MASK_0,
453 NETXEN_NIC_REG_2(0x044),
454 NETXEN_NIC_REG_2(0x048),
455 NETXEN_NIC_REG_2(0x04c),
456 },
452 }, 457 },
453 /* Instance 1 */ 458 /* Instance 1 */
454 { 459 {
@@ -461,7 +466,19 @@ static struct netxen_recv_crb recv_crb_registers[] = {
461 NETXEN_NIC_REG(0x164) 466 NETXEN_NIC_REG(0x164)
462 }, 467 },
463 /* crb_sts_consumer: */ 468 /* crb_sts_consumer: */
464 NETXEN_NIC_REG(0x17c), 469 {
470 NETXEN_NIC_REG(0x17c),
471 NETXEN_NIC_REG_2(0x020),
472 NETXEN_NIC_REG_2(0x024),
473 NETXEN_NIC_REG_2(0x028),
474 },
475 /* sw_int_mask */
476 {
477 CRB_SW_INT_MASK_1,
478 NETXEN_NIC_REG_2(0x064),
479 NETXEN_NIC_REG_2(0x068),
480 NETXEN_NIC_REG_2(0x06c),
481 },
465 }, 482 },
466 /* Instance 2 */ 483 /* Instance 2 */
467 { 484 {
@@ -474,7 +491,19 @@ static struct netxen_recv_crb recv_crb_registers[] = {
474 NETXEN_NIC_REG(0x208) 491 NETXEN_NIC_REG(0x208)
475 }, 492 },
476 /* crb_sts_consumer: */ 493 /* crb_sts_consumer: */
477 NETXEN_NIC_REG(0x220), 494 {
495 NETXEN_NIC_REG(0x220),
496 NETXEN_NIC_REG_2(0x03c),
497 NETXEN_NIC_REG_2(0x03c),
498 NETXEN_NIC_REG_2(0x03c),
499 },
500 /* sw_int_mask */
501 {
502 CRB_SW_INT_MASK_2,
503 NETXEN_NIC_REG_2(0x03c),
504 NETXEN_NIC_REG_2(0x03c),
505 NETXEN_NIC_REG_2(0x03c),
506 },
478 }, 507 },
479 /* Instance 3 */ 508 /* Instance 3 */
480 { 509 {
@@ -487,7 +516,19 @@ static struct netxen_recv_crb recv_crb_registers[] = {
487 NETXEN_NIC_REG(0x24c) 516 NETXEN_NIC_REG(0x24c)
488 }, 517 },
489 /* crb_sts_consumer: */ 518 /* crb_sts_consumer: */
490 NETXEN_NIC_REG(0x264), 519 {
520 NETXEN_NIC_REG(0x264),
521 NETXEN_NIC_REG_2(0x03c),
522 NETXEN_NIC_REG_2(0x03c),
523 NETXEN_NIC_REG_2(0x03c),
524 },
525 /* sw_int_mask */
526 {
527 CRB_SW_INT_MASK_3,
528 NETXEN_NIC_REG_2(0x03c),
529 NETXEN_NIC_REG_2(0x03c),
530 NETXEN_NIC_REG_2(0x03c),
531 },
491 }, 532 },
492}; 533};
493 534
@@ -497,62 +538,65 @@ netxen_init_old_ctx(struct netxen_adapter *adapter)
497 struct netxen_recv_context *recv_ctx; 538 struct netxen_recv_context *recv_ctx;
498 struct nx_host_rds_ring *rds_ring; 539 struct nx_host_rds_ring *rds_ring;
499 struct nx_host_sds_ring *sds_ring; 540 struct nx_host_sds_ring *sds_ring;
541 struct nx_host_tx_ring *tx_ring;
500 int ring; 542 int ring;
501 int func_id = adapter->portnum; 543 int port = adapter->portnum;
544 struct netxen_ring_ctx *hwctx = adapter->ctx_desc;
545 u32 signature;
502 546
503 adapter->ctx_desc->cmd_ring_addr = 547 tx_ring = &adapter->tx_ring;
504 cpu_to_le64(adapter->ahw.cmd_desc_phys_addr); 548 hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr);
505 adapter->ctx_desc->cmd_ring_size = 549 hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc);
506 cpu_to_le32(adapter->num_txd);
507 550
508 recv_ctx = &adapter->recv_ctx; 551 recv_ctx = &adapter->recv_ctx;
509 552
510 for (ring = 0; ring < adapter->max_rds_rings; ring++) { 553 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
511 rds_ring = &recv_ctx->rds_rings[ring]; 554 rds_ring = &recv_ctx->rds_rings[ring];
512 555
513 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = 556 hwctx->rcv_rings[ring].addr =
514 cpu_to_le64(rds_ring->phys_addr); 557 cpu_to_le64(rds_ring->phys_addr);
515 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = 558 hwctx->rcv_rings[ring].size =
516 cpu_to_le32(rds_ring->num_desc); 559 cpu_to_le32(rds_ring->num_desc);
517 } 560 }
518 sds_ring = &recv_ctx->sds_rings[0];
519 adapter->ctx_desc->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
520 adapter->ctx_desc->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
521 561
522 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id), 562 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
563 sds_ring = &recv_ctx->sds_rings[ring];
564
565 if (ring == 0) {
566 hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
567 hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
568 }
569 hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr);
570 hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc);
571 hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring);
572 }
573 hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings);
574
575 signature = (adapter->max_sds_rings > 1) ?
576 NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE;
577
578 NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port),
523 lower32(adapter->ctx_desc_phys_addr)); 579 lower32(adapter->ctx_desc_phys_addr));
524 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id), 580 NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port),
525 upper32(adapter->ctx_desc_phys_addr)); 581 upper32(adapter->ctx_desc_phys_addr));
526 adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id), 582 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
527 NETXEN_CTX_SIGNATURE | func_id); 583 signature | port);
528 return 0; 584 return 0;
529} 585}
530 586
531static uint32_t sw_int_mask[4] = {
532 CRB_SW_INT_MASK_0, CRB_SW_INT_MASK_1,
533 CRB_SW_INT_MASK_2, CRB_SW_INT_MASK_3
534};
535
536int netxen_alloc_hw_resources(struct netxen_adapter *adapter) 587int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
537{ 588{
538 struct netxen_hardware_context *hw = &adapter->ahw;
539 u32 state = 0;
540 void *addr; 589 void *addr;
541 int err = 0; 590 int err = 0;
542 int ring; 591 int ring;
543 struct netxen_recv_context *recv_ctx; 592 struct netxen_recv_context *recv_ctx;
544 struct nx_host_rds_ring *rds_ring; 593 struct nx_host_rds_ring *rds_ring;
545 struct nx_host_sds_ring *sds_ring; 594 struct nx_host_sds_ring *sds_ring;
595 struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
546 596
547 struct pci_dev *pdev = adapter->pdev; 597 struct pci_dev *pdev = adapter->pdev;
548 struct net_device *netdev = adapter->netdev; 598 struct net_device *netdev = adapter->netdev;
549 599 int port = adapter->portnum;
550 err = netxen_receive_peg_ready(adapter);
551 if (err) {
552 printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n",
553 state);
554 return err;
555 }
556 600
557 addr = pci_alloc_consistent(pdev, 601 addr = pci_alloc_consistent(pdev,
558 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), 602 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
@@ -564,17 +608,16 @@ int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
564 } 608 }
565 memset(addr, 0, sizeof(struct netxen_ring_ctx)); 609 memset(addr, 0, sizeof(struct netxen_ring_ctx));
566 adapter->ctx_desc = (struct netxen_ring_ctx *)addr; 610 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
567 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum); 611 adapter->ctx_desc->ctx_id = cpu_to_le32(port);
568 adapter->ctx_desc->cmd_consumer_offset = 612 adapter->ctx_desc->cmd_consumer_offset =
569 cpu_to_le64(adapter->ctx_desc_phys_addr + 613 cpu_to_le64(adapter->ctx_desc_phys_addr +
570 sizeof(struct netxen_ring_ctx)); 614 sizeof(struct netxen_ring_ctx));
571 adapter->cmd_consumer = 615 tx_ring->hw_consumer =
572 (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx)); 616 (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
573 617
574 /* cmd desc ring */ 618 /* cmd desc ring */
575 addr = pci_alloc_consistent(pdev, 619 addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
576 TX_DESC_RINGSIZE(adapter), 620 &tx_ring->phys_addr);
577 &hw->cmd_desc_phys_addr);
578 621
579 if (addr == NULL) { 622 if (addr == NULL) {
580 dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n", 623 dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n",
@@ -582,7 +625,7 @@ int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
582 return -ENOMEM; 625 return -ENOMEM;
583 } 626 }
584 627
585 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; 628 tx_ring->desc_head = (struct cmd_desc_type0 *)addr;
586 629
587 recv_ctx = &adapter->recv_ctx; 630 recv_ctx = &adapter->recv_ctx;
588 631
@@ -602,8 +645,7 @@ int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
602 645
603 if (adapter->fw_major < 4) 646 if (adapter->fw_major < 4)
604 rds_ring->crb_rcv_producer = 647 rds_ring->crb_rcv_producer =
605 recv_crb_registers[adapter->portnum]. 648 recv_crb_registers[port].crb_rcv_producer[ring];
606 crb_rcv_producer[ring];
607 } 649 }
608 650
609 for (ring = 0; ring < adapter->max_sds_rings; ring++) { 651 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
@@ -620,13 +662,16 @@ int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
620 goto err_out_free; 662 goto err_out_free;
621 } 663 }
622 sds_ring->desc_head = (struct status_desc *)addr; 664 sds_ring->desc_head = (struct status_desc *)addr;
665
666 sds_ring->crb_sts_consumer =
667 recv_crb_registers[port].crb_sts_consumer[ring];
668
669 sds_ring->crb_intr_mask =
670 recv_crb_registers[port].sw_int_mask[ring];
623 } 671 }
624 672
625 673
626 if (adapter->fw_major >= 4) { 674 if (adapter->fw_major >= 4) {
627 adapter->intr_scheme = INTR_SCHEME_PERPORT;
628 adapter->msi_mode = MSI_MODE_MULTIFUNC;
629
630 err = nx_fw_cmd_create_rx_ctx(adapter); 675 err = nx_fw_cmd_create_rx_ctx(adapter);
631 if (err) 676 if (err)
632 goto err_out_free; 677 goto err_out_free;
@@ -634,23 +679,11 @@ int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
634 if (err) 679 if (err)
635 goto err_out_free; 680 goto err_out_free;
636 } else { 681 } else {
637 sds_ring = &recv_ctx->sds_rings[0];
638 sds_ring->crb_sts_consumer =
639 recv_crb_registers[adapter->portnum].crb_sts_consumer;
640
641 adapter->intr_scheme = adapter->pci_read_normalize(adapter,
642 CRB_NIC_CAPABILITIES_FW);
643 adapter->msi_mode = adapter->pci_read_normalize(adapter,
644 CRB_NIC_MSI_MODE_FW);
645 recv_ctx->sds_rings[0].crb_intr_mask =
646 sw_int_mask[adapter->portnum];
647
648 err = netxen_init_old_ctx(adapter); 682 err = netxen_init_old_ctx(adapter);
649 if (err) { 683 if (err) {
650 netxen_free_hw_resources(adapter); 684 netxen_free_hw_resources(adapter);
651 return err; 685 return err;
652 } 686 }
653
654 } 687 }
655 688
656 return 0; 689 return 0;
@@ -665,11 +698,19 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
665 struct netxen_recv_context *recv_ctx; 698 struct netxen_recv_context *recv_ctx;
666 struct nx_host_rds_ring *rds_ring; 699 struct nx_host_rds_ring *rds_ring;
667 struct nx_host_sds_ring *sds_ring; 700 struct nx_host_sds_ring *sds_ring;
701 struct nx_host_tx_ring *tx_ring;
668 int ring; 702 int ring;
669 703
704 int port = adapter->portnum;
705
670 if (adapter->fw_major >= 4) { 706 if (adapter->fw_major >= 4) {
671 nx_fw_cmd_destroy_tx_ctx(adapter); 707 nx_fw_cmd_destroy_tx_ctx(adapter);
672 nx_fw_cmd_destroy_rx_ctx(adapter); 708 nx_fw_cmd_destroy_rx_ctx(adapter);
709 } else {
710 netxen_api_lock(adapter);
711 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
712 NETXEN_CTX_RESET | port);
713 netxen_api_unlock(adapter);
673 } 714 }
674 715
675 if (adapter->ctx_desc != NULL) { 716 if (adapter->ctx_desc != NULL) {
@@ -681,13 +722,12 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
681 adapter->ctx_desc = NULL; 722 adapter->ctx_desc = NULL;
682 } 723 }
683 724
684 if (adapter->ahw.cmd_desc_head != NULL) { 725 tx_ring = &adapter->tx_ring;
726 if (tx_ring->desc_head != NULL) {
685 pci_free_consistent(adapter->pdev, 727 pci_free_consistent(adapter->pdev,
686 sizeof(struct cmd_desc_type0) * 728 TX_DESC_RINGSIZE(tx_ring),
687 adapter->num_txd, 729 tx_ring->desc_head, tx_ring->phys_addr);
688 adapter->ahw.cmd_desc_head, 730 tx_ring->desc_head = NULL;
689 adapter->ahw.cmd_desc_phys_addr);
690 adapter->ahw.cmd_desc_head = NULL;
691 } 731 }
692 732
693 recv_ctx = &adapter->recv_ctx; 733 recv_ctx = &adapter->recv_ctx;
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index a677ff895184..a452b2facb77 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -30,7 +30,6 @@
30 30
31#include <linux/types.h> 31#include <linux/types.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <asm/uaccess.h>
34#include <linux/pci.h> 33#include <linux/pci.h>
35#include <asm/io.h> 34#include <asm/io.h>
36#include <linux/netdevice.h> 35#include <linux/netdevice.h>
@@ -53,13 +52,9 @@ struct netxen_nic_stats {
53#define NETXEN_NIC_INVALID_DATA 0xDEADBEEF 52#define NETXEN_NIC_INVALID_DATA 0xDEADBEEF
54 53
55static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = { 54static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = {
56 {"rcvd_bad_skb", NETXEN_NIC_STAT(stats.rcvdbadskb)},
57 {"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)}, 55 {"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)},
58 {"xmited_frames", NETXEN_NIC_STAT(stats.xmitedframes)},
59 {"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)}, 56 {"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)},
60 {"bad_skb_len", NETXEN_NIC_STAT(stats.badskblen)}, 57 {"rx_dropped", NETXEN_NIC_STAT(stats.rxdropped)},
61 {"no_cmd_desc", NETXEN_NIC_STAT(stats.nocmddescriptor)},
62 {"polled", NETXEN_NIC_STAT(stats.polled)},
63 {"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)}, 58 {"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)},
64 {"csummed", NETXEN_NIC_STAT(stats.csummed)}, 59 {"csummed", NETXEN_NIC_STAT(stats.csummed)},
65 {"no_rcv", NETXEN_NIC_STAT(stats.no_rcv)}, 60 {"no_rcv", NETXEN_NIC_STAT(stats.no_rcv)},
@@ -97,12 +92,9 @@ netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
97 strncpy(drvinfo->driver, netxen_nic_driver_name, 32); 92 strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
98 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32); 93 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
99 write_lock_irqsave(&adapter->adapter_lock, flags); 94 write_lock_irqsave(&adapter->adapter_lock, flags);
100 fw_major = adapter->pci_read_normalize(adapter, 95 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
101 NETXEN_FW_VERSION_MAJOR); 96 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
102 fw_minor = adapter->pci_read_normalize(adapter, 97 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
103 NETXEN_FW_VERSION_MINOR);
104 fw_build = adapter->pci_read_normalize(adapter,
105 NETXEN_FW_VERSION_SUB);
106 write_unlock_irqrestore(&adapter->adapter_lock, flags); 98 write_unlock_irqrestore(&adapter->adapter_lock, flags);
107 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build); 99 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
108 100
@@ -115,6 +107,7 @@ static int
115netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 107netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
116{ 108{
117 struct netxen_adapter *adapter = netdev_priv(dev); 109 struct netxen_adapter *adapter = netdev_priv(dev);
110 int check_sfp_module = 0;
118 111
119 /* read which mode */ 112 /* read which mode */
120 if (adapter->ahw.port_type == NETXEN_NIC_GBE) { 113 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
@@ -139,7 +132,7 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
139 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { 132 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
140 u32 val; 133 u32 val;
141 134
142 adapter->hw_read_wx(adapter, NETXEN_PORT_MODE_ADDR, &val, 4); 135 val = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
143 if (val == NETXEN_PORT_MODE_802_3_AP) { 136 if (val == NETXEN_PORT_MODE_802_3_AP) {
144 ecmd->supported = SUPPORTED_1000baseT_Full; 137 ecmd->supported = SUPPORTED_1000baseT_Full;
145 ecmd->advertising = ADVERTISED_1000baseT_Full; 138 ecmd->advertising = ADVERTISED_1000baseT_Full;
@@ -148,13 +141,19 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
148 ecmd->advertising = ADVERTISED_10000baseT_Full; 141 ecmd->advertising = ADVERTISED_10000baseT_Full;
149 } 142 }
150 143
144 if (netif_running(dev) && adapter->has_link_events) {
145 ecmd->speed = adapter->link_speed;
146 ecmd->autoneg = adapter->link_autoneg;
147 ecmd->duplex = adapter->link_duplex;
148 goto skip;
149 }
150
151 ecmd->port = PORT_TP; 151 ecmd->port = PORT_TP;
152 152
153 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 153 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
154 u16 pcifn = adapter->ahw.pci_func; 154 u16 pcifn = adapter->ahw.pci_func;
155 155
156 adapter->hw_read_wx(adapter, 156 val = NXRD32(adapter, P3_LINK_SPEED_REG(pcifn));
157 P3_LINK_SPEED_REG(pcifn), &val, 4);
158 ecmd->speed = P3_LINK_SPEED_MHZ * 157 ecmd->speed = P3_LINK_SPEED_MHZ *
159 P3_LINK_SPEED_VAL(pcifn, val); 158 P3_LINK_SPEED_VAL(pcifn, val);
160 } else 159 } else
@@ -165,10 +164,11 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
165 } else 164 } else
166 return -EIO; 165 return -EIO;
167 166
167skip:
168 ecmd->phy_address = adapter->physical_port; 168 ecmd->phy_address = adapter->physical_port;
169 ecmd->transceiver = XCVR_EXTERNAL; 169 ecmd->transceiver = XCVR_EXTERNAL;
170 170
171 switch ((netxen_brdtype_t)adapter->ahw.board_type) { 171 switch (adapter->ahw.board_type) {
172 case NETXEN_BRDTYPE_P2_SB35_4G: 172 case NETXEN_BRDTYPE_P2_SB35_4G:
173 case NETXEN_BRDTYPE_P2_SB31_2G: 173 case NETXEN_BRDTYPE_P2_SB31_2G:
174 case NETXEN_BRDTYPE_P3_REF_QG: 174 case NETXEN_BRDTYPE_P3_REF_QG:
@@ -195,7 +195,7 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
195 case NETXEN_BRDTYPE_P3_HMEZ: 195 case NETXEN_BRDTYPE_P3_HMEZ:
196 ecmd->supported |= SUPPORTED_MII; 196 ecmd->supported |= SUPPORTED_MII;
197 ecmd->advertising |= ADVERTISED_MII; 197 ecmd->advertising |= ADVERTISED_MII;
198 ecmd->port = PORT_FIBRE; 198 ecmd->port = PORT_MII;
199 ecmd->autoneg = AUTONEG_DISABLE; 199 ecmd->autoneg = AUTONEG_DISABLE;
200 break; 200 break;
201 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: 201 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
@@ -203,6 +203,8 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
203 case NETXEN_BRDTYPE_P3_10G_SFP_QT: 203 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
204 ecmd->advertising |= ADVERTISED_TP; 204 ecmd->advertising |= ADVERTISED_TP;
205 ecmd->supported |= SUPPORTED_TP; 205 ecmd->supported |= SUPPORTED_TP;
206 check_sfp_module = netif_running(dev) &&
207 adapter->has_link_events;
206 case NETXEN_BRDTYPE_P2_SB31_10G: 208 case NETXEN_BRDTYPE_P2_SB31_10G:
207 case NETXEN_BRDTYPE_P3_10G_XFP: 209 case NETXEN_BRDTYPE_P3_10G_XFP:
208 ecmd->supported |= SUPPORTED_FIBRE; 210 ecmd->supported |= SUPPORTED_FIBRE;
@@ -217,6 +219,8 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
217 ecmd->advertising |= 219 ecmd->advertising |=
218 (ADVERTISED_FIBRE | ADVERTISED_TP); 220 (ADVERTISED_FIBRE | ADVERTISED_TP);
219 ecmd->port = PORT_FIBRE; 221 ecmd->port = PORT_FIBRE;
222 check_sfp_module = netif_running(dev) &&
223 adapter->has_link_events;
220 } else { 224 } else {
221 ecmd->autoneg = AUTONEG_ENABLE; 225 ecmd->autoneg = AUTONEG_ENABLE;
222 ecmd->supported |= (SUPPORTED_TP |SUPPORTED_Autoneg); 226 ecmd->supported |= (SUPPORTED_TP |SUPPORTED_Autoneg);
@@ -227,10 +231,27 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 break; 231 break;
228 default: 232 default:
229 printk(KERN_ERR "netxen-nic: Unsupported board model %d\n", 233 printk(KERN_ERR "netxen-nic: Unsupported board model %d\n",
230 (netxen_brdtype_t)adapter->ahw.board_type); 234 adapter->ahw.board_type);
231 return -EIO; 235 return -EIO;
232 } 236 }
233 237
238 if (check_sfp_module) {
239 switch (adapter->module_type) {
240 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
241 case LINKEVENT_MODULE_OPTICAL_SRLR:
242 case LINKEVENT_MODULE_OPTICAL_LRM:
243 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
244 ecmd->port = PORT_FIBRE;
245 break;
246 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
247 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
248 case LINKEVENT_MODULE_TWINAX:
249 ecmd->port = PORT_TP;
250 default:
251 ecmd->port = -1;
252 }
253 }
254
234 return 0; 255 return 0;
235} 256}
236 257
@@ -398,12 +419,11 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
398 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) | 419 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
399 (adapter->pdev)->device; 420 (adapter->pdev)->device;
400 /* which mode */ 421 /* which mode */
401 adapter->hw_read_wx(adapter, NETXEN_NIU_MODE, &regs_buff[0], 4); 422 regs_buff[0] = NXRD32(adapter, NETXEN_NIU_MODE);
402 mode = regs_buff[0]; 423 mode = regs_buff[0];
403 424
404 /* Common registers to all the modes */ 425 /* Common registers to all the modes */
405 adapter->hw_read_wx(adapter, 426 regs_buff[2] = NXRD32(adapter, NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER);
406 NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER, &regs_buff[2], 4);
407 /* GB/XGB Mode */ 427 /* GB/XGB Mode */
408 mode = (mode / 2) - 1; 428 mode = (mode / 2) - 1;
409 window = 0; 429 window = 0;
@@ -414,9 +434,8 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
414 window = adapter->physical_port * 434 window = adapter->physical_port *
415 NETXEN_NIC_PORT_WINDOW; 435 NETXEN_NIC_PORT_WINDOW;
416 436
417 adapter->hw_read_wx(adapter, 437 regs_buff[i] = NXRD32(adapter,
418 niu_registers[mode].reg[i - 3] + window, 438 niu_registers[mode].reg[i - 3] + window);
419 &regs_buff[i], 4);
420 } 439 }
421 440
422 } 441 }
@@ -440,7 +459,7 @@ static u32 netxen_nic_test_link(struct net_device *dev)
440 return !val; 459 return !val;
441 } 460 }
442 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { 461 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
443 val = adapter->pci_read_normalize(adapter, CRB_XG_STATE); 462 val = NXRD32(adapter, CRB_XG_STATE);
444 return (val == XG_LINK_UP) ? 0 : 1; 463 return (val == XG_LINK_UP) ? 0 : 1;
445 } 464 }
446 return -EIO; 465 return -EIO;
@@ -504,10 +523,9 @@ netxen_nic_get_pauseparam(struct net_device *dev,
504 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) 523 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
505 return; 524 return;
506 /* get flow control settings */ 525 /* get flow control settings */
507 netxen_nic_read_w0(adapter,NETXEN_NIU_GB_MAC_CONFIG_0(port), 526 val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
508 &val);
509 pause->rx_pause = netxen_gb_get_rx_flowctl(val); 527 pause->rx_pause = netxen_gb_get_rx_flowctl(val);
510 netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, &val); 528 val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
511 switch (port) { 529 switch (port) {
512 case 0: 530 case 0:
513 pause->tx_pause = !(netxen_gb_get_gb0_mask(val)); 531 pause->tx_pause = !(netxen_gb_get_gb0_mask(val));
@@ -527,7 +545,7 @@ netxen_nic_get_pauseparam(struct net_device *dev,
527 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS)) 545 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
528 return; 546 return;
529 pause->rx_pause = 1; 547 pause->rx_pause = 1;
530 netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, &val); 548 val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
531 if (port == 0) 549 if (port == 0)
532 pause->tx_pause = !(netxen_xg_get_xg0_mask(val)); 550 pause->tx_pause = !(netxen_xg_get_xg0_mask(val));
533 else 551 else
@@ -550,18 +568,17 @@ netxen_nic_set_pauseparam(struct net_device *dev,
550 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) 568 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
551 return -EIO; 569 return -EIO;
552 /* set flow control */ 570 /* set flow control */
553 netxen_nic_read_w0(adapter, 571 val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
554 NETXEN_NIU_GB_MAC_CONFIG_0(port), &val);
555 572
556 if (pause->rx_pause) 573 if (pause->rx_pause)
557 netxen_gb_rx_flowctl(val); 574 netxen_gb_rx_flowctl(val);
558 else 575 else
559 netxen_gb_unset_rx_flowctl(val); 576 netxen_gb_unset_rx_flowctl(val);
560 577
561 netxen_nic_write_w0(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 578 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
562 val); 579 val);
563 /* set autoneg */ 580 /* set autoneg */
564 netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, &val); 581 val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
565 switch (port) { 582 switch (port) {
566 case 0: 583 case 0:
567 if (pause->tx_pause) 584 if (pause->tx_pause)
@@ -589,11 +606,11 @@ netxen_nic_set_pauseparam(struct net_device *dev,
589 netxen_gb_set_gb3_mask(val); 606 netxen_gb_set_gb3_mask(val);
590 break; 607 break;
591 } 608 }
592 netxen_nic_write_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, val); 609 NXWR32(adapter, NETXEN_NIU_GB_PAUSE_CTL, val);
593 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { 610 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
594 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS)) 611 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
595 return -EIO; 612 return -EIO;
596 netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, &val); 613 val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
597 if (port == 0) { 614 if (port == 0) {
598 if (pause->tx_pause) 615 if (pause->tx_pause)
599 netxen_xg_unset_xg0_mask(val); 616 netxen_xg_unset_xg0_mask(val);
@@ -605,7 +622,7 @@ netxen_nic_set_pauseparam(struct net_device *dev,
605 else 622 else
606 netxen_xg_set_xg1_mask(val); 623 netxen_xg_set_xg1_mask(val);
607 } 624 }
608 netxen_nic_write_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, val); 625 NXWR32(adapter, NETXEN_NIU_XG_PAUSE_CTL, val);
609 } else { 626 } else {
610 printk(KERN_ERR "%s: Unknown board type: %x\n", 627 printk(KERN_ERR "%s: Unknown board type: %x\n",
611 netxen_nic_driver_name, 628 netxen_nic_driver_name,
@@ -619,14 +636,14 @@ static int netxen_nic_reg_test(struct net_device *dev)
619 struct netxen_adapter *adapter = netdev_priv(dev); 636 struct netxen_adapter *adapter = netdev_priv(dev);
620 u32 data_read, data_written; 637 u32 data_read, data_written;
621 638
622 netxen_nic_read_w0(adapter, NETXEN_PCIX_PH_REG(0), &data_read); 639 data_read = NXRD32(adapter, NETXEN_PCIX_PH_REG(0));
623 if ((data_read & 0xffff) != PHAN_VENDOR_ID) 640 if ((data_read & 0xffff) != PHAN_VENDOR_ID)
624 return 1; 641 return 1;
625 642
626 data_written = (u32)0xa5a5a5a5; 643 data_written = (u32)0xa5a5a5a5;
627 644
628 netxen_nic_reg_write(adapter, CRB_SCRATCHPAD_TEST, data_written); 645 NXWR32(adapter, CRB_SCRATCHPAD_TEST, data_written);
629 data_read = adapter->pci_read_normalize(adapter, CRB_SCRATCHPAD_TEST); 646 data_read = NXRD32(adapter, CRB_SCRATCHPAD_TEST);
630 if (data_written != data_read) 647 if (data_written != data_read)
631 return 1; 648 return 1;
632 649
@@ -743,11 +760,11 @@ netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
743 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 760 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
744 return; 761 return;
745 762
746 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 763 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
747 if (wol_cfg & (1UL << adapter->portnum)) 764 if (wol_cfg & (1UL << adapter->portnum))
748 wol->supported |= WAKE_MAGIC; 765 wol->supported |= WAKE_MAGIC;
749 766
750 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 767 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
751 if (wol_cfg & (1UL << adapter->portnum)) 768 if (wol_cfg & (1UL << adapter->portnum))
752 wol->wolopts |= WAKE_MAGIC; 769 wol->wolopts |= WAKE_MAGIC;
753} 770}
@@ -764,16 +781,16 @@ netxen_nic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
764 if (wol->wolopts & ~WAKE_MAGIC) 781 if (wol->wolopts & ~WAKE_MAGIC)
765 return -EOPNOTSUPP; 782 return -EOPNOTSUPP;
766 783
767 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 784 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
768 if (!(wol_cfg & (1 << adapter->portnum))) 785 if (!(wol_cfg & (1 << adapter->portnum)))
769 return -EOPNOTSUPP; 786 return -EOPNOTSUPP;
770 787
771 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 788 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
772 if (wol->wolopts & WAKE_MAGIC) 789 if (wol->wolopts & WAKE_MAGIC)
773 wol_cfg |= 1UL << adapter->portnum; 790 wol_cfg |= 1UL << adapter->portnum;
774 else 791 else
775 wol_cfg &= ~(1UL << adapter->portnum); 792 wol_cfg &= ~(1UL << adapter->portnum);
776 netxen_nic_reg_write(adapter, NETXEN_WOL_CONFIG, wol_cfg); 793 NXWR32(adapter, NETXEN_WOL_CONFIG, wol_cfg);
777 794
778 return 0; 795 return 0;
779} 796}
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
index 016c62129c76..7f0ddbfa7b28 100644
--- a/drivers/net/netxen/netxen_nic_hdr.h
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -31,16 +31,8 @@
31#ifndef __NETXEN_NIC_HDR_H_ 31#ifndef __NETXEN_NIC_HDR_H_
32#define __NETXEN_NIC_HDR_H_ 32#define __NETXEN_NIC_HDR_H_
33 33
34#include <linux/module.h>
35#include <linux/kernel.h> 34#include <linux/kernel.h>
36#include <linux/spinlock.h>
37#include <asm/irq.h>
38#include <linux/init.h>
39#include <linux/errno.h>
40#include <linux/pci.h>
41#include <linux/types.h> 35#include <linux/types.h>
42#include <asm/uaccess.h>
43#include <asm/string.h> /* for memset */
44 36
45/* 37/*
46 * The basic unit of access when reading/writing control registers. 38 * The basic unit of access when reading/writing control registers.
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 5026811c04ce..3bb2b8c74d92 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -48,8 +48,49 @@
48#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) 48#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
49#define CRB_INDIRECT_2M (0x1e0000UL) 49#define CRB_INDIRECT_2M (0x1e0000UL)
50 50
51#ifndef readq
52static inline u64 readq(void __iomem *addr)
53{
54 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
55}
56#endif
57
58#ifndef writeq
59static inline void writeq(u64 val, void __iomem *addr)
60{
61 writel(((u32) (val)), (addr));
62 writel(((u32) (val >> 32)), (addr + 4));
63}
64#endif
65
66#define ADDR_IN_RANGE(addr, low, high) \
67 (((addr) < (high)) && ((addr) >= (low)))
68
69#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base0 + (off))
71#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
73#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
74 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
75
76static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
77 unsigned long off)
78{
79 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
80 return PCI_OFFSET_FIRST_RANGE(adapter, off);
81
82 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
83 return PCI_OFFSET_SECOND_RANGE(adapter, off);
84
85 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
86 return PCI_OFFSET_THIRD_RANGE(adapter, off);
87
88 return NULL;
89}
90
51#define CRB_WIN_LOCK_TIMEOUT 100000000 91#define CRB_WIN_LOCK_TIMEOUT 100000000
52static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { 92static crb_128M_2M_block_map_t
93crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */ 94 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 95 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000}, 96 {1, 0x0110000, 0x0120000, 0x130000},
@@ -279,18 +320,8 @@ static unsigned crb_hub_agt[64] =
279 320
280/* PCI Windowing for DDR regions. */ 321/* PCI Windowing for DDR regions. */
281 322
282#define ADDR_IN_RANGE(addr, low, high) \
283 (((addr) <= (high)) && ((addr) >= (low)))
284
285#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ 323#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
286 324
287#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
288#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
289#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
290#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
291
292#define NETXEN_NIC_WINDOW_MARGIN 0x100000
293
294int netxen_nic_set_mac(struct net_device *netdev, void *p) 325int netxen_nic_set_mac(struct net_device *netdev, void *p)
295{ 326{
296 struct netxen_adapter *adapter = netdev_priv(netdev); 327 struct netxen_adapter *adapter = netdev_priv(netdev);
@@ -331,22 +362,20 @@ netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
331 if (adapter->mc_enabled) 362 if (adapter->mc_enabled)
332 return 0; 363 return 0;
333 364
334 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 365 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
335 val |= (1UL << (28+port)); 366 val |= (1UL << (28+port));
336 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 367 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
337 368
338 /* add broadcast addr to filter */ 369 /* add broadcast addr to filter */
339 val = 0xffffff; 370 val = 0xffffff;
340 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 371 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
341 netxen_crb_writelit_adapter(adapter, 372 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
342 NETXEN_UNICAST_ADDR(port, 0)+4, val);
343 373
344 /* add station addr to filter */ 374 /* add station addr to filter */
345 val = MAC_HI(addr); 375 val = MAC_HI(addr);
346 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); 376 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
347 val = MAC_LO(addr); 377 val = MAC_LO(addr);
348 netxen_crb_writelit_adapter(adapter, 378 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
349 NETXEN_UNICAST_ADDR(port, 1)+4, val);
350 379
351 adapter->mc_enabled = 1; 380 adapter->mc_enabled = 1;
352 return 0; 381 return 0;
@@ -362,18 +391,17 @@ netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
362 if (!adapter->mc_enabled) 391 if (!adapter->mc_enabled)
363 return 0; 392 return 0;
364 393
365 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 394 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
366 val &= ~(1UL << (28+port)); 395 val &= ~(1UL << (28+port));
367 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 396 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
368 397
369 val = MAC_HI(addr); 398 val = MAC_HI(addr);
370 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 399 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
371 val = MAC_LO(addr); 400 val = MAC_LO(addr);
372 netxen_crb_writelit_adapter(adapter, 401 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
373 NETXEN_UNICAST_ADDR(port, 0)+4, val);
374 402
375 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); 403 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
376 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); 404 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
377 405
378 adapter->mc_enabled = 0; 406 adapter->mc_enabled = 0;
379 return 0; 407 return 0;
@@ -389,10 +417,8 @@ netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
389 lo = MAC_LO(addr); 417 lo = MAC_LO(addr);
390 hi = MAC_HI(addr); 418 hi = MAC_HI(addr);
391 419
392 netxen_crb_writelit_adapter(adapter, 420 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
393 NETXEN_MCAST_ADDR(port, index), hi); 421 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
394 netxen_crb_writelit_adapter(adapter,
395 NETXEN_MCAST_ADDR(port, index)+4, lo);
396 422
397 return 0; 423 return 0;
398} 424}
@@ -486,45 +512,44 @@ static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
486 512
487static int 513static int
488netxen_send_cmd_descs(struct netxen_adapter *adapter, 514netxen_send_cmd_descs(struct netxen_adapter *adapter,
489 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements) 515 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
490{ 516{
491 uint32_t i, producer; 517 u32 i, producer, consumer;
492 struct netxen_cmd_buffer *pbuf; 518 struct netxen_cmd_buffer *pbuf;
493 struct cmd_desc_type0 *cmd_desc; 519 struct cmd_desc_type0 *cmd_desc;
494 520 struct nx_host_tx_ring *tx_ring;
495 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
496 printk(KERN_WARNING "%s: Too many command descriptors in a "
497 "request\n", __func__);
498 return -EINVAL;
499 }
500 521
501 i = 0; 522 i = 0;
502 523
524 tx_ring = &adapter->tx_ring;
503 netif_tx_lock_bh(adapter->netdev); 525 netif_tx_lock_bh(adapter->netdev);
504 526
505 producer = adapter->cmd_producer; 527 producer = tx_ring->producer;
528 consumer = tx_ring->sw_consumer;
529
530 if (nr_desc > find_diff_among(producer, consumer, tx_ring->num_desc)) {
531 netif_tx_unlock_bh(adapter->netdev);
532 return -EBUSY;
533 }
534
506 do { 535 do {
507 cmd_desc = &cmd_desc_arr[i]; 536 cmd_desc = &cmd_desc_arr[i];
508 537
509 pbuf = &adapter->cmd_buf_arr[producer]; 538 pbuf = &tx_ring->cmd_buf_arr[producer];
510 pbuf->skb = NULL; 539 pbuf->skb = NULL;
511 pbuf->frag_count = 0; 540 pbuf->frag_count = 0;
512 541
513 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */ 542 memcpy(&tx_ring->desc_head[producer],
514 memcpy(&adapter->ahw.cmd_desc_head[producer],
515 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); 543 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
516 544
517 producer = get_next_index(producer, 545 producer = get_next_index(producer, tx_ring->num_desc);
518 adapter->num_txd);
519 i++; 546 i++;
520 547
521 } while (i != nr_elements); 548 } while (i != nr_desc);
522 549
523 adapter->cmd_producer = producer; 550 tx_ring->producer = producer;
524 551
525 /* write producer index to start the xmit */ 552 netxen_nic_update_cmd_producer(adapter, tx_ring, producer);
526
527 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
528 553
529 netif_tx_unlock_bh(adapter->netdev); 554 netif_tx_unlock_bh(adapter->netdev);
530 555
@@ -717,6 +742,28 @@ int netxen_config_rss(struct netxen_adapter *adapter, int enable)
717 return rv; 742 return rv;
718} 743}
719 744
745int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
746{
747 nx_nic_req_t req;
748 u64 word;
749 int rv;
750
751 memset(&req, 0, sizeof(nx_nic_req_t));
752 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
753
754 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
755 req.req_hdr = cpu_to_le64(word);
756 req.words[0] = cpu_to_le64(enable);
757
758 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
759 if (rv != 0) {
760 printk(KERN_ERR "%s: could not configure link notification\n",
761 adapter->netdev->name);
762 }
763
764 return rv;
765}
766
720/* 767/*
721 * netxen_nic_change_mtu - Change the Maximum Transfer Unit 768 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
722 * @returns 0 on success, negative on failure 769 * @returns 0 on success, negative on failure
@@ -812,8 +859,8 @@ int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
812 crbaddr = CRB_MAC_BLOCK_START + 859 crbaddr = CRB_MAC_BLOCK_START +
813 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); 860 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
814 861
815 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4); 862 mac_lo = NXRD32(adapter, crbaddr);
816 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4); 863 mac_hi = NXRD32(adapter, crbaddr+4);
817 864
818 if (pci_func & 1) 865 if (pci_func & 1)
819 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); 866 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
@@ -831,8 +878,7 @@ static int crb_win_lock(struct netxen_adapter *adapter)
831 878
832 while (!done) { 879 while (!done) {
833 /* acquire semaphore3 from PCI HW block */ 880 /* acquire semaphore3 from PCI HW block */
834 adapter->hw_read_wx(adapter, 881 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
835 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
836 if (done == 1) 882 if (done == 1)
837 break; 883 break;
838 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 884 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
@@ -840,8 +886,7 @@ static int crb_win_lock(struct netxen_adapter *adapter)
840 timeout++; 886 timeout++;
841 udelay(1); 887 udelay(1);
842 } 888 }
843 netxen_crb_writelit_adapter(adapter, 889 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
844 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
845 return 0; 890 return 0;
846} 891}
847 892
@@ -849,8 +894,7 @@ static void crb_win_unlock(struct netxen_adapter *adapter)
849{ 894{
850 int val; 895 int val;
851 896
852 adapter->hw_read_wx(adapter, 897 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
853 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
854} 898}
855 899
856/* 900/*
@@ -986,8 +1030,7 @@ netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
986 dev_info(&pdev->dev, "loading firmware from flash\n"); 1030 dev_info(&pdev->dev, "loading firmware from flash\n");
987 1031
988 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 1032 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
989 adapter->pci_write_normalize(adapter, 1033 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
990 NETXEN_ROMUSB_GLB_CAS_RST, 1);
991 1034
992 if (fw) { 1035 if (fw) {
993 __le64 data; 1036 __le64 data;
@@ -1039,13 +1082,10 @@ netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
1039 msleep(1); 1082 msleep(1);
1040 1083
1041 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 1084 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1042 adapter->pci_write_normalize(adapter, 1085 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1043 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1044 else { 1086 else {
1045 adapter->pci_write_normalize(adapter, 1087 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1046 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); 1088 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1047 adapter->pci_write_normalize(adapter,
1048 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1049 } 1089 }
1050 1090
1051 return 0; 1091 return 0;
@@ -1103,8 +1143,7 @@ netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1103 if (NETXEN_VERSION_CODE(major, minor, build) > ver) 1143 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1104 return -EINVAL; 1144 return -EINVAL;
1105 1145
1106 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc), 1146 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1107 NETXEN_BDINFO_MAGIC);
1108 return 0; 1147 return 0;
1109} 1148}
1110 1149
@@ -1132,8 +1171,7 @@ request_mn:
1132 netxen_rom_fast_read(adapter, 1171 netxen_rom_fast_read(adapter,
1133 NX_FW_VERSION_OFFSET, (int *)&flashed_ver); 1172 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1134 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { 1173 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1135 adapter->hw_read_wx(adapter, 1174 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
1136 NX_PEG_TUNE_CAPABILITY, &capability, 4);
1137 if (capability & NX_PEG_TUNE_MN_PRESENT) { 1175 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1138 fw_type = NX_P3_MN_ROMIMAGE; 1176 fw_type = NX_P3_MN_ROMIMAGE;
1139 goto request_fw; 1177 goto request_fw;
@@ -1173,13 +1211,10 @@ load_fw:
1173} 1211}
1174 1212
1175int 1213int
1176netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, 1214netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1177 ulong off, void *data, int len)
1178{ 1215{
1179 void __iomem *addr; 1216 void __iomem *addr;
1180 1217
1181 BUG_ON(len != 4);
1182
1183 if (ADDR_IN_WINDOW1(off)) { 1218 if (ADDR_IN_WINDOW1(off)) {
1184 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1219 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1185 } else { /* Window 0 */ 1220 } else { /* Window 0 */
@@ -1192,7 +1227,7 @@ netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1192 return 1; 1227 return 1;
1193 } 1228 }
1194 1229
1195 writel(*(u32 *) data, addr); 1230 writel(data, addr);
1196 1231
1197 if (!ADDR_IN_WINDOW1(off)) 1232 if (!ADDR_IN_WINDOW1(off))
1198 netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1233 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
@@ -1200,13 +1235,11 @@ netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1200 return 0; 1235 return 0;
1201} 1236}
1202 1237
1203int 1238u32
1204netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, 1239netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1205 ulong off, void *data, int len)
1206{ 1240{
1207 void __iomem *addr; 1241 void __iomem *addr;
1208 1242 u32 data;
1209 BUG_ON(len != 4);
1210 1243
1211 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ 1244 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1212 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1245 addr = NETXEN_CRB_NORMALIZE(adapter, off);
@@ -1220,24 +1253,21 @@ netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1220 return 1; 1253 return 1;
1221 } 1254 }
1222 1255
1223 *(u32 *)data = readl(addr); 1256 data = readl(addr);
1224 1257
1225 if (!ADDR_IN_WINDOW1(off)) 1258 if (!ADDR_IN_WINDOW1(off))
1226 netxen_nic_pci_change_crbwindow_128M(adapter, 1); 1259 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1227 1260
1228 return 0; 1261 return data;
1229} 1262}
1230 1263
1231int 1264int
1232netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, 1265netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1233 ulong off, void *data, int len)
1234{ 1266{
1235 unsigned long flags = 0; 1267 unsigned long flags = 0;
1236 int rv; 1268 int rv;
1237 1269
1238 BUG_ON(len != 4); 1270 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, 4);
1239
1240 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1241 1271
1242 if (rv == -1) { 1272 if (rv == -1) {
1243 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", 1273 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
@@ -1250,26 +1280,24 @@ netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1250 write_lock_irqsave(&adapter->adapter_lock, flags); 1280 write_lock_irqsave(&adapter->adapter_lock, flags);
1251 crb_win_lock(adapter); 1281 crb_win_lock(adapter);
1252 netxen_nic_pci_set_crbwindow_2M(adapter, &off); 1282 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1253 writel(*(uint32_t *)data, (void __iomem *)off); 1283 writel(data, (void __iomem *)off);
1254 crb_win_unlock(adapter); 1284 crb_win_unlock(adapter);
1255 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1285 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1256 } else 1286 } else
1257 writel(*(uint32_t *)data, (void __iomem *)off); 1287 writel(data, (void __iomem *)off);
1258 1288
1259 1289
1260 return 0; 1290 return 0;
1261} 1291}
1262 1292
1263int 1293u32
1264netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, 1294netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1265 ulong off, void *data, int len)
1266{ 1295{
1267 unsigned long flags = 0; 1296 unsigned long flags = 0;
1268 int rv; 1297 int rv;
1298 u32 data;
1269 1299
1270 BUG_ON(len != 4); 1300 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, 4);
1271
1272 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1273 1301
1274 if (rv == -1) { 1302 if (rv == -1) {
1275 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", 1303 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
@@ -1282,47 +1310,13 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1282 write_lock_irqsave(&adapter->adapter_lock, flags); 1310 write_lock_irqsave(&adapter->adapter_lock, flags);
1283 crb_win_lock(adapter); 1311 crb_win_lock(adapter);
1284 netxen_nic_pci_set_crbwindow_2M(adapter, &off); 1312 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1285 *(uint32_t *)data = readl((void __iomem *)off); 1313 data = readl((void __iomem *)off);
1286 crb_win_unlock(adapter); 1314 crb_win_unlock(adapter);
1287 write_unlock_irqrestore(&adapter->adapter_lock, flags); 1315 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1288 } else 1316 } else
1289 *(uint32_t *)data = readl((void __iomem *)off); 1317 data = readl((void __iomem *)off);
1290
1291 return 0;
1292}
1293 1318
1294void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) 1319 return data;
1295{
1296 adapter->hw_write_wx(adapter, off, &val, 4);
1297}
1298
1299int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1300{
1301 int val;
1302 adapter->hw_read_wx(adapter, off, &val, 4);
1303 return val;
1304}
1305
1306/* Change the window to 0, write and change back to window 1. */
1307void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1308{
1309 adapter->hw_write_wx(adapter, index, &value, 4);
1310}
1311
1312/* Change the window to 0, read and change back to window 1. */
1313void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1314{
1315 adapter->hw_read_wx(adapter, index, value, 4);
1316}
1317
1318void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1319{
1320 adapter->hw_write_wx(adapter, index, &value, 4);
1321}
1322
1323void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1324{
1325 adapter->hw_read_wx(adapter, index, value, 4);
1326} 1320}
1327 1321
1328/* 1322/*
@@ -1425,17 +1419,6 @@ u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1425 return readl((void __iomem *)(pci_base_offset(adapter, off))); 1419 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1426} 1420}
1427 1421
1428void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1429 u64 off, u32 data)
1430{
1431 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1432}
1433
1434u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1435{
1436 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1437}
1438
1439unsigned long 1422unsigned long
1440netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, 1423netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1441 unsigned long long addr) 1424 unsigned long long addr)
@@ -1447,12 +1430,10 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1447 /* DDR network side */ 1430 /* DDR network side */
1448 window = MN_WIN(addr); 1431 window = MN_WIN(addr);
1449 adapter->ahw.ddr_mn_window = window; 1432 adapter->ahw.ddr_mn_window = window;
1450 adapter->hw_write_wx(adapter, 1433 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1451 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, 1434 window);
1452 &window, 4); 1435 win_read = NXRD32(adapter,
1453 adapter->hw_read_wx(adapter, 1436 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1454 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1455 &win_read, 4);
1456 if ((win_read << 17) != window) { 1437 if ((win_read << 17) != window) {
1457 printk(KERN_INFO "Written MNwin (0x%x) != " 1438 printk(KERN_INFO "Written MNwin (0x%x) != "
1458 "Read MNwin (0x%x)\n", window, win_read); 1439 "Read MNwin (0x%x)\n", window, win_read);
@@ -1467,12 +1448,10 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1467 1448
1468 window = OCM_WIN(addr); 1449 window = OCM_WIN(addr);
1469 adapter->ahw.ddr_mn_window = window; 1450 adapter->ahw.ddr_mn_window = window;
1470 adapter->hw_write_wx(adapter, 1451 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1471 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, 1452 window);
1472 &window, 4); 1453 win_read = NXRD32(adapter,
1473 adapter->hw_read_wx(adapter, 1454 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1474 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1475 &win_read, 4);
1476 if ((win_read >> 7) != window) { 1455 if ((win_read >> 7) != window) {
1477 printk(KERN_INFO "%s: Written OCMwin (0x%x) != " 1456 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1478 "Read OCMwin (0x%x)\n", 1457 "Read OCMwin (0x%x)\n",
@@ -1485,12 +1464,10 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1485 /* QDR network side */ 1464 /* QDR network side */
1486 window = MS_WIN(addr); 1465 window = MS_WIN(addr);
1487 adapter->ahw.qdr_sn_window = window; 1466 adapter->ahw.qdr_sn_window = window;
1488 adapter->hw_write_wx(adapter, 1467 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1489 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, 1468 window);
1490 &window, 4); 1469 win_read = NXRD32(adapter,
1491 adapter->hw_read_wx(adapter, 1470 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1492 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1493 &win_read, 4);
1494 if (win_read != window) { 1471 if (win_read != window) {
1495 printk(KERN_INFO "%s: Written MSwin (0x%x) != " 1472 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1496 "Read MSwin (0x%x)\n", 1473 "Read MSwin (0x%x)\n",
@@ -1936,27 +1913,20 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1936 1913
1937 for (i = 0; i < loop; i++) { 1914 for (i = 0; i < loop; i++) {
1938 temp = off8 + (i << 3); 1915 temp = off8 + (i << 3);
1939 adapter->hw_write_wx(adapter, 1916 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1940 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1941 temp = 0; 1917 temp = 0;
1942 adapter->hw_write_wx(adapter, 1918 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1943 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1944 temp = word[i] & 0xffffffff; 1919 temp = word[i] & 0xffffffff;
1945 adapter->hw_write_wx(adapter, 1920 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1946 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1947 temp = (word[i] >> 32) & 0xffffffff; 1921 temp = (word[i] >> 32) & 0xffffffff;
1948 adapter->hw_write_wx(adapter, 1922 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1949 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1950 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1923 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1951 adapter->hw_write_wx(adapter, 1924 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1952 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1953 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1925 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1954 adapter->hw_write_wx(adapter, 1926 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1955 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1956 1927
1957 for (j = 0; j < MAX_CTL_CHECK; j++) { 1928 for (j = 0; j < MAX_CTL_CHECK; j++) {
1958 adapter->hw_read_wx(adapter, 1929 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1959 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1960 if ((temp & MIU_TA_CTL_BUSY) == 0) 1930 if ((temp & MIU_TA_CTL_BUSY) == 0)
1961 break; 1931 break;
1962 } 1932 }
@@ -2013,21 +1983,16 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2013 1983
2014 for (i = 0; i < loop; i++) { 1984 for (i = 0; i < loop; i++) {
2015 temp = off8 + (i << 3); 1985 temp = off8 + (i << 3);
2016 adapter->hw_write_wx(adapter, 1986 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
2017 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
2018 temp = 0; 1987 temp = 0;
2019 adapter->hw_write_wx(adapter, 1988 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
2020 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
2021 temp = MIU_TA_CTL_ENABLE; 1989 temp = MIU_TA_CTL_ENABLE;
2022 adapter->hw_write_wx(adapter, 1990 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
2023 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2024 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1991 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2025 adapter->hw_write_wx(adapter, 1992 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
2026 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2027 1993
2028 for (j = 0; j < MAX_CTL_CHECK; j++) { 1994 for (j = 0; j < MAX_CTL_CHECK; j++) {
2029 adapter->hw_read_wx(adapter, 1995 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
2030 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2031 if ((temp & MIU_TA_CTL_BUSY) == 0) 1996 if ((temp & MIU_TA_CTL_BUSY) == 0)
2032 break; 1997 break;
2033 } 1998 }
@@ -2042,8 +2007,8 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2042 start = off0[i] >> 2; 2007 start = off0[i] >> 2;
2043 end = (off0[i] + sz[i] - 1) >> 2; 2008 end = (off0[i] + sz[i] - 1) >> 2;
2044 for (k = start; k <= end; k++) { 2009 for (k = start; k <= end; k++) {
2045 adapter->hw_read_wx(adapter, 2010 temp = NXRD32(adapter,
2046 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4); 2011 mem_crb + MIU_TEST_AGT_RDDATA(k));
2047 word[i] |= ((uint64_t)temp << (32 * k)); 2012 word[i] |= ((uint64_t)temp << (32 * k));
2048 } 2013 }
2049 } 2014 }
@@ -2086,29 +2051,14 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2086int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, 2051int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2087 u64 off, u32 data) 2052 u64 off, u32 data)
2088{ 2053{
2089 adapter->hw_write_wx(adapter, off, &data, 4); 2054 NXWR32(adapter, off, data);
2090 2055
2091 return 0; 2056 return 0;
2092} 2057}
2093 2058
2094u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) 2059u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2095{ 2060{
2096 u32 temp; 2061 return NXRD32(adapter, off);
2097 adapter->hw_read_wx(adapter, off, &temp, 4);
2098 return temp;
2099}
2100
2101void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2102 u64 off, u32 data)
2103{
2104 adapter->hw_write_wx(adapter, off, &data, 4);
2105}
2106
2107u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2108{
2109 u32 temp;
2110 adapter->hw_read_wx(adapter, off, &temp, 4);
2111 return temp;
2112} 2062}
2113 2063
2114int netxen_nic_get_board_info(struct netxen_adapter *adapter) 2064int netxen_nic_get_board_info(struct netxen_adapter *adapter)
@@ -2142,13 +2092,12 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2142 adapter->ahw.board_type = board_type; 2092 adapter->ahw.board_type = board_type;
2143 2093
2144 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { 2094 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2145 u32 gpio = netxen_nic_reg_read(adapter, 2095 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2146 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2147 if ((gpio & 0x8000) == 0) 2096 if ((gpio & 0x8000) == 0)
2148 board_type = NETXEN_BRDTYPE_P3_10G_TP; 2097 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2149 } 2098 }
2150 2099
2151 switch ((netxen_brdtype_t)board_type) { 2100 switch (board_type) {
2152 case NETXEN_BRDTYPE_P2_SB35_4G: 2101 case NETXEN_BRDTYPE_P2_SB35_4G:
2153 adapter->ahw.port_type = NETXEN_NIC_GBE; 2102 adapter->ahw.port_type = NETXEN_NIC_GBE;
2154 break; 2103 break;
@@ -2195,8 +2144,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2195int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) 2144int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2196{ 2145{
2197 new_mtu += MTU_FUDGE_FACTOR; 2146 new_mtu += MTU_FUDGE_FACTOR;
2198 netxen_nic_write_w0(adapter, 2147 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2199 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2200 new_mtu); 2148 new_mtu);
2201 return 0; 2149 return 0;
2202} 2150}
@@ -2205,21 +2153,12 @@ int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2205{ 2153{
2206 new_mtu += MTU_FUDGE_FACTOR; 2154 new_mtu += MTU_FUDGE_FACTOR;
2207 if (adapter->physical_port == 0) 2155 if (adapter->physical_port == 0)
2208 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, 2156 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2209 new_mtu);
2210 else 2157 else
2211 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, 2158 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2212 new_mtu);
2213 return 0; 2159 return 0;
2214} 2160}
2215 2161
2216void
2217netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2218 unsigned long off, int data)
2219{
2220 adapter->hw_write_wx(adapter, off, &data, 4);
2221}
2222
2223void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 2162void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2224{ 2163{
2225 __u32 status; 2164 __u32 status;
@@ -2234,8 +2173,7 @@ void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2234 } 2173 }
2235 2174
2236 if (adapter->ahw.port_type == NETXEN_NIC_GBE) { 2175 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2237 adapter->hw_read_wx(adapter, 2176 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2238 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2239 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 2177 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2240 adapter->link_speed = SPEED_1000; 2178 adapter->link_speed = SPEED_1000;
2241 adapter->link_duplex = DUPLEX_FULL; 2179 adapter->link_duplex = DUPLEX_FULL;
@@ -2312,9 +2250,9 @@ void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2312 addr += sizeof(u32); 2250 addr += sizeof(u32);
2313 } 2251 }
2314 2252
2315 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4); 2253 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2316 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4); 2254 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2317 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4); 2255 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2318 2256
2319 adapter->fw_major = fw_major; 2257 adapter->fw_major = fw_major;
2320 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build); 2258 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
@@ -2337,8 +2275,7 @@ void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2337 fw_major, fw_minor, fw_build); 2275 fw_major, fw_minor, fw_build);
2338 2276
2339 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 2277 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2340 adapter->hw_read_wx(adapter, 2278 i = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
2341 NETXEN_MIU_MN_CONTROL, &i, 4);
2342 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0; 2279 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2343 dev_info(&pdev->dev, "firmware running in %s mode\n", 2280 dev_info(&pdev->dev, "firmware running in %s mode\n",
2344 adapter->ahw.cut_through ? "cut-through" : "legacy"); 2281 adapter->ahw.cut_through ? "cut-through" : "legacy");
@@ -2353,9 +2290,9 @@ netxen_nic_wol_supported(struct netxen_adapter *adapter)
2353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 2290 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2354 return 0; 2291 return 0;
2355 2292
2356 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 2293 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2357 if (wol_cfg & (1UL << adapter->portnum)) { 2294 if (wol_cfg & (1UL << adapter->portnum)) {
2358 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 2295 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2359 if (wol_cfg & (1 << adapter->portnum)) 2296 if (wol_cfg & (1 << adapter->portnum))
2360 return 1; 2297 return 1;
2361 } 2298 }
diff --git a/drivers/net/netxen/netxen_nic_hw.h b/drivers/net/netxen/netxen_nic_hw.h
index 04b47a7993cd..f20c96591a87 100644
--- a/drivers/net/netxen/netxen_nic_hw.h
+++ b/drivers/net/netxen/netxen_nic_hw.h
@@ -36,35 +36,15 @@
36/* Hardware memory size of 128 meg */ 36/* Hardware memory size of 128 meg */
37#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024) 37#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
38 38
39#ifndef readq
40static inline u64 readq(void __iomem * addr)
41{
42 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
43}
44#endif
45
46#ifndef writeq
47static inline void writeq(u64 val, void __iomem * addr)
48{
49 writel(((u32) (val)), (addr));
50 writel(((u32) (val >> 32)), (addr + 4));
51}
52#endif
53
54struct netxen_adapter; 39struct netxen_adapter;
55 40
56#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20) 41#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
57 42
58struct netxen_port;
59void netxen_nic_set_link_parameters(struct netxen_adapter *adapter); 43void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
60 44
61typedef u8 netxen_ethernet_macaddr_t[6]; 45typedef u8 netxen_ethernet_macaddr_t[6];
62 46
63/* Nibble or Byte mode for phy interface (GbE mode only) */ 47/* Nibble or Byte mode for phy interface (GbE mode only) */
64typedef enum {
65 NETXEN_NIU_10_100_MB = 0,
66 NETXEN_NIU_1000_MB
67} netxen_niu_gbe_ifmode_t;
68 48
69#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1) 49#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
70 50
@@ -222,30 +202,28 @@ typedef enum {
222/* 202/*
223 * PHY-Specific MII control/status registers. 203 * PHY-Specific MII control/status registers.
224 */ 204 */
225typedef enum { 205#define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL 0
226 NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0, 206#define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS 1
227 NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1, 207#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 2
228 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2, 208#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 3
229 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3, 209#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
230 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4, 210#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART 5
231 NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5, 211#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE 6
232 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6, 212#define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT 7
233 NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7, 213#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE 8
234 NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8, 214#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL 9
235 NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9, 215#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS 10
236 NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10, 216#define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS 15
237 NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15, 217#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL 16
238 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16, 218#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
239 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17, 219#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE 18
240 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18, 220#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS 19
241 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19, 221#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE 20
242 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20, 222#define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT 21
243 NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21, 223#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL 24
244 NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24, 224#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE 25
245 NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25, 225#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET 26
246 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26, 226#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE 27
247 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
248} netxen_niu_phy_register_t;
249 227
250/* 228/*
251 * PHY-Specific Status Register (reg 17). 229 * PHY-Specific Status Register (reg 17).
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index 0759c35f16ac..8893a973399a 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -108,42 +108,6 @@ static void crb_addr_transform_setup(void)
108 crb_addr_transform(I2C0); 108 crb_addr_transform(I2C0);
109} 109}
110 110
111int netxen_init_firmware(struct netxen_adapter *adapter)
112{
113 u32 state = 0, loops = 0, err = 0;
114
115 /* Window 1 call */
116 state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
117
118 if (state == PHAN_INITIALIZE_ACK)
119 return 0;
120
121 while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
122 msleep(1);
123 /* Window 1 call */
124 state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
125
126 loops++;
127 }
128 if (loops >= 2000) {
129 printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
130 state);
131 err = -EIO;
132 return err;
133 }
134 /* Window 1 call */
135 adapter->pci_write_normalize(adapter,
136 CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
137 adapter->pci_write_normalize(adapter,
138 CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
139 adapter->pci_write_normalize(adapter,
140 CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
141 adapter->pci_write_normalize(adapter,
142 CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
143
144 return err;
145}
146
147void netxen_release_rx_buffers(struct netxen_adapter *adapter) 111void netxen_release_rx_buffers(struct netxen_adapter *adapter)
148{ 112{
149 struct netxen_recv_context *recv_ctx; 113 struct netxen_recv_context *recv_ctx;
@@ -173,9 +137,10 @@ void netxen_release_tx_buffers(struct netxen_adapter *adapter)
173 struct netxen_cmd_buffer *cmd_buf; 137 struct netxen_cmd_buffer *cmd_buf;
174 struct netxen_skb_frag *buffrag; 138 struct netxen_skb_frag *buffrag;
175 int i, j; 139 int i, j;
140 struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
176 141
177 cmd_buf = adapter->cmd_buf_arr; 142 cmd_buf = tx_ring->cmd_buf_arr;
178 for (i = 0; i < adapter->num_txd; i++) { 143 for (i = 0; i < tx_ring->num_desc; i++) {
179 buffrag = cmd_buf->frag_array; 144 buffrag = cmd_buf->frag_array;
180 if (buffrag->dma) { 145 if (buffrag->dma) {
181 pci_unmap_single(adapter->pdev, buffrag->dma, 146 pci_unmap_single(adapter->pdev, buffrag->dma,
@@ -203,6 +168,7 @@ void netxen_free_sw_resources(struct netxen_adapter *adapter)
203{ 168{
204 struct netxen_recv_context *recv_ctx; 169 struct netxen_recv_context *recv_ctx;
205 struct nx_host_rds_ring *rds_ring; 170 struct nx_host_rds_ring *rds_ring;
171 struct nx_host_tx_ring *tx_ring;
206 int ring; 172 int ring;
207 173
208 recv_ctx = &adapter->recv_ctx; 174 recv_ctx = &adapter->recv_ctx;
@@ -214,8 +180,9 @@ void netxen_free_sw_resources(struct netxen_adapter *adapter)
214 } 180 }
215 } 181 }
216 182
217 if (adapter->cmd_buf_arr) 183 tx_ring = &adapter->tx_ring;
218 vfree(adapter->cmd_buf_arr); 184 if (tx_ring->cmd_buf_arr)
185 vfree(tx_ring->cmd_buf_arr);
219 return; 186 return;
220} 187}
221 188
@@ -224,21 +191,24 @@ int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
224 struct netxen_recv_context *recv_ctx; 191 struct netxen_recv_context *recv_ctx;
225 struct nx_host_rds_ring *rds_ring; 192 struct nx_host_rds_ring *rds_ring;
226 struct nx_host_sds_ring *sds_ring; 193 struct nx_host_sds_ring *sds_ring;
194 struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
227 struct netxen_rx_buffer *rx_buf; 195 struct netxen_rx_buffer *rx_buf;
228 int ring, i, num_rx_bufs; 196 int ring, i, num_rx_bufs;
229 197
230 struct netxen_cmd_buffer *cmd_buf_arr; 198 struct netxen_cmd_buffer *cmd_buf_arr;
231 struct net_device *netdev = adapter->netdev; 199 struct net_device *netdev = adapter->netdev;
200 struct pci_dev *pdev = adapter->pdev;
232 201
202 tx_ring->num_desc = adapter->num_txd;
233 cmd_buf_arr = 203 cmd_buf_arr =
234 (struct netxen_cmd_buffer *)vmalloc(TX_BUFF_RINGSIZE(adapter)); 204 (struct netxen_cmd_buffer *)vmalloc(TX_BUFF_RINGSIZE(tx_ring));
235 if (cmd_buf_arr == NULL) { 205 if (cmd_buf_arr == NULL) {
236 printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n", 206 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
237 netdev->name); 207 netdev->name);
238 return -ENOMEM; 208 return -ENOMEM;
239 } 209 }
240 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(adapter)); 210 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
241 adapter->cmd_buf_arr = cmd_buf_arr; 211 tx_ring->cmd_buf_arr = cmd_buf_arr;
242 212
243 recv_ctx = &adapter->recv_ctx; 213 recv_ctx = &adapter->recv_ctx;
244 for (ring = 0; ring < adapter->max_rds_rings; ring++) { 214 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
@@ -307,8 +277,6 @@ int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
307 for (ring = 0; ring < adapter->max_sds_rings; ring++) { 277 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
308 sds_ring = &recv_ctx->sds_rings[ring]; 278 sds_ring = &recv_ctx->sds_rings[ring];
309 sds_ring->irq = adapter->msix_entries[ring].vector; 279 sds_ring->irq = adapter->msix_entries[ring].vector;
310 sds_ring->clean_tx = (ring == 0);
311 sds_ring->post_rxd = (ring == 0);
312 sds_ring->adapter = adapter; 280 sds_ring->adapter = adapter;
313 sds_ring->num_desc = adapter->num_rxd; 281 sds_ring->num_desc = adapter->num_rxd;
314 282
@@ -400,8 +368,7 @@ static int rom_lock(struct netxen_adapter *adapter)
400 368
401 while (!done) { 369 while (!done) {
402 /* acquire semaphore2 from PCI HW block */ 370 /* acquire semaphore2 from PCI HW block */
403 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK), 371 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
404 &done);
405 if (done == 1) 372 if (done == 1)
406 break; 373 break;
407 if (timeout >= rom_lock_timeout) 374 if (timeout >= rom_lock_timeout)
@@ -418,7 +385,7 @@ static int rom_lock(struct netxen_adapter *adapter)
418 cpu_relax(); /*This a nop instr on i386 */ 385 cpu_relax(); /*This a nop instr on i386 */
419 } 386 }
420 } 387 }
421 netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); 388 NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
422 return 0; 389 return 0;
423} 390}
424 391
@@ -430,7 +397,7 @@ static int netxen_wait_rom_done(struct netxen_adapter *adapter)
430 cond_resched(); 397 cond_resched();
431 398
432 while (done == 0) { 399 while (done == 0) {
433 done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); 400 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
434 done &= 2; 401 done &= 2;
435 timeout++; 402 timeout++;
436 if (timeout >= rom_max_timeout) { 403 if (timeout >= rom_max_timeout) {
@@ -443,30 +410,28 @@ static int netxen_wait_rom_done(struct netxen_adapter *adapter)
443 410
444static void netxen_rom_unlock(struct netxen_adapter *adapter) 411static void netxen_rom_unlock(struct netxen_adapter *adapter)
445{ 412{
446 u32 val;
447
448 /* release semaphore2 */ 413 /* release semaphore2 */
449 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val); 414 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
450 415
451} 416}
452 417
453static int do_rom_fast_read(struct netxen_adapter *adapter, 418static int do_rom_fast_read(struct netxen_adapter *adapter,
454 int addr, int *valp) 419 int addr, int *valp)
455{ 420{
456 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); 421 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
457 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 422 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
458 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); 423 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
459 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); 424 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
460 if (netxen_wait_rom_done(adapter)) { 425 if (netxen_wait_rom_done(adapter)) {
461 printk("Error waiting for rom done\n"); 426 printk("Error waiting for rom done\n");
462 return -EIO; 427 return -EIO;
463 } 428 }
464 /* reset abyte_cnt and dummy_byte_cnt */ 429 /* reset abyte_cnt and dummy_byte_cnt */
465 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); 430 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
466 udelay(10); 431 udelay(10);
467 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 432 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
468 433
469 *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); 434 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
470 return 0; 435 return 0;
471} 436}
472 437
@@ -530,8 +495,7 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
530 495
531 /* resetall */ 496 /* resetall */
532 rom_lock(adapter); 497 rom_lock(adapter);
533 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 498 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
534 0xffffffff);
535 netxen_rom_unlock(adapter); 499 netxen_rom_unlock(adapter);
536 500
537 if (verbose) { 501 if (verbose) {
@@ -655,7 +619,7 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
655 } 619 }
656 } 620 }
657 621
658 adapter->hw_write_wx(adapter, off, &buf[i].data, 4); 622 NXWR32(adapter, off, buf[i].data);
659 623
660 msleep(init_delay); 624 msleep(init_delay);
661 } 625 }
@@ -665,33 +629,31 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
665 629
666 /* unreset_net_cache */ 630 /* unreset_net_cache */
667 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 631 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
668 adapter->hw_read_wx(adapter, 632 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
669 NETXEN_ROMUSB_GLB_SW_RESET, &val, 4); 633 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
670 netxen_crb_writelit_adapter(adapter,
671 NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
672 } 634 }
673 635
674 /* p2dn replyCount */ 636 /* p2dn replyCount */
675 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); 637 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
676 /* disable_peg_cache 0 */ 638 /* disable_peg_cache 0 */
677 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); 639 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
678 /* disable_peg_cache 1 */ 640 /* disable_peg_cache 1 */
679 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); 641 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
680 642
681 /* peg_clr_all */ 643 /* peg_clr_all */
682 644
683 /* peg_clr 0 */ 645 /* peg_clr 0 */
684 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); 646 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
685 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); 647 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
686 /* peg_clr 1 */ 648 /* peg_clr 1 */
687 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); 649 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
688 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); 650 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
689 /* peg_clr 2 */ 651 /* peg_clr 2 */
690 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); 652 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
691 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); 653 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
692 /* peg_clr 3 */ 654 /* peg_clr 3 */
693 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); 655 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
694 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); 656 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
695 return 0; 657 return 0;
696} 658}
697 659
@@ -715,12 +677,12 @@ int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
715 hi = (addr >> 32) & 0xffffffff; 677 hi = (addr >> 32) & 0xffffffff;
716 lo = addr & 0xffffffff; 678 lo = addr & 0xffffffff;
717 679
718 adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); 680 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
719 adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); 681 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
720 682
721 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 683 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
722 uint32_t temp = 0; 684 uint32_t temp = 0;
723 adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4); 685 NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp);
724 } 686 }
725 687
726 return 0; 688 return 0;
@@ -762,8 +724,7 @@ int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
762 724
763 if (!pegtune_val) { 725 if (!pegtune_val) {
764 do { 726 do {
765 val = adapter->pci_read_normalize(adapter, 727 val = NXRD32(adapter, CRB_CMDPEG_STATE);
766 CRB_CMDPEG_STATE);
767 728
768 if (val == PHAN_INITIALIZE_COMPLETE || 729 if (val == PHAN_INITIALIZE_COMPLETE ||
769 val == PHAN_INITIALIZE_ACK) 730 val == PHAN_INITIALIZE_ACK)
@@ -774,7 +735,7 @@ int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
774 } while (--retries); 735 } while (--retries);
775 736
776 if (!retries) { 737 if (!retries) {
777 pegtune_val = adapter->pci_read_normalize(adapter, 738 pegtune_val = NXRD32(adapter,
778 NETXEN_ROMUSB_GLB_PEGTUNE_DONE); 739 NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
779 printk(KERN_WARNING "netxen_phantom_init: init failed, " 740 printk(KERN_WARNING "netxen_phantom_init: init failed, "
780 "pegtune_val=%x\n", pegtune_val); 741 "pegtune_val=%x\n", pegtune_val);
@@ -785,13 +746,14 @@ int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
785 return 0; 746 return 0;
786} 747}
787 748
788int netxen_receive_peg_ready(struct netxen_adapter *adapter) 749static int
750netxen_receive_peg_ready(struct netxen_adapter *adapter)
789{ 751{
790 u32 val = 0; 752 u32 val = 0;
791 int retries = 2000; 753 int retries = 2000;
792 754
793 do { 755 do {
794 val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE); 756 val = NXRD32(adapter, CRB_RCVPEG_STATE);
795 757
796 if (val == PHAN_PEG_RCV_INITIALIZED) 758 if (val == PHAN_PEG_RCV_INITIALIZED)
797 return 0; 759 return 0;
@@ -809,6 +771,93 @@ int netxen_receive_peg_ready(struct netxen_adapter *adapter)
809 return 0; 771 return 0;
810} 772}
811 773
774int netxen_init_firmware(struct netxen_adapter *adapter)
775{
776 int err;
777
778 err = netxen_receive_peg_ready(adapter);
779 if (err)
780 return err;
781
782 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
783 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
784 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
785 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
786
787 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) {
788 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
789 }
790
791 return err;
792}
793
794static void
795netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
796{
797 u32 cable_OUI;
798 u16 cable_len;
799 u16 link_speed;
800 u8 link_status, module, duplex, autoneg;
801 struct net_device *netdev = adapter->netdev;
802
803 adapter->has_link_events = 1;
804
805 cable_OUI = msg->body[1] & 0xffffffff;
806 cable_len = (msg->body[1] >> 32) & 0xffff;
807 link_speed = (msg->body[1] >> 48) & 0xffff;
808
809 link_status = msg->body[2] & 0xff;
810 duplex = (msg->body[2] >> 16) & 0xff;
811 autoneg = (msg->body[2] >> 24) & 0xff;
812
813 module = (msg->body[2] >> 8) & 0xff;
814 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
815 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
816 netdev->name, cable_OUI, cable_len);
817 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
818 printk(KERN_INFO "%s: unsupported cable length %d\n",
819 netdev->name, cable_len);
820 }
821
822 netxen_advert_link_change(adapter, link_status);
823
824 /* update link parameters */
825 if (duplex == LINKEVENT_FULL_DUPLEX)
826 adapter->link_duplex = DUPLEX_FULL;
827 else
828 adapter->link_duplex = DUPLEX_HALF;
829 adapter->module_type = module;
830 adapter->link_autoneg = autoneg;
831 adapter->link_speed = link_speed;
832}
833
834static void
835netxen_handle_fw_message(int desc_cnt, int index,
836 struct nx_host_sds_ring *sds_ring)
837{
838 nx_fw_msg_t msg;
839 struct status_desc *desc;
840 int i = 0, opcode;
841
842 while (desc_cnt > 0 && i < 8) {
843 desc = &sds_ring->desc_head[index];
844 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
845 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
846
847 index = get_next_index(index, sds_ring->num_desc);
848 desc_cnt--;
849 }
850
851 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
852 switch (opcode) {
853 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
854 netxen_handle_linkevent(sds_ring->adapter, &msg);
855 break;
856 default:
857 break;
858 }
859}
860
812static int 861static int
813netxen_alloc_rx_skb(struct netxen_adapter *adapter, 862netxen_alloc_rx_skb(struct netxen_adapter *adapter,
814 struct nx_host_rds_ring *rds_ring, 863 struct nx_host_rds_ring *rds_ring,
@@ -874,7 +923,8 @@ no_skb:
874 923
875static struct netxen_rx_buffer * 924static struct netxen_rx_buffer *
876netxen_process_rcv(struct netxen_adapter *adapter, 925netxen_process_rcv(struct netxen_adapter *adapter,
877 int ring, int index, int length, int cksum, int pkt_offset) 926 int ring, int index, int length, int cksum, int pkt_offset,
927 struct nx_host_sds_ring *sds_ring)
878{ 928{
879 struct net_device *netdev = adapter->netdev; 929 struct net_device *netdev = adapter->netdev;
880 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; 930 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
@@ -902,7 +952,7 @@ netxen_process_rcv(struct netxen_adapter *adapter,
902 952
903 skb->protocol = eth_type_trans(skb, netdev); 953 skb->protocol = eth_type_trans(skb, netdev);
904 954
905 netif_receive_skb(skb); 955 napi_gro_receive(&sds_ring->napi, skb);
906 956
907 adapter->stats.no_rcv++; 957 adapter->stats.no_rcv++;
908 adapter->stats.rxbytes += length; 958 adapter->stats.rxbytes += length;
@@ -927,35 +977,53 @@ netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
927 977
928 int count = 0; 978 int count = 0;
929 u64 sts_data; 979 u64 sts_data;
930 int opcode, ring, index, length, cksum, pkt_offset; 980 int opcode, ring, index, length, cksum, pkt_offset, desc_cnt;
931 981
932 while (count < max) { 982 while (count < max) {
933 desc = &sds_ring->desc_head[consumer]; 983 desc = &sds_ring->desc_head[consumer];
934 sts_data = le64_to_cpu(desc->status_desc_data); 984 sts_data = le64_to_cpu(desc->status_desc_data[0]);
935 985
936 if (!(sts_data & STATUS_OWNER_HOST)) 986 if (!(sts_data & STATUS_OWNER_HOST))
937 break; 987 break;
938 988
989 desc_cnt = netxen_get_sts_desc_cnt(sts_data);
939 ring = netxen_get_sts_type(sts_data); 990 ring = netxen_get_sts_type(sts_data);
991
940 if (ring > RCV_RING_JUMBO) 992 if (ring > RCV_RING_JUMBO)
941 continue; 993 goto skip;
942 994
943 opcode = netxen_get_sts_opcode(sts_data); 995 opcode = netxen_get_sts_opcode(sts_data);
944 996
997 switch (opcode) {
998 case NETXEN_NIC_RXPKT_DESC:
999 case NETXEN_OLD_RXPKT_DESC:
1000 break;
1001 case NETXEN_NIC_RESPONSE_DESC:
1002 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1003 default:
1004 goto skip;
1005 }
1006
1007 WARN_ON(desc_cnt > 1);
1008
945 index = netxen_get_sts_refhandle(sts_data); 1009 index = netxen_get_sts_refhandle(sts_data);
946 length = netxen_get_sts_totallength(sts_data); 1010 length = netxen_get_sts_totallength(sts_data);
947 cksum = netxen_get_sts_status(sts_data); 1011 cksum = netxen_get_sts_status(sts_data);
948 pkt_offset = netxen_get_sts_pkt_offset(sts_data); 1012 pkt_offset = netxen_get_sts_pkt_offset(sts_data);
949 1013
950 rxbuf = netxen_process_rcv(adapter, ring, index, 1014 rxbuf = netxen_process_rcv(adapter, ring, index,
951 length, cksum, pkt_offset); 1015 length, cksum, pkt_offset, sds_ring);
952 1016
953 if (rxbuf) 1017 if (rxbuf)
954 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]); 1018 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
955 1019
956 desc->status_desc_data = cpu_to_le64(STATUS_OWNER_PHANTOM); 1020skip:
957 1021 for (; desc_cnt > 0; desc_cnt--) {
958 consumer = get_next_index(consumer, sds_ring->num_desc); 1022 desc = &sds_ring->desc_head[consumer];
1023 desc->status_desc_data[0] =
1024 cpu_to_le64(STATUS_OWNER_PHANTOM);
1025 consumer = get_next_index(consumer, sds_ring->num_desc);
1026 }
959 count++; 1027 count++;
960 } 1028 }
961 1029
@@ -980,8 +1048,7 @@ netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
980 1048
981 if (count) { 1049 if (count) {
982 sds_ring->consumer = consumer; 1050 sds_ring->consumer = consumer;
983 adapter->pci_write_normalize(adapter, 1051 NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
984 sds_ring->crb_sts_consumer, consumer);
985 } 1052 }
986 1053
987 return count; 1054 return count;
@@ -990,23 +1057,24 @@ netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
990/* Process Command status ring */ 1057/* Process Command status ring */
991int netxen_process_cmd_ring(struct netxen_adapter *adapter) 1058int netxen_process_cmd_ring(struct netxen_adapter *adapter)
992{ 1059{
993 u32 last_consumer, consumer; 1060 u32 sw_consumer, hw_consumer;
994 int count = 0, i; 1061 int count = 0, i;
995 struct netxen_cmd_buffer *buffer; 1062 struct netxen_cmd_buffer *buffer;
996 struct pci_dev *pdev = adapter->pdev; 1063 struct pci_dev *pdev = adapter->pdev;
997 struct net_device *netdev = adapter->netdev; 1064 struct net_device *netdev = adapter->netdev;
998 struct netxen_skb_frag *frag; 1065 struct netxen_skb_frag *frag;
999 int done = 0; 1066 int done = 0;
1067 struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
1000 1068
1001 if (!spin_trylock(&adapter->tx_clean_lock)) 1069 if (!spin_trylock(&adapter->tx_clean_lock))
1002 return 1; 1070 return 1;
1003 1071
1004 last_consumer = adapter->last_cmd_consumer; 1072 sw_consumer = tx_ring->sw_consumer;
1005 barrier(); /* cmd_consumer can change underneath */ 1073 barrier(); /* hw_consumer can change underneath */
1006 consumer = le32_to_cpu(*(adapter->cmd_consumer)); 1074 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1007 1075
1008 while (last_consumer != consumer) { 1076 while (sw_consumer != hw_consumer) {
1009 buffer = &adapter->cmd_buf_arr[last_consumer]; 1077 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
1010 if (buffer->skb) { 1078 if (buffer->skb) {
1011 frag = &buffer->frag_array[0]; 1079 frag = &buffer->frag_array[0];
1012 pci_unmap_single(pdev, frag->dma, frag->length, 1080 pci_unmap_single(pdev, frag->dma, frag->length,
@@ -1024,14 +1092,13 @@ int netxen_process_cmd_ring(struct netxen_adapter *adapter)
1024 buffer->skb = NULL; 1092 buffer->skb = NULL;
1025 } 1093 }
1026 1094
1027 last_consumer = get_next_index(last_consumer, 1095 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
1028 adapter->num_txd);
1029 if (++count >= MAX_STATUS_HANDLE) 1096 if (++count >= MAX_STATUS_HANDLE)
1030 break; 1097 break;
1031 } 1098 }
1032 1099
1033 if (count) { 1100 if (count) {
1034 adapter->last_cmd_consumer = last_consumer; 1101 tx_ring->sw_consumer = sw_consumer;
1035 smp_mb(); 1102 smp_mb();
1036 if (netif_queue_stopped(netdev) && netif_running(netdev)) { 1103 if (netif_queue_stopped(netdev) && netif_running(netdev)) {
1037 netif_tx_lock(netdev); 1104 netif_tx_lock(netdev);
@@ -1053,9 +1120,9 @@ int netxen_process_cmd_ring(struct netxen_adapter *adapter)
1053 * There is still a possible race condition and the host could miss an 1120 * There is still a possible race condition and the host could miss an
1054 * interrupt. The card has to take care of this. 1121 * interrupt. The card has to take care of this.
1055 */ 1122 */
1056 barrier(); /* cmd_consumer can change underneath */ 1123 barrier(); /* hw_consumer can change underneath */
1057 consumer = le32_to_cpu(*(adapter->cmd_consumer)); 1124 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1058 done = (last_consumer == consumer); 1125 done = (sw_consumer == hw_consumer);
1059 spin_unlock(&adapter->tx_clean_lock); 1126 spin_unlock(&adapter->tx_clean_lock);
1060 1127
1061 return (done); 1128 return (done);
@@ -1099,8 +1166,7 @@ netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1099 1166
1100 if (count) { 1167 if (count) {
1101 rds_ring->producer = producer; 1168 rds_ring->producer = producer;
1102 adapter->pci_write_normalize(adapter, 1169 NXWR32(adapter, rds_ring->crb_rcv_producer,
1103 rds_ring->crb_rcv_producer,
1104 (producer-1) & (rds_ring->num_desc-1)); 1170 (producer-1) & (rds_ring->num_desc-1));
1105 1171
1106 if (adapter->fw_major < 4) { 1172 if (adapter->fw_major < 4) {
@@ -1160,8 +1226,7 @@ netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1160 1226
1161 if (count) { 1227 if (count) {
1162 rds_ring->producer = producer; 1228 rds_ring->producer = producer;
1163 adapter->pci_write_normalize(adapter, 1229 NXWR32(adapter, rds_ring->crb_rcv_producer,
1164 rds_ring->crb_rcv_producer,
1165 (producer - 1) & (rds_ring->num_desc - 1)); 1230 (producer - 1) & (rds_ring->num_desc - 1));
1166 wmb(); 1231 wmb();
1167 } 1232 }
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index aef77289bd34..e877eefdfeb0 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -29,7 +29,7 @@
29 */ 29 */
30 30
31#include <linux/vmalloc.h> 31#include <linux/vmalloc.h>
32#include <linux/highmem.h> 32#include <linux/interrupt.h>
33#include "netxen_nic_hw.h" 33#include "netxen_nic_hw.h"
34 34
35#include "netxen_nic.h" 35#include "netxen_nic.h"
@@ -107,10 +107,9 @@ static uint32_t crb_cmd_producer[4] = {
107 107
108void 108void
109netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, 109netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
110 uint32_t crb_producer) 110 struct nx_host_tx_ring *tx_ring, u32 producer)
111{ 111{
112 adapter->pci_write_normalize(adapter, 112 NXWR32(adapter, tx_ring->crb_cmd_producer, producer);
113 adapter->crb_addr_cmd_producer, crb_producer);
114} 113}
115 114
116static uint32_t crb_cmd_consumer[4] = { 115static uint32_t crb_cmd_consumer[4] = {
@@ -120,10 +119,9 @@ static uint32_t crb_cmd_consumer[4] = {
120 119
121static inline void 120static inline void
122netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter, 121netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter,
123 u32 crb_consumer) 122 struct nx_host_tx_ring *tx_ring, u32 consumer)
124{ 123{
125 adapter->pci_write_normalize(adapter, 124 NXWR32(adapter, tx_ring->crb_cmd_consumer, consumer);
126 adapter->crb_addr_cmd_consumer, crb_consumer);
127} 125}
128 126
129static uint32_t msi_tgt_status[8] = { 127static uint32_t msi_tgt_status[8] = {
@@ -139,37 +137,60 @@ static inline void netxen_nic_disable_int(struct nx_host_sds_ring *sds_ring)
139{ 137{
140 struct netxen_adapter *adapter = sds_ring->adapter; 138 struct netxen_adapter *adapter = sds_ring->adapter;
141 139
142 adapter->pci_write_normalize(adapter, sds_ring->crb_intr_mask, 0); 140 NXWR32(adapter, sds_ring->crb_intr_mask, 0);
143} 141}
144 142
145static inline void netxen_nic_enable_int(struct nx_host_sds_ring *sds_ring) 143static inline void netxen_nic_enable_int(struct nx_host_sds_ring *sds_ring)
146{ 144{
147 struct netxen_adapter *adapter = sds_ring->adapter; 145 struct netxen_adapter *adapter = sds_ring->adapter;
148 146
149 adapter->pci_write_normalize(adapter, sds_ring->crb_intr_mask, 0x1); 147 NXWR32(adapter, sds_ring->crb_intr_mask, 0x1);
150 148
151 if (!NETXEN_IS_MSI_FAMILY(adapter)) 149 if (!NETXEN_IS_MSI_FAMILY(adapter))
152 adapter->pci_write_immediate(adapter, 150 adapter->pci_write_immediate(adapter,
153 adapter->legacy_intr.tgt_mask_reg, 0xfbff); 151 adapter->legacy_intr.tgt_mask_reg, 0xfbff);
154} 152}
155 153
154static int
155netxen_alloc_sds_rings(struct netxen_recv_context *recv_ctx, int count)
156{
157 int size = sizeof(struct nx_host_sds_ring) * count;
158
159 recv_ctx->sds_rings = kzalloc(size, GFP_KERNEL);
160
161 return (recv_ctx->sds_rings == NULL);
162}
163
156static void 164static void
165netxen_free_sds_rings(struct netxen_recv_context *recv_ctx)
166{
167 if (recv_ctx->sds_rings != NULL)
168 kfree(recv_ctx->sds_rings);
169}
170
171static int
157netxen_napi_add(struct netxen_adapter *adapter, struct net_device *netdev) 172netxen_napi_add(struct netxen_adapter *adapter, struct net_device *netdev)
158{ 173{
159 int ring; 174 int ring;
160 struct nx_host_sds_ring *sds_ring; 175 struct nx_host_sds_ring *sds_ring;
161 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; 176 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
162 177
163 if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) 178 if ((adapter->flags & NETXEN_NIC_MSIX_ENABLED) &&
179 adapter->rss_supported)
164 adapter->max_sds_rings = (num_online_cpus() >= 4) ? 4 : 2; 180 adapter->max_sds_rings = (num_online_cpus() >= 4) ? 4 : 2;
165 else 181 else
166 adapter->max_sds_rings = 1; 182 adapter->max_sds_rings = 1;
167 183
184 if (netxen_alloc_sds_rings(recv_ctx, adapter->max_sds_rings))
185 return 1;
186
168 for (ring = 0; ring < adapter->max_sds_rings; ring++) { 187 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
169 sds_ring = &recv_ctx->sds_rings[ring]; 188 sds_ring = &recv_ctx->sds_rings[ring];
170 netif_napi_add(netdev, &sds_ring->napi, 189 netif_napi_add(netdev, &sds_ring->napi,
171 netxen_nic_poll, NETXEN_NETDEV_WEIGHT); 190 netxen_nic_poll, NETXEN_NETDEV_WEIGHT);
172 } 191 }
192
193 return 0;
173} 194}
174 195
175static void 196static void
@@ -240,7 +261,7 @@ nx_update_dma_mask(struct netxen_adapter *adapter)
240 261
241 change = 0; 262 change = 0;
242 263
243 shift = netxen_nic_reg_read(adapter, CRB_DMA_SHIFT); 264 shift = NXRD32(adapter, CRB_DMA_SHIFT);
244 if (shift >= 32) 265 if (shift >= 32)
245 return 0; 266 return 0;
246 267
@@ -268,10 +289,22 @@ static void netxen_check_options(struct netxen_adapter *adapter)
268 else if (adapter->ahw.port_type == NETXEN_NIC_GBE) 289 else if (adapter->ahw.port_type == NETXEN_NIC_GBE)
269 adapter->num_rxd = MAX_RCV_DESCRIPTORS_1G; 290 adapter->num_rxd = MAX_RCV_DESCRIPTORS_1G;
270 291
271 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 292 adapter->msix_supported = 0;
293 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
272 adapter->msix_supported = !!use_msi_x; 294 adapter->msix_supported = !!use_msi_x;
273 else 295 adapter->rss_supported = !!use_msi_x;
274 adapter->msix_supported = 0; 296 } else if (adapter->fw_version >= NETXEN_VERSION_CODE(3, 4, 336)) {
297 switch (adapter->ahw.board_type) {
298 case NETXEN_BRDTYPE_P2_SB31_10G:
299 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
300 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
301 adapter->msix_supported = !!use_msi_x;
302 adapter->rss_supported = !!use_msi_x;
303 break;
304 default:
305 break;
306 }
307 }
275 308
276 adapter->num_txd = MAX_CMD_DESCRIPTORS_HOST; 309 adapter->num_txd = MAX_CMD_DESCRIPTORS_HOST;
277 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS; 310 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS;
@@ -287,43 +320,34 @@ netxen_check_hw_init(struct netxen_adapter *adapter, int first_boot)
287 320
288 if (first_boot == 0x55555555) { 321 if (first_boot == 0x55555555) {
289 /* This is the first boot after power up */ 322 /* This is the first boot after power up */
290 adapter->pci_write_normalize(adapter, 323 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
291 NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
292 324
293 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) 325 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
294 return 0; 326 return 0;
295 327
296 /* PCI bus master workaround */ 328 /* PCI bus master workaround */
297 adapter->hw_read_wx(adapter, 329 first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4));
298 NETXEN_PCIE_REG(0x4), &first_boot, 4);
299 if (!(first_boot & 0x4)) { 330 if (!(first_boot & 0x4)) {
300 first_boot |= 0x4; 331 first_boot |= 0x4;
301 adapter->hw_write_wx(adapter, 332 NXWR32(adapter, NETXEN_PCIE_REG(0x4), first_boot);
302 NETXEN_PCIE_REG(0x4), &first_boot, 4); 333 first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4));
303 adapter->hw_read_wx(adapter,
304 NETXEN_PCIE_REG(0x4), &first_boot, 4);
305 } 334 }
306 335
307 /* This is the first boot after power up */ 336 /* This is the first boot after power up */
308 adapter->hw_read_wx(adapter, 337 first_boot = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
309 NETXEN_ROMUSB_GLB_SW_RESET, &first_boot, 4);
310 if (first_boot != 0x80000f) { 338 if (first_boot != 0x80000f) {
311 /* clear the register for future unloads/loads */ 339 /* clear the register for future unloads/loads */
312 adapter->pci_write_normalize(adapter, 340 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), 0);
313 NETXEN_CAM_RAM(0x1fc), 0);
314 return -EIO; 341 return -EIO;
315 } 342 }
316 343
317 /* Start P2 boot loader */ 344 /* Start P2 boot loader */
318 val = adapter->pci_read_normalize(adapter, 345 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
319 NETXEN_ROMUSB_GLB_PEGTUNE_DONE); 346 NXWR32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1);
320 adapter->pci_write_normalize(adapter,
321 NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1);
322 timeout = 0; 347 timeout = 0;
323 do { 348 do {
324 msleep(1); 349 msleep(1);
325 val = adapter->pci_read_normalize(adapter, 350 val = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc));
326 NETXEN_CAM_RAM(0x1fc));
327 351
328 if (++timeout > 5000) 352 if (++timeout > 5000)
329 return -EIO; 353 return -EIO;
@@ -342,24 +366,19 @@ static void netxen_set_port_mode(struct netxen_adapter *adapter)
342 (val == NETXEN_BRDTYPE_P3_XG_LOM)) { 366 (val == NETXEN_BRDTYPE_P3_XG_LOM)) {
343 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 367 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
344 data = NETXEN_PORT_MODE_802_3_AP; 368 data = NETXEN_PORT_MODE_802_3_AP;
345 adapter->hw_write_wx(adapter, 369 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
346 NETXEN_PORT_MODE_ADDR, &data, 4);
347 } else if (port_mode == NETXEN_PORT_MODE_XG) { 370 } else if (port_mode == NETXEN_PORT_MODE_XG) {
348 data = NETXEN_PORT_MODE_XG; 371 data = NETXEN_PORT_MODE_XG;
349 adapter->hw_write_wx(adapter, 372 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
350 NETXEN_PORT_MODE_ADDR, &data, 4);
351 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_1G) { 373 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_1G) {
352 data = NETXEN_PORT_MODE_AUTO_NEG_1G; 374 data = NETXEN_PORT_MODE_AUTO_NEG_1G;
353 adapter->hw_write_wx(adapter, 375 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
354 NETXEN_PORT_MODE_ADDR, &data, 4);
355 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_XG) { 376 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_XG) {
356 data = NETXEN_PORT_MODE_AUTO_NEG_XG; 377 data = NETXEN_PORT_MODE_AUTO_NEG_XG;
357 adapter->hw_write_wx(adapter, 378 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
358 NETXEN_PORT_MODE_ADDR, &data, 4);
359 } else { 379 } else {
360 data = NETXEN_PORT_MODE_AUTO_NEG; 380 data = NETXEN_PORT_MODE_AUTO_NEG;
361 adapter->hw_write_wx(adapter, 381 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
362 NETXEN_PORT_MODE_ADDR, &data, 4);
363 } 382 }
364 383
365 if ((wol_port_mode != NETXEN_PORT_MODE_802_3_AP) && 384 if ((wol_port_mode != NETXEN_PORT_MODE_802_3_AP) &&
@@ -368,8 +387,7 @@ static void netxen_set_port_mode(struct netxen_adapter *adapter)
368 (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_XG)) { 387 (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_XG)) {
369 wol_port_mode = NETXEN_PORT_MODE_AUTO_NEG; 388 wol_port_mode = NETXEN_PORT_MODE_AUTO_NEG;
370 } 389 }
371 adapter->hw_write_wx(adapter, NETXEN_WOL_PORT_MODE, 390 NXWR32(adapter, NETXEN_WOL_PORT_MODE, wol_port_mode);
372 &wol_port_mode, 4);
373 } 391 }
374} 392}
375 393
@@ -462,8 +480,6 @@ netxen_setup_intr(struct netxen_adapter *adapter)
462 struct pci_dev *pdev = adapter->pdev; 480 struct pci_dev *pdev = adapter->pdev;
463 481
464 adapter->flags &= ~(NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED); 482 adapter->flags &= ~(NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED);
465 adapter->intr_scheme = -1;
466 adapter->msi_mode = -1;
467 483
468 if (adapter->ahw.revision_id >= NX_P3_B0) 484 if (adapter->ahw.revision_id >= NX_P3_B0)
469 legacy_intrp = &legacy_intr[adapter->ahw.pci_func]; 485 legacy_intrp = &legacy_intr[adapter->ahw.pci_func];
@@ -552,8 +568,6 @@ netxen_setup_pci_map(struct netxen_adapter *adapter)
552 adapter->hw_read_wx = netxen_nic_hw_read_wx_128M; 568 adapter->hw_read_wx = netxen_nic_hw_read_wx_128M;
553 adapter->pci_read_immediate = netxen_nic_pci_read_immediate_128M; 569 adapter->pci_read_immediate = netxen_nic_pci_read_immediate_128M;
554 adapter->pci_write_immediate = netxen_nic_pci_write_immediate_128M; 570 adapter->pci_write_immediate = netxen_nic_pci_write_immediate_128M;
555 adapter->pci_read_normalize = netxen_nic_pci_read_normalize_128M;
556 adapter->pci_write_normalize = netxen_nic_pci_write_normalize_128M;
557 adapter->pci_set_window = netxen_nic_pci_set_window_128M; 571 adapter->pci_set_window = netxen_nic_pci_set_window_128M;
558 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M; 572 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M;
559 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M; 573 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M;
@@ -575,9 +589,6 @@ netxen_setup_pci_map(struct netxen_adapter *adapter)
575 adapter->pci_read_immediate = netxen_nic_pci_read_immediate_2M; 589 adapter->pci_read_immediate = netxen_nic_pci_read_immediate_2M;
576 adapter->pci_write_immediate = 590 adapter->pci_write_immediate =
577 netxen_nic_pci_write_immediate_2M; 591 netxen_nic_pci_write_immediate_2M;
578 adapter->pci_read_normalize = netxen_nic_pci_read_normalize_2M;
579 adapter->pci_write_normalize =
580 netxen_nic_pci_write_normalize_2M;
581 adapter->pci_set_window = netxen_nic_pci_set_window_2M; 592 adapter->pci_set_window = netxen_nic_pci_set_window_2M;
582 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M; 593 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M;
583 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M; 594 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M;
@@ -660,8 +671,7 @@ netxen_start_firmware(struct netxen_adapter *adapter)
660 if (!first_driver) 671 if (!first_driver)
661 return 0; 672 return 0;
662 673
663 first_boot = adapter->pci_read_normalize(adapter, 674 first_boot = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc));
664 NETXEN_CAM_RAM(0x1fc));
665 675
666 err = netxen_check_hw_init(adapter, first_boot); 676 err = netxen_check_hw_init(adapter, first_boot);
667 if (err) { 677 if (err) {
@@ -670,13 +680,12 @@ netxen_start_firmware(struct netxen_adapter *adapter)
670 } 680 }
671 681
672 if (first_boot != 0x55555555) { 682 if (first_boot != 0x55555555) {
673 adapter->pci_write_normalize(adapter, 683 NXWR32(adapter, CRB_CMDPEG_STATE, 0);
674 CRB_CMDPEG_STATE, 0);
675 netxen_pinit_from_rom(adapter, 0); 684 netxen_pinit_from_rom(adapter, 0);
676 msleep(1); 685 msleep(1);
677 } 686 }
678 687
679 netxen_nic_reg_write(adapter, CRB_DMA_SHIFT, 0x55555555); 688 NXWR32(adapter, CRB_DMA_SHIFT, 0x55555555);
680 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 689 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
681 netxen_set_port_mode(adapter); 690 netxen_set_port_mode(adapter);
682 691
@@ -688,8 +697,7 @@ netxen_start_firmware(struct netxen_adapter *adapter)
688 val = 0x7654; 697 val = 0x7654;
689 if (adapter->ahw.port_type == NETXEN_NIC_XGBE) 698 if (adapter->ahw.port_type == NETXEN_NIC_XGBE)
690 val |= 0x0f000000; 699 val |= 0x0f000000;
691 netxen_crb_writelit_adapter(adapter, 700 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
692 NETXEN_MAC_ADDR_CNTL_REG, val);
693 701
694 } 702 }
695 703
@@ -703,7 +711,7 @@ netxen_start_firmware(struct netxen_adapter *adapter)
703 val = (_NETXEN_NIC_LINUX_MAJOR << 16) 711 val = (_NETXEN_NIC_LINUX_MAJOR << 16)
704 | ((_NETXEN_NIC_LINUX_MINOR << 8)) 712 | ((_NETXEN_NIC_LINUX_MINOR << 8))
705 | (_NETXEN_NIC_LINUX_SUBVERSION); 713 | (_NETXEN_NIC_LINUX_SUBVERSION);
706 adapter->pci_write_normalize(adapter, CRB_DRIVER_VERSION, val); 714 NXWR32(adapter, CRB_DRIVER_VERSION, val);
707 715
708 /* Handshake with the card before we register the devices. */ 716 /* Handshake with the card before we register the devices. */
709 err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE); 717 err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
@@ -726,15 +734,6 @@ netxen_nic_request_irq(struct netxen_adapter *adapter)
726 struct net_device *netdev = adapter->netdev; 734 struct net_device *netdev = adapter->netdev;
727 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; 735 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
728 736
729 if ((adapter->msi_mode != MSI_MODE_MULTIFUNC) ||
730 (adapter->intr_scheme != INTR_SCHEME_PERPORT)) {
731 printk(KERN_ERR "%s: Firmware interrupt scheme is "
732 "incompatible with driver\n",
733 netdev->name);
734 adapter->driver_mismatch = 1;
735 return -EINVAL;
736 }
737
738 if (adapter->flags & NETXEN_NIC_MSIX_ENABLED) 737 if (adapter->flags & NETXEN_NIC_MSIX_ENABLED)
739 handler = netxen_msix_intr; 738 handler = netxen_msix_intr;
740 else if (adapter->flags & NETXEN_NIC_MSI_ENABLED) 739 else if (adapter->flags & NETXEN_NIC_MSI_ENABLED)
@@ -798,6 +797,9 @@ netxen_nic_up(struct netxen_adapter *adapter, struct net_device *netdev)
798 if (adapter->max_sds_rings > 1) 797 if (adapter->max_sds_rings > 1)
799 netxen_config_rss(adapter, 1); 798 netxen_config_rss(adapter, 1);
800 799
800 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
801 netxen_linkevent_request(adapter, 1);
802
801 return 0; 803 return 0;
802} 804}
803 805
@@ -825,6 +827,7 @@ netxen_nic_attach(struct netxen_adapter *adapter)
825 struct pci_dev *pdev = adapter->pdev; 827 struct pci_dev *pdev = adapter->pdev;
826 int err, ring; 828 int err, ring;
827 struct nx_host_rds_ring *rds_ring; 829 struct nx_host_rds_ring *rds_ring;
830 struct nx_host_tx_ring *tx_ring;
828 831
829 err = netxen_init_firmware(adapter); 832 err = netxen_init_firmware(adapter);
830 if (err != 0) { 833 if (err != 0) {
@@ -854,13 +857,12 @@ netxen_nic_attach(struct netxen_adapter *adapter)
854 } 857 }
855 858
856 if (adapter->fw_major < 4) { 859 if (adapter->fw_major < 4) {
857 adapter->crb_addr_cmd_producer = 860 tx_ring = &adapter->tx_ring;
858 crb_cmd_producer[adapter->portnum]; 861 tx_ring->crb_cmd_producer = crb_cmd_producer[adapter->portnum];
859 adapter->crb_addr_cmd_consumer = 862 tx_ring->crb_cmd_consumer = crb_cmd_consumer[adapter->portnum];
860 crb_cmd_consumer[adapter->portnum];
861 863
862 netxen_nic_update_cmd_producer(adapter, 0); 864 netxen_nic_update_cmd_producer(adapter, tx_ring, 0);
863 netxen_nic_update_cmd_consumer(adapter, 0); 865 netxen_nic_update_cmd_consumer(adapter, tx_ring, 0);
864 } 866 }
865 867
866 for (ring = 0; ring < adapter->max_rds_rings; ring++) { 868 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
@@ -979,6 +981,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
979 SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops); 981 SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops);
980 982
981 netdev->features |= (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO); 983 netdev->features |= (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO);
984 netdev->features |= (NETIF_F_GRO);
982 netdev->vlan_features |= (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO); 985 netdev->vlan_features |= (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO);
983 986
984 if (NX_IS_REVISION_P3(revision_id)) { 987 if (NX_IS_REVISION_P3(revision_id)) {
@@ -1024,8 +1027,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1024 */ 1027 */
1025 adapter->physical_port = adapter->portnum; 1028 adapter->physical_port = adapter->portnum;
1026 if (adapter->fw_major < 4) { 1029 if (adapter->fw_major < 4) {
1027 i = adapter->pci_read_normalize(adapter, 1030 i = NXRD32(adapter, CRB_V2P(adapter->portnum));
1028 CRB_V2P(adapter->portnum));
1029 if (i != 0x55555555) 1031 if (i != 0x55555555)
1030 adapter->physical_port = i; 1032 adapter->physical_port = i;
1031 } 1033 }
@@ -1036,10 +1038,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1036 1038
1037 netdev->irq = adapter->msix_entries[0].vector; 1039 netdev->irq = adapter->msix_entries[0].vector;
1038 1040
1039 netxen_napi_add(adapter, netdev); 1041 if (netxen_napi_add(adapter, netdev))
1040
1041 err = netxen_receive_peg_ready(adapter);
1042 if (err)
1043 goto err_out_disable_msi; 1042 goto err_out_disable_msi;
1044 1043
1045 init_timer(&adapter->watchdog_timer); 1044 init_timer(&adapter->watchdog_timer);
@@ -1122,6 +1121,7 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev)
1122 netxen_free_adapter_offload(adapter); 1121 netxen_free_adapter_offload(adapter);
1123 1122
1124 netxen_teardown_intr(adapter); 1123 netxen_teardown_intr(adapter);
1124 netxen_free_sds_rings(&adapter->recv_ctx);
1125 1125
1126 netxen_cleanup_pci_map(adapter); 1126 netxen_cleanup_pci_map(adapter);
1127 1127
@@ -1315,7 +1315,7 @@ static int
1315netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1315netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1316{ 1316{
1317 struct netxen_adapter *adapter = netdev_priv(netdev); 1317 struct netxen_adapter *adapter = netdev_priv(netdev);
1318 struct netxen_hardware_context *hw = &adapter->ahw; 1318 struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
1319 unsigned int first_seg_len = skb->len - skb->data_len; 1319 unsigned int first_seg_len = skb->len - skb->data_len;
1320 struct netxen_cmd_buffer *pbuf; 1320 struct netxen_cmd_buffer *pbuf;
1321 struct netxen_skb_frag *buffrag; 1321 struct netxen_skb_frag *buffrag;
@@ -1326,28 +1326,26 @@ netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1326 1326
1327 u32 producer, consumer; 1327 u32 producer, consumer;
1328 int frag_count, no_of_desc; 1328 int frag_count, no_of_desc;
1329 u32 num_txd = adapter->num_txd; 1329 u32 num_txd = tx_ring->num_desc;
1330 bool is_tso = false; 1330 bool is_tso = false;
1331 1331
1332 frag_count = skb_shinfo(skb)->nr_frags + 1; 1332 frag_count = skb_shinfo(skb)->nr_frags + 1;
1333 1333
1334 /* There 4 fragments per descriptor */ 1334 /* 4 fragments per cmd des */
1335 no_of_desc = (frag_count + 3) >> 2; 1335 no_of_desc = (frag_count + 3) >> 2;
1336 1336
1337 producer = adapter->cmd_producer; 1337 producer = tx_ring->producer;
1338 smp_mb(); 1338 smp_mb();
1339 consumer = adapter->last_cmd_consumer; 1339 consumer = tx_ring->sw_consumer;
1340 if ((no_of_desc+2) > find_diff_among(producer, consumer, num_txd)) { 1340 if ((no_of_desc+2) > find_diff_among(producer, consumer, num_txd)) {
1341 netif_stop_queue(netdev); 1341 netif_stop_queue(netdev);
1342 smp_mb(); 1342 smp_mb();
1343 return NETDEV_TX_BUSY; 1343 return NETDEV_TX_BUSY;
1344 } 1344 }
1345 1345
1346 /* Copy the descriptors into the hardware */ 1346 hwdesc = &tx_ring->desc_head[producer];
1347 hwdesc = &hw->cmd_desc_head[producer];
1348 netxen_clear_cmddesc((u64 *)hwdesc); 1347 netxen_clear_cmddesc((u64 *)hwdesc);
1349 /* Take skb->data itself */ 1348 pbuf = &tx_ring->cmd_buf_arr[producer];
1350 pbuf = &adapter->cmd_buf_arr[producer];
1351 1349
1352 is_tso = netxen_tso_check(netdev, hwdesc, skb); 1350 is_tso = netxen_tso_check(netdev, hwdesc, skb);
1353 1351
@@ -1376,9 +1374,9 @@ netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1376 if ((i & 0x3) == 0) { 1374 if ((i & 0x3) == 0) {
1377 k = 0; 1375 k = 0;
1378 producer = get_next_index(producer, num_txd); 1376 producer = get_next_index(producer, num_txd);
1379 hwdesc = &hw->cmd_desc_head[producer]; 1377 hwdesc = &tx_ring->desc_head[producer];
1380 netxen_clear_cmddesc((u64 *)hwdesc); 1378 netxen_clear_cmddesc((u64 *)hwdesc);
1381 pbuf = &adapter->cmd_buf_arr[producer]; 1379 pbuf = &tx_ring->cmd_buf_arr[producer];
1382 pbuf->skb = NULL; 1380 pbuf->skb = NULL;
1383 } 1381 }
1384 frag = &skb_shinfo(skb)->frags[i - 1]; 1382 frag = &skb_shinfo(skb)->frags[i - 1];
@@ -1430,8 +1428,8 @@ netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1430 more_hdr = 0; 1428 more_hdr = 0;
1431 } 1429 }
1432 /* copy the MAC/IP/TCP headers to the cmd descriptor list */ 1430 /* copy the MAC/IP/TCP headers to the cmd descriptor list */
1433 hwdesc = &hw->cmd_desc_head[producer]; 1431 hwdesc = &tx_ring->desc_head[producer];
1434 pbuf = &adapter->cmd_buf_arr[producer]; 1432 pbuf = &tx_ring->cmd_buf_arr[producer];
1435 pbuf->skb = NULL; 1433 pbuf->skb = NULL;
1436 1434
1437 /* copy the first 64 bytes */ 1435 /* copy the first 64 bytes */
@@ -1440,8 +1438,8 @@ netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1440 producer = get_next_index(producer, num_txd); 1438 producer = get_next_index(producer, num_txd);
1441 1439
1442 if (more_hdr) { 1440 if (more_hdr) {
1443 hwdesc = &hw->cmd_desc_head[producer]; 1441 hwdesc = &tx_ring->desc_head[producer];
1444 pbuf = &adapter->cmd_buf_arr[producer]; 1442 pbuf = &tx_ring->cmd_buf_arr[producer];
1445 pbuf->skb = NULL; 1443 pbuf->skb = NULL;
1446 /* copy the next 64 bytes - should be enough except 1444 /* copy the next 64 bytes - should be enough except
1447 * for pathological case 1445 * for pathological case
@@ -1454,10 +1452,10 @@ netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1454 } 1452 }
1455 } 1453 }
1456 1454
1457 adapter->cmd_producer = producer; 1455 tx_ring->producer = producer;
1458 adapter->stats.txbytes += skb->len; 1456 adapter->stats.txbytes += skb->len;
1459 1457
1460 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer); 1458 netxen_nic_update_cmd_producer(adapter, tx_ring, producer);
1461 1459
1462 adapter->stats.xmitcalled++; 1460 adapter->stats.xmitcalled++;
1463 netdev->trans_start = jiffies; 1461 netdev->trans_start = jiffies;
@@ -1476,7 +1474,7 @@ static int netxen_nic_check_temp(struct netxen_adapter *adapter)
1476 uint32_t temp, temp_state, temp_val; 1474 uint32_t temp, temp_state, temp_val;
1477 int rv = 0; 1475 int rv = 0;
1478 1476
1479 temp = adapter->pci_read_normalize(adapter, CRB_TEMP_STATE); 1477 temp = NXRD32(adapter, CRB_TEMP_STATE);
1480 1478
1481 temp_state = nx_get_temp_state(temp); 1479 temp_state = nx_get_temp_state(temp);
1482 temp_val = nx_get_temp_val(temp); 1480 temp_val = nx_get_temp_val(temp);
@@ -1510,26 +1508,9 @@ static int netxen_nic_check_temp(struct netxen_adapter *adapter)
1510 return rv; 1508 return rv;
1511} 1509}
1512 1510
1513static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter) 1511void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup)
1514{ 1512{
1515 struct net_device *netdev = adapter->netdev; 1513 struct net_device *netdev = adapter->netdev;
1516 u32 val, port, linkup;
1517
1518 port = adapter->physical_port;
1519
1520 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1521 val = adapter->pci_read_normalize(adapter, CRB_XG_STATE_P3);
1522 val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val);
1523 linkup = (val == XG_LINK_UP_P3);
1524 } else {
1525 val = adapter->pci_read_normalize(adapter, CRB_XG_STATE);
1526 if (adapter->ahw.port_type == NETXEN_NIC_GBE)
1527 linkup = (val >> port) & 1;
1528 else {
1529 val = (val >> port*8) & 0xff;
1530 linkup = (val == XG_LINK_UP);
1531 }
1532 }
1533 1514
1534 if (adapter->ahw.linkup && !linkup) { 1515 if (adapter->ahw.linkup && !linkup) {
1535 printk(KERN_INFO "%s: %s NIC Link is down\n", 1516 printk(KERN_INFO "%s: %s NIC Link is down\n",
@@ -1540,7 +1521,9 @@ static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter)
1540 netif_stop_queue(netdev); 1521 netif_stop_queue(netdev);
1541 } 1522 }
1542 1523
1543 netxen_nic_set_link_parameters(adapter); 1524 if (!adapter->has_link_events)
1525 netxen_nic_set_link_parameters(adapter);
1526
1544 } else if (!adapter->ahw.linkup && linkup) { 1527 } else if (!adapter->ahw.linkup && linkup) {
1545 printk(KERN_INFO "%s: %s NIC Link is up\n", 1528 printk(KERN_INFO "%s: %s NIC Link is up\n",
1546 netxen_nic_driver_name, netdev->name); 1529 netxen_nic_driver_name, netdev->name);
@@ -1550,10 +1533,34 @@ static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter)
1550 netif_wake_queue(netdev); 1533 netif_wake_queue(netdev);
1551 } 1534 }
1552 1535
1553 netxen_nic_set_link_parameters(adapter); 1536 if (!adapter->has_link_events)
1537 netxen_nic_set_link_parameters(adapter);
1554 } 1538 }
1555} 1539}
1556 1540
1541static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter)
1542{
1543 u32 val, port, linkup;
1544
1545 port = adapter->physical_port;
1546
1547 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1548 val = NXRD32(adapter, CRB_XG_STATE_P3);
1549 val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val);
1550 linkup = (val == XG_LINK_UP_P3);
1551 } else {
1552 val = NXRD32(adapter, CRB_XG_STATE);
1553 if (adapter->ahw.port_type == NETXEN_NIC_GBE)
1554 linkup = (val >> port) & 1;
1555 else {
1556 val = (val >> port*8) & 0xff;
1557 linkup = (val == XG_LINK_UP);
1558 }
1559 }
1560
1561 netxen_advert_link_change(adapter, linkup);
1562}
1563
1557static void netxen_watchdog(unsigned long v) 1564static void netxen_watchdog(unsigned long v)
1558{ 1565{
1559 struct netxen_adapter *adapter = (struct netxen_adapter *)v; 1566 struct netxen_adapter *adapter = (struct netxen_adapter *)v;
@@ -1569,7 +1576,8 @@ void netxen_watchdog_task(struct work_struct *work)
1569 if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter)) 1576 if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
1570 return; 1577 return;
1571 1578
1572 netxen_nic_handle_phy_intr(adapter); 1579 if (!adapter->has_link_events)
1580 netxen_nic_handle_phy_intr(adapter);
1573 1581
1574 if (netif_running(adapter->netdev)) 1582 if (netif_running(adapter->netdev))
1575 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); 1583 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
@@ -1598,10 +1606,6 @@ static void netxen_tx_timeout_task(struct work_struct *work)
1598 netif_wake_queue(adapter->netdev); 1606 netif_wake_queue(adapter->netdev);
1599} 1607}
1600 1608
1601/*
1602 * netxen_nic_get_stats - Get System Network Statistics
1603 * @netdev: network interface device structure
1604 */
1605struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev) 1609struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
1606{ 1610{
1607 struct netxen_adapter *adapter = netdev_priv(netdev); 1611 struct netxen_adapter *adapter = netdev_priv(netdev);
@@ -1609,22 +1613,11 @@ struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev)
1609 1613
1610 memset(stats, 0, sizeof(*stats)); 1614 memset(stats, 0, sizeof(*stats));
1611 1615
1612 /* total packets received */
1613 stats->rx_packets = adapter->stats.no_rcv; 1616 stats->rx_packets = adapter->stats.no_rcv;
1614 /* total packets transmitted */ 1617 stats->tx_packets = adapter->stats.xmitfinished;
1615 stats->tx_packets = adapter->stats.xmitedframes +
1616 adapter->stats.xmitfinished;
1617 /* total bytes received */
1618 stats->rx_bytes = adapter->stats.rxbytes; 1618 stats->rx_bytes = adapter->stats.rxbytes;
1619 /* total bytes transmitted */
1620 stats->tx_bytes = adapter->stats.txbytes; 1619 stats->tx_bytes = adapter->stats.txbytes;
1621 /* bad packets received */
1622 stats->rx_errors = adapter->stats.rcvdbadskb;
1623 /* packet transmit problems */
1624 stats->tx_errors = adapter->stats.nocmddescriptor;
1625 /* no space in linux buffers */
1626 stats->rx_dropped = adapter->stats.rxdropped; 1620 stats->rx_dropped = adapter->stats.rxdropped;
1627 /* no space available in linux */
1628 stats->tx_dropped = adapter->stats.txdropped; 1621 stats->tx_dropped = adapter->stats.txdropped;
1629 1622
1630 return stats; 1623 return stats;
@@ -1651,15 +1644,14 @@ static irqreturn_t netxen_intr(int irq, void *data)
1651 } else { 1644 } else {
1652 unsigned long our_int = 0; 1645 unsigned long our_int = 0;
1653 1646
1654 our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR); 1647 our_int = NXRD32(adapter, CRB_INT_VECTOR);
1655 1648
1656 /* not our interrupt */ 1649 /* not our interrupt */
1657 if (!test_and_clear_bit((7 + adapter->portnum), &our_int)) 1650 if (!test_and_clear_bit((7 + adapter->portnum), &our_int))
1658 return IRQ_NONE; 1651 return IRQ_NONE;
1659 1652
1660 /* claim interrupt */ 1653 /* claim interrupt */
1661 adapter->pci_write_normalize(adapter, 1654 NXWR32(adapter, CRB_INT_VECTOR, (our_int & 0xffffffff));
1662 CRB_INT_VECTOR, (our_int & 0xffffffff));
1663 } 1655 }
1664 1656
1665 /* clear interrupt */ 1657 /* clear interrupt */
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c
index d85203203d4d..5e2698bf575a 100644
--- a/drivers/net/netxen/netxen_nic_niu.c
+++ b/drivers/net/netxen/netxen_nic_niu.c
@@ -43,8 +43,7 @@ static int phy_lock(struct netxen_adapter *adapter)
43 int done = 0, timeout = 0; 43 int done = 0, timeout = 0;
44 44
45 while (!done) { 45 while (!done) {
46 done = netxen_nic_reg_read(adapter, 46 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
47 NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
48 if (done == 1) 47 if (done == 1)
49 break; 48 break;
50 if (timeout >= phy_lock_timeout) { 49 if (timeout >= phy_lock_timeout) {
@@ -59,8 +58,7 @@ static int phy_lock(struct netxen_adapter *adapter)
59 } 58 }
60 } 59 }
61 60
62 netxen_crb_writelit_adapter(adapter, 61 NXWR32(adapter, NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
63 NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
64 return 0; 62 return 0;
65} 63}
66 64
@@ -105,9 +103,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
105 * so it cannot be in reset 103 * so it cannot be in reset
106 */ 104 */
107 105
108 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), 106 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
109 &mac_cfg0, 4))
110 return -EIO;
111 if (netxen_gb_get_soft_reset(mac_cfg0)) { 107 if (netxen_gb_get_soft_reset(mac_cfg0)) {
112 __u32 temp; 108 __u32 temp;
113 temp = 0; 109 temp = 0;
@@ -115,9 +111,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
115 netxen_gb_rx_reset_pb(temp); 111 netxen_gb_rx_reset_pb(temp);
116 netxen_gb_tx_reset_mac(temp); 112 netxen_gb_tx_reset_mac(temp);
117 netxen_gb_rx_reset_mac(temp); 113 netxen_gb_rx_reset_mac(temp);
118 if (adapter->hw_write_wx(adapter, 114 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
119 NETXEN_NIU_GB_MAC_CONFIG_0(0),
120 &temp, 4))
121 return -EIO; 115 return -EIO;
122 restore = 1; 116 restore = 1;
123 } 117 }
@@ -125,43 +119,32 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
125 address = 0; 119 address = 0;
126 netxen_gb_mii_mgmt_reg_addr(address, reg); 120 netxen_gb_mii_mgmt_reg_addr(address, reg);
127 netxen_gb_mii_mgmt_phy_addr(address, phy); 121 netxen_gb_mii_mgmt_phy_addr(address, phy);
128 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), 122 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
129 &address, 4))
130 return -EIO; 123 return -EIO;
131 command = 0; /* turn off any prior activity */ 124 command = 0; /* turn off any prior activity */
132 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), 125 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
133 &command, 4))
134 return -EIO; 126 return -EIO;
135 /* send read command */ 127 /* send read command */
136 netxen_gb_mii_mgmt_set_read_cycle(command); 128 netxen_gb_mii_mgmt_set_read_cycle(command);
137 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), 129 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
138 &command, 4))
139 return -EIO; 130 return -EIO;
140 131
141 status = 0; 132 status = 0;
142 do { 133 do {
143 if (adapter->hw_read_wx(adapter, 134 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
144 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
145 &status, 4))
146 return -EIO;
147 timeout++; 135 timeout++;
148 } while ((netxen_get_gb_mii_mgmt_busy(status) 136 } while ((netxen_get_gb_mii_mgmt_busy(status)
149 || netxen_get_gb_mii_mgmt_notvalid(status)) 137 || netxen_get_gb_mii_mgmt_notvalid(status))
150 && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); 138 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
151 139
152 if (timeout < NETXEN_NIU_PHY_WAITMAX) { 140 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
153 if (adapter->hw_read_wx(adapter, 141 *readval = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_STATUS(0));
154 NETXEN_NIU_GB_MII_MGMT_STATUS(0),
155 readval, 4))
156 return -EIO;
157 result = 0; 142 result = 0;
158 } else 143 } else
159 result = -1; 144 result = -1;
160 145
161 if (restore) 146 if (restore)
162 if (adapter->hw_write_wx(adapter, 147 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
163 NETXEN_NIU_GB_MAC_CONFIG_0(0),
164 &mac_cfg0, 4))
165 return -EIO; 148 return -EIO;
166 phy_unlock(adapter); 149 phy_unlock(adapter);
167 return result; 150 return result;
@@ -197,9 +180,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
197 * cannot be in reset 180 * cannot be in reset
198 */ 181 */
199 182
200 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), 183 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
201 &mac_cfg0, 4))
202 return -EIO;
203 if (netxen_gb_get_soft_reset(mac_cfg0)) { 184 if (netxen_gb_get_soft_reset(mac_cfg0)) {
204 __u32 temp; 185 __u32 temp;
205 temp = 0; 186 temp = 0;
@@ -208,35 +189,27 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
208 netxen_gb_tx_reset_mac(temp); 189 netxen_gb_tx_reset_mac(temp);
209 netxen_gb_rx_reset_mac(temp); 190 netxen_gb_rx_reset_mac(temp);
210 191
211 if (adapter->hw_write_wx(adapter, 192 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
212 NETXEN_NIU_GB_MAC_CONFIG_0(0),
213 &temp, 4))
214 return -EIO; 193 return -EIO;
215 restore = 1; 194 restore = 1;
216 } 195 }
217 196
218 command = 0; /* turn off any prior activity */ 197 command = 0; /* turn off any prior activity */
219 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), 198 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
220 &command, 4))
221 return -EIO; 199 return -EIO;
222 200
223 address = 0; 201 address = 0;
224 netxen_gb_mii_mgmt_reg_addr(address, reg); 202 netxen_gb_mii_mgmt_reg_addr(address, reg);
225 netxen_gb_mii_mgmt_phy_addr(address, phy); 203 netxen_gb_mii_mgmt_phy_addr(address, phy);
226 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), 204 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
227 &address, 4))
228 return -EIO; 205 return -EIO;
229 206
230 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), 207 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
231 &val, 4))
232 return -EIO; 208 return -EIO;
233 209
234 status = 0; 210 status = 0;
235 do { 211 do {
236 if (adapter->hw_read_wx(adapter, 212 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
237 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
238 &status, 4))
239 return -EIO;
240 timeout++; 213 timeout++;
241 } while ((netxen_get_gb_mii_mgmt_busy(status)) 214 } while ((netxen_get_gb_mii_mgmt_busy(status))
242 && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); 215 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
@@ -248,9 +221,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
248 221
249 /* restore the state of port 0 MAC in case we tampered with it */ 222 /* restore the state of port 0 MAC in case we tampered with it */
250 if (restore) 223 if (restore)
251 if (adapter->hw_write_wx(adapter, 224 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
252 NETXEN_NIU_GB_MAC_CONFIG_0(0),
253 &mac_cfg0, 4))
254 return -EIO; 225 return -EIO;
255 226
256 return result; 227 return result;
@@ -258,7 +229,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
258 229
259int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter) 230int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
260{ 231{
261 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f); 232 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x3f);
262 return 0; 233 return 0;
263} 234}
264 235
@@ -281,7 +252,7 @@ int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
281 252
282int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter) 253int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
283{ 254{
284 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f); 255 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x7f);
285 return 0; 256 return 0;
286} 257}
287 258
@@ -315,36 +286,27 @@ static int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
315static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, 286static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
316 int port, long enable) 287 int port, long enable)
317{ 288{
318 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2); 289 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
319 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 290 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
320 0x80000000); 291 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
321 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 292 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf1ff);
322 0x0000f0025); 293 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
323 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 294 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
324 0xf1ff); 295 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
325 netxen_crb_writelit_adapter(adapter, 296 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
326 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
327 netxen_crb_writelit_adapter(adapter,
328 NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
329 netxen_crb_writelit_adapter(adapter,
330 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
331 netxen_crb_writelit_adapter(adapter,
332 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
333 297
334 if (enable) { 298 if (enable) {
335 /* 299 /*
336 * Do NOT enable flow control until a suitable solution for 300 * Do NOT enable flow control until a suitable solution for
337 * shutting down pause frames is found. 301 * shutting down pause frames is found.
338 */ 302 */
339 netxen_crb_writelit_adapter(adapter, 303 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
340 NETXEN_NIU_GB_MAC_CONFIG_0(port),
341 0x5);
342 } 304 }
343 305
344 if (netxen_niu_gbe_enable_phy_interrupts(adapter)) 306 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
345 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n"); 307 printk(KERN_ERR "ERROR enabling PHY interrupts\n");
346 if (netxen_niu_gbe_clear_phy_interrupts(adapter)) 308 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
347 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n"); 309 printk(KERN_ERR "ERROR clearing PHY interrupts\n");
348} 310}
349 311
350/* 312/*
@@ -353,36 +315,27 @@ static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
353static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, 315static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
354 int port, long enable) 316 int port, long enable)
355{ 317{
356 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2); 318 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
357 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 319 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
358 0x80000000); 320 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
359 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 321 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf2ff);
360 0x0000f0025); 322 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
361 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 323 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
362 0xf2ff); 324 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
363 netxen_crb_writelit_adapter(adapter, 325 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
364 NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
365 netxen_crb_writelit_adapter(adapter,
366 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
367 netxen_crb_writelit_adapter(adapter,
368 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
369 netxen_crb_writelit_adapter(adapter,
370 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
371 326
372 if (enable) { 327 if (enable) {
373 /* 328 /*
374 * Do NOT enable flow control until a suitable solution for 329 * Do NOT enable flow control until a suitable solution for
375 * shutting down pause frames is found. 330 * shutting down pause frames is found.
376 */ 331 */
377 netxen_crb_writelit_adapter(adapter, 332 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
378 NETXEN_NIU_GB_MAC_CONFIG_0(port),
379 0x5);
380 } 333 }
381 334
382 if (netxen_niu_gbe_enable_phy_interrupts(adapter)) 335 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
383 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n"); 336 printk(KERN_ERR "ERROR enabling PHY interrupts\n");
384 if (netxen_niu_gbe_clear_phy_interrupts(adapter)) 337 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
385 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n"); 338 printk(KERN_ERR "ERROR clearing PHY interrupts\n");
386} 339}
387 340
388int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port) 341int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
@@ -416,25 +369,20 @@ int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
416 * plugged in. 369 * plugged in.
417 */ 370 */
418 371
419 netxen_crb_writelit_adapter(adapter, 372 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
420 NETXEN_NIU_GB_MAC_CONFIG_0
421 (port),
422 NETXEN_GB_MAC_SOFT_RESET); 373 NETXEN_GB_MAC_SOFT_RESET);
423 netxen_crb_writelit_adapter(adapter, 374 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
424 NETXEN_NIU_GB_MAC_CONFIG_0 375 NETXEN_GB_MAC_RESET_PROT_BLK |
425 (port), 376 NETXEN_GB_MAC_ENABLE_TX_RX |
426 NETXEN_GB_MAC_RESET_PROT_BLK 377 NETXEN_GB_MAC_PAUSED_FRMS);
427 | NETXEN_GB_MAC_ENABLE_TX_RX
428 |
429 NETXEN_GB_MAC_PAUSED_FRMS);
430 if (netxen_niu_gbe_clear_phy_interrupts(adapter)) 378 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
431 printk(KERN_ERR PFX 379 printk(KERN_ERR
432 "ERROR clearing PHY interrupts\n"); 380 "ERROR clearing PHY interrupts\n");
433 if (netxen_niu_gbe_enable_phy_interrupts(adapter)) 381 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
434 printk(KERN_ERR PFX 382 printk(KERN_ERR
435 "ERROR enabling PHY interrupts\n"); 383 "ERROR enabling PHY interrupts\n");
436 if (netxen_niu_gbe_clear_phy_interrupts(adapter)) 384 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
437 printk(KERN_ERR PFX 385 printk(KERN_ERR
438 "ERROR clearing PHY interrupts\n"); 386 "ERROR clearing PHY interrupts\n");
439 result = -1; 387 result = -1;
440 } 388 }
@@ -447,10 +395,8 @@ int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
447int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) 395int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
448{ 396{
449 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 397 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
450 netxen_crb_writelit_adapter(adapter, 398 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
451 NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); 399 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
452 netxen_crb_writelit_adapter(adapter,
453 NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
454 } 400 }
455 401
456 return 0; 402 return 0;
@@ -473,12 +419,8 @@ static int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
473 if ((phy < 0) || (phy > 3)) 419 if ((phy < 0) || (phy > 3))
474 return -EINVAL; 420 return -EINVAL;
475 421
476 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), 422 stationhigh = NXRD32(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy));
477 &stationhigh, 4)) 423 stationlow = NXRD32(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy));
478 return -EIO;
479 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
480 &stationlow, 4))
481 return -EIO;
482 ((__le32 *)val)[1] = cpu_to_le32(stationhigh); 424 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
483 ((__le32 *)val)[0] = cpu_to_le32(stationlow); 425 ((__le32 *)val)[0] = cpu_to_le32(stationlow);
484 426
@@ -507,14 +449,12 @@ int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
507 temp[0] = temp[1] = 0; 449 temp[0] = temp[1] = 0;
508 memcpy(temp + 2, addr, 2); 450 memcpy(temp + 2, addr, 2);
509 val = le32_to_cpu(*(__le32 *)temp); 451 val = le32_to_cpu(*(__le32 *)temp);
510 if (adapter->hw_write_wx(adapter, 452 if (NXWR32(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), val))
511 NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4))
512 return -EIO; 453 return -EIO;
513 454
514 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32)); 455 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
515 val = le32_to_cpu(*(__le32 *)temp); 456 val = le32_to_cpu(*(__le32 *)temp);
516 if (adapter->hw_write_wx(adapter, 457 if (NXWR32(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), val))
517 NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4))
518 return -2; 458 return -2;
519 459
520 netxen_niu_macaddr_get(adapter, 460 netxen_niu_macaddr_get(adapter,
@@ -545,8 +485,7 @@ int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
545 return -EINVAL; 485 return -EINVAL;
546 mac_cfg0 = 0; 486 mac_cfg0 = 0;
547 netxen_gb_soft_reset(mac_cfg0); 487 netxen_gb_soft_reset(mac_cfg0);
548 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 488 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), mac_cfg0))
549 &mac_cfg0, 4))
550 return -EIO; 489 return -EIO;
551 return 0; 490 return 0;
552} 491}
@@ -564,8 +503,8 @@ int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
564 return -EINVAL; 503 return -EINVAL;
565 504
566 mac_cfg = 0; 505 mac_cfg = 0;
567 if (adapter->hw_write_wx(adapter, 506 if (NXWR32(adapter,
568 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), &mac_cfg, 4)) 507 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
569 return -EIO; 508 return -EIO;
570 return 0; 509 return 0;
571} 510}
@@ -581,9 +520,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
581 return -EINVAL; 520 return -EINVAL;
582 521
583 /* save previous contents */ 522 /* save previous contents */
584 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, 523 reg = NXRD32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR);
585 &reg, 4))
586 return -EIO;
587 if (mode == NETXEN_NIU_PROMISC_MODE) { 524 if (mode == NETXEN_NIU_PROMISC_MODE) {
588 switch (port) { 525 switch (port) {
589 case 0: 526 case 0:
@@ -619,8 +556,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
619 return -EIO; 556 return -EIO;
620 } 557 }
621 } 558 }
622 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, 559 if (NXWR32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, reg))
623 &reg, 4))
624 return -EIO; 560 return -EIO;
625 return 0; 561 return 0;
626} 562}
@@ -647,28 +583,24 @@ int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
647 case 0: 583 case 0:
648 memcpy(temp + 2, addr, 2); 584 memcpy(temp + 2, addr, 2);
649 val = le32_to_cpu(*(__le32 *)temp); 585 val = le32_to_cpu(*(__le32 *)temp);
650 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, 586 if (NXWR32(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, val))
651 &val, 4))
652 return -EIO; 587 return -EIO;
653 588
654 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); 589 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
655 val = le32_to_cpu(*(__le32 *)temp); 590 val = le32_to_cpu(*(__le32 *)temp);
656 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, 591 if (NXWR32(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, val))
657 &val, 4))
658 return -EIO; 592 return -EIO;
659 break; 593 break;
660 594
661 case 1: 595 case 1:
662 memcpy(temp + 2, addr, 2); 596 memcpy(temp + 2, addr, 2);
663 val = le32_to_cpu(*(__le32 *)temp); 597 val = le32_to_cpu(*(__le32 *)temp);
664 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1, 598 if (NXWR32(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1, val))
665 &val, 4))
666 return -EIO; 599 return -EIO;
667 600
668 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); 601 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
669 val = le32_to_cpu(*(__le32 *)temp); 602 val = le32_to_cpu(*(__le32 *)temp);
670 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI, 603 if (NXWR32(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI, val))
671 &val, 4))
672 return -EIO; 604 return -EIO;
673 break; 605 break;
674 606
@@ -689,9 +621,7 @@ int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
689 if (port > NETXEN_NIU_MAX_XG_PORTS) 621 if (port > NETXEN_NIU_MAX_XG_PORTS)
690 return -EINVAL; 622 return -EINVAL;
691 623
692 if (adapter->hw_read_wx(adapter, 624 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
693 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), &reg, 4))
694 return -EIO;
695 if (mode == NETXEN_NIU_PROMISC_MODE) 625 if (mode == NETXEN_NIU_PROMISC_MODE)
696 reg = (reg | 0x2000UL); 626 reg = (reg | 0x2000UL);
697 else 627 else
@@ -702,8 +632,7 @@ int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
702 else 632 else
703 reg = (reg & ~0x1000UL); 633 reg = (reg & ~0x1000UL);
704 634
705 netxen_crb_writelit_adapter(adapter, 635 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
706 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
707 636
708 return 0; 637 return 0;
709} 638}
diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h
index 50183335e43a..845dcf436cf6 100644
--- a/drivers/net/netxen/netxen_nic_phan_reg.h
+++ b/drivers/net/netxen/netxen_nic_phan_reg.h
@@ -36,23 +36,25 @@
36 */ 36 */
37#define NIC_CRB_BASE NETXEN_CAM_RAM(0x200) 37#define NIC_CRB_BASE NETXEN_CAM_RAM(0x200)
38#define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X)) 38#define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X))
39#define NIC_CRB_BASE_2 NETXEN_CAM_RAM(0x700)
40#define NETXEN_NIC_REG_2(X) (NIC_CRB_BASE_2+(X))
39 41
40#define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00) 42#define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00)
41#define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04) 43#define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04)
42#define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08) 44#define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08)
43#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c) 45#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c)
44#define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10) /* C0 EPG BUG */ 46#define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10)
45#define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14) 47#define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14)
46#define NX_CDRP_CRB_OFFSET NETXEN_NIC_REG(0x18) 48#define NX_CDRP_CRB_OFFSET NETXEN_NIC_REG(0x18)
47#define NX_ARG1_CRB_OFFSET NETXEN_NIC_REG(0x1c) 49#define NX_ARG1_CRB_OFFSET NETXEN_NIC_REG(0x1c)
48#define NX_ARG2_CRB_OFFSET NETXEN_NIC_REG(0x20) 50#define NX_ARG2_CRB_OFFSET NETXEN_NIC_REG(0x20)
49#define NX_ARG3_CRB_OFFSET NETXEN_NIC_REG(0x24) 51#define NX_ARG3_CRB_OFFSET NETXEN_NIC_REG(0x24)
50#define NX_SIGN_CRB_OFFSET NETXEN_NIC_REG(0x28) 52#define NX_SIGN_CRB_OFFSET NETXEN_NIC_REG(0x28)
51#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x20) /* 4 regs for perf */ 53#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x20)
52#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x24) 54#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x24)
53#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x28) 55#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x28)
54#define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x2c) 56#define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x2c)
55#define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x30) /* phantom init status */ 57#define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x30)
56#define CRB_MMAP_ADDR_3 NETXEN_NIC_REG(0x34) 58#define CRB_MMAP_ADDR_3 NETXEN_NIC_REG(0x34)
57#define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x38) 59#define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x38)
58#define CRB_HOST_DUMMY_BUF_ADDR_HI NETXEN_NIC_REG(0x3c) 60#define CRB_HOST_DUMMY_BUF_ADDR_HI NETXEN_NIC_REG(0x3c)
@@ -65,7 +67,7 @@
65#define CRB_MMAP_SIZE_1 NETXEN_NIC_REG(0x58) 67#define CRB_MMAP_SIZE_1 NETXEN_NIC_REG(0x58)
66#define CRB_MMAP_SIZE_2 NETXEN_NIC_REG(0x5c) 68#define CRB_MMAP_SIZE_2 NETXEN_NIC_REG(0x5c)
67#define CRB_MMAP_SIZE_3 NETXEN_NIC_REG(0x60) 69#define CRB_MMAP_SIZE_3 NETXEN_NIC_REG(0x60)
68#define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x64) /* interrupt coalescing */ 70#define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x64)
69#define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x68) 71#define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x68)
70#define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x6c) 72#define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x6c)
71#define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x70) 73#define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x70)
@@ -83,13 +85,13 @@
83#define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xa0) 85#define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xa0)
84#define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xa4) 86#define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xa4)
85#define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xa8) 87#define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xa8)
86#define CRB_TX_STATE NETXEN_NIC_REG(0xac) /* Debug -performance */ 88#define CRB_TX_STATE NETXEN_NIC_REG(0xac)
87#define CRB_TX_COUNT NETXEN_NIC_REG(0xb0) 89#define CRB_TX_COUNT NETXEN_NIC_REG(0xb0)
88#define CRB_RX_STATE NETXEN_NIC_REG(0xb4) 90#define CRB_RX_STATE NETXEN_NIC_REG(0xb4)
89#define CRB_RX_PERF_DEBUG_1 NETXEN_NIC_REG(0xb8) 91#define CRB_RX_PERF_DEBUG_1 NETXEN_NIC_REG(0xb8)
90#define CRB_RX_LRO_CONTROL NETXEN_NIC_REG(0xbc) /* LRO On/OFF */ 92#define CRB_RX_LRO_CONTROL NETXEN_NIC_REG(0xbc)
91#define CRB_RX_LRO_START_NUM NETXEN_NIC_REG(0xc0) 93#define CRB_RX_LRO_START_NUM NETXEN_NIC_REG(0xc0)
92#define CRB_MPORT_MODE NETXEN_NIC_REG(0xc4) /* Multiport Mode */ 94#define CRB_MPORT_MODE NETXEN_NIC_REG(0xc4)
93#define CRB_CMD_RING_SIZE NETXEN_NIC_REG(0xc8) 95#define CRB_CMD_RING_SIZE NETXEN_NIC_REG(0xc8)
94#define CRB_DMA_SHIFT NETXEN_NIC_REG(0xcc) 96#define CRB_DMA_SHIFT NETXEN_NIC_REG(0xcc)
95#define CRB_INT_VECTOR NETXEN_NIC_REG(0xd4) 97#define CRB_INT_VECTOR NETXEN_NIC_REG(0xd4)
@@ -109,8 +111,6 @@
109#define CRB_CMD_CONSUMER_OFFSET_1 NETXEN_NIC_REG(0x1b0) 111#define CRB_CMD_CONSUMER_OFFSET_1 NETXEN_NIC_REG(0x1b0)
110#define CRB_CMD_PRODUCER_OFFSET_2 NETXEN_NIC_REG(0x1b8) 112#define CRB_CMD_PRODUCER_OFFSET_2 NETXEN_NIC_REG(0x1b8)
111#define CRB_CMD_CONSUMER_OFFSET_2 NETXEN_NIC_REG(0x1bc) 113#define CRB_CMD_CONSUMER_OFFSET_2 NETXEN_NIC_REG(0x1bc)
112
113// 1c0 to 1cc used for signature reg
114#define CRB_CMD_PRODUCER_OFFSET_3 NETXEN_NIC_REG(0x1d0) 114#define CRB_CMD_PRODUCER_OFFSET_3 NETXEN_NIC_REG(0x1d0)
115#define CRB_CMD_CONSUMER_OFFSET_3 NETXEN_NIC_REG(0x1d4) 115#define CRB_CMD_CONSUMER_OFFSET_3 NETXEN_NIC_REG(0x1d4)
116#define CRB_TEMP_STATE NETXEN_NIC_REG(0x1b4) 116#define CRB_TEMP_STATE NETXEN_NIC_REG(0x1b4)
@@ -120,8 +120,7 @@
120#define CRB_V2P_2 NETXEN_NIC_REG(0x298) 120#define CRB_V2P_2 NETXEN_NIC_REG(0x298)
121#define CRB_V2P_3 NETXEN_NIC_REG(0x29c) 121#define CRB_V2P_3 NETXEN_NIC_REG(0x29c)
122#define CRB_V2P(port) (CRB_V2P_0+((port)*4)) 122#define CRB_V2P(port) (CRB_V2P_0+((port)*4))
123#define CRB_DRIVER_VERSION NETXEN_NIC_REG(0x2a0) 123#define CRB_DRIVER_VERSION NETXEN_NIC_REG(0x2a0)
124/* sw int status/mask registers */
125#define CRB_SW_INT_MASK_0 NETXEN_NIC_REG(0x1d8) 124#define CRB_SW_INT_MASK_0 NETXEN_NIC_REG(0x1d8)
126#define CRB_SW_INT_MASK_1 NETXEN_NIC_REG(0x1e0) 125#define CRB_SW_INT_MASK_1 NETXEN_NIC_REG(0x1e0)
127#define CRB_SW_INT_MASK_2 NETXEN_NIC_REG(0x1e4) 126#define CRB_SW_INT_MASK_2 NETXEN_NIC_REG(0x1e4)
@@ -136,7 +135,8 @@
136#define CRB_NIC_CAPABILITIES_HOST NETXEN_NIC_REG(0x1a8) 135#define CRB_NIC_CAPABILITIES_HOST NETXEN_NIC_REG(0x1a8)
137#define CRB_NIC_CAPABILITIES_FW NETXEN_NIC_REG(0x1dc) 136#define CRB_NIC_CAPABILITIES_FW NETXEN_NIC_REG(0x1dc)
138#define CRB_NIC_MSI_MODE_HOST NETXEN_NIC_REG(0x270) 137#define CRB_NIC_MSI_MODE_HOST NETXEN_NIC_REG(0x270)
139#define CRB_NIC_MSI_MODE_FW NETXEN_NIC_REG(0x274) 138#define CRB_NIC_MSI_MODE_FW NETXEN_NIC_REG(0x274)
139#define CRB_FW_CAPABILITIES_1 NETXEN_NIC_REG(0x128)
140 140
141#define INTR_SCHEME_PERPORT 0x1 141#define INTR_SCHEME_PERPORT 0x1
142#define MSI_MODE_MULTIFUNC 0x1 142#define MSI_MODE_MULTIFUNC 0x1
@@ -162,7 +162,8 @@
162 162
163struct netxen_recv_crb { 163struct netxen_recv_crb {
164 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; 164 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
165 u32 crb_sts_consumer; 165 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
166 u32 sw_int_mask[NUM_STS_DESC_RINGS];
166}; 167};
167 168
168/* 169/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 04:55:03 -0500