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path: root/drivers/net/netxen/netxen_nic_hw.c
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Diffstat (limited to 'drivers/net/netxen/netxen_nic_hw.c')
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c1359
1 files changed, 1244 insertions, 115 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index a472873f48bd..defbeeac5dbe 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -38,6 +38,248 @@
38 38
39#include <net/ip.h> 39#include <net/ip.h>
40 40
41#define MASK(n) ((1ULL<<(n))-1)
42#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44#define MS_WIN(addr) (addr & 0x0ffc0000)
45
46#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48#define CRB_BLK(off) ((off >> 20) & 0x3f)
49#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50#define CRB_WINDOW_2M (0x130060)
51#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52#define CRB_INDIRECT_2M (0x1e0000UL)
53
54#define CRB_WIN_LOCK_TIMEOUT 100000000
55static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210};
211
212/*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215static unsigned crb_hub_agt[64] =
216{
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281};
282
41struct netxen_recv_crb recv_crb_registers[] = { 283struct netxen_recv_crb recv_crb_registers[] = {
42 /* 284 /*
43 * Instance 0. 285 * Instance 0.
@@ -123,7 +365,7 @@ static u64 ctx_addr_sig_regs[][3] = {
123#define NETXEN_MIN_MTU 64 365#define NETXEN_MIN_MTU 64
124#define NETXEN_ETH_FCS_SIZE 4 366#define NETXEN_ETH_FCS_SIZE 4
125#define NETXEN_ENET_HEADER_SIZE 14 367#define NETXEN_ENET_HEADER_SIZE 14
126#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ 368#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
127#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) 369#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
128#define NETXEN_NIU_HDRSIZE (0x1 << 6) 370#define NETXEN_NIU_HDRSIZE (0x1 << 6)
129#define NETXEN_NIU_TLRSIZE (0x1 << 5) 371#define NETXEN_NIU_TLRSIZE (0x1 << 5)
@@ -139,8 +381,6 @@ static u64 ctx_addr_sig_regs[][3] = {
139 381
140#define NETXEN_NIC_WINDOW_MARGIN 0x100000 382#define NETXEN_NIC_WINDOW_MARGIN 0x100000
141 383
142static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
143 unsigned long long addr);
144void netxen_free_hw_resources(struct netxen_adapter *adapter); 384void netxen_free_hw_resources(struct netxen_adapter *adapter);
145 385
146int netxen_nic_set_mac(struct net_device *netdev, void *p) 386int netxen_nic_set_mac(struct net_device *netdev, void *p)
@@ -181,9 +421,9 @@ netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
181 if (adapter->mc_enabled) 421 if (adapter->mc_enabled)
182 return 0; 422 return 0;
183 423
184 netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 424 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
185 val |= (1UL << (28+port)); 425 val |= (1UL << (28+port));
186 netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 426 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
187 427
188 /* add broadcast addr to filter */ 428 /* add broadcast addr to filter */
189 val = 0xffffff; 429 val = 0xffffff;
@@ -212,9 +452,9 @@ netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
212 if (!adapter->mc_enabled) 452 if (!adapter->mc_enabled)
213 return 0; 453 return 0;
214 454
215 netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 455 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
216 val &= ~(1UL << (28+port)); 456 val &= ~(1UL << (28+port));
217 netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 457 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
218 458
219 val = MAC_HI(addr); 459 val = MAC_HI(addr);
220 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 460 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
@@ -344,18 +584,15 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
344 584
345 585
346 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { 586 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
347 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
348 loops = 0; 587 loops = 0;
349 state = 0; 588 state = 0;
350 /* Window 1 call */ 589 do {
351 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE));
352 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
353 msleep(1);
354 /* Window 1 call */ 590 /* Window 1 call */
355 state = readl(NETXEN_CRB_NORMALIZE(adapter, 591 state = adapter->pci_read_normalize(adapter,
356 CRB_RCVPEG_STATE)); 592 CRB_RCVPEG_STATE);
593 msleep(1);
357 loops++; 594 loops++;
358 } 595 } while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20);
359 if (loops >= 20) { 596 if (loops >= 20) {
360 printk(KERN_ERR "Rcv Peg initialization not complete:" 597 printk(KERN_ERR "Rcv Peg initialization not complete:"
361 "%x.\n", state); 598 "%x.\n", state);
@@ -363,10 +600,10 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
363 return err; 600 return err;
364 } 601 }
365 } 602 }
366 adapter->intr_scheme = readl( 603 adapter->intr_scheme = adapter->pci_read_normalize(adapter,
367 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW)); 604 CRB_NIC_CAPABILITIES_FW);
368 adapter->msi_mode = readl( 605 adapter->msi_mode = adapter->pci_read_normalize(adapter,
369 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW)); 606 CRB_NIC_MSI_MODE_FW);
370 607
371 addr = pci_alloc_consistent(adapter->pdev, 608 addr = pci_alloc_consistent(adapter->pdev,
372 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), 609 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
@@ -449,12 +686,12 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
449 } 686 }
450 /* Window = 1 */ 687 /* Window = 1 */
451 688
452 writel(lower32(adapter->ctx_desc_phys_addr), 689 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id),
453 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id))); 690 lower32(adapter->ctx_desc_phys_addr));
454 writel(upper32(adapter->ctx_desc_phys_addr), 691 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id),
455 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id))); 692 upper32(adapter->ctx_desc_phys_addr));
456 writel(NETXEN_CTX_SIGNATURE | func_id, 693 adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id),
457 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id))); 694 NETXEN_CTX_SIGNATURE | func_id);
458 return err; 695 return err;
459} 696}
460 697
@@ -601,10 +838,41 @@ int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
601 return 0; 838 return 0;
602} 839}
603 840
841#define CRB_WIN_LOCK_TIMEOUT 100000000
842
843static int crb_win_lock(struct netxen_adapter *adapter)
844{
845 int done = 0, timeout = 0;
846
847 while (!done) {
848 /* acquire semaphore3 from PCI HW block */
849 adapter->hw_read_wx(adapter,
850 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
851 if (done == 1)
852 break;
853 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
854 return -1;
855 timeout++;
856 udelay(1);
857 }
858 netxen_crb_writelit_adapter(adapter,
859 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
860 return 0;
861}
862
863static void crb_win_unlock(struct netxen_adapter *adapter)
864{
865 int val;
866
867 adapter->hw_read_wx(adapter,
868 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
869}
870
604/* 871/*
605 * Changes the CRB window to the specified window. 872 * Changes the CRB window to the specified window.
606 */ 873 */
607void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw) 874void
875netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
608{ 876{
609 void __iomem *offset; 877 void __iomem *offset;
610 u32 tmp; 878 u32 tmp;
@@ -633,7 +901,7 @@ void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
633 while ((tmp = readl(offset)) != wndw) { 901 while ((tmp = readl(offset)) != wndw) {
634 printk(KERN_WARNING "%s: %s WARNING: CRB window value not " 902 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
635 "registered properly: 0x%08x.\n", 903 "registered properly: 0x%08x.\n",
636 netxen_nic_driver_name, __FUNCTION__, tmp); 904 netxen_nic_driver_name, __func__, tmp);
637 mdelay(1); 905 mdelay(1);
638 if (count >= 10) 906 if (count >= 10)
639 break; 907 break;
@@ -646,51 +914,112 @@ void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
646 adapter->curr_window = 0; 914 adapter->curr_window = 0;
647} 915}
648 916
917/*
918 * Return -1 if off is not valid,
919 * 1 if window access is needed. 'off' is set to offset from
920 * CRB space in 128M pci map
921 * 0 if no window access is needed. 'off' is set to 2M addr
922 * In: 'off' is offset from base in 128M pci map
923 */
924static int
925netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
926 ulong *off, int len)
927{
928 unsigned long end = *off + len;
929 crb_128M_2M_sub_block_map_t *m;
930
931
932 if (*off >= NETXEN_CRB_MAX)
933 return -1;
934
935 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
936 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
937 (ulong)adapter->ahw.pci_base0;
938 return 0;
939 }
940
941 if (*off < NETXEN_PCI_CRBSPACE)
942 return -1;
943
944 *off -= NETXEN_PCI_CRBSPACE;
945 end = *off + len;
946
947 /*
948 * Try direct map
949 */
950 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
951
952 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
953 *off = *off + m->start_2M - m->start_128M +
954 (ulong)adapter->ahw.pci_base0;
955 return 0;
956 }
957
958 /*
959 * Not in direct map, use crb window
960 */
961 return 1;
962}
963
964/*
965 * In: 'off' is offset from CRB space in 128M pci map
966 * Out: 'off' is 2M pci map addr
967 * side effect: lock crb window
968 */
969static void
970netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
971{
972 u32 win_read;
973
974 adapter->crb_win = CRB_HI(*off);
975 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
976 adapter->ahw.pci_base0));
977 /*
978 * Read back value to make sure write has gone through before trying
979 * to use it.
980 */
981 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
982 if (win_read != adapter->crb_win) {
983 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
984 "Read crbwin (0x%x), off=0x%lx\n",
985 __func__, adapter->crb_win, win_read, *off);
986 }
987 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
988 (ulong)adapter->ahw.pci_base0;
989}
990
649int netxen_load_firmware(struct netxen_adapter *adapter) 991int netxen_load_firmware(struct netxen_adapter *adapter)
650{ 992{
651 int i; 993 int i;
652 u32 data, size = 0; 994 u32 data, size = 0;
653 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE; 995 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
654 u64 off;
655 void __iomem *addr;
656 996
657 size = NETXEN_FIRMWARE_LEN; 997 size = NETXEN_FIRMWARE_LEN;
658 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); 998 adapter->pci_write_normalize(adapter,
999 NETXEN_ROMUSB_GLB_CAS_RST, 1);
659 1000
660 for (i = 0; i < size; i++) { 1001 for (i = 0; i < size; i++) {
661 int retries = 10;
662 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) 1002 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
663 return -EIO; 1003 return -EIO;
664 1004
665 off = netxen_nic_pci_set_window(adapter, memaddr); 1005 adapter->pci_mem_write(adapter, memaddr, &data, 4);
666 addr = pci_base_offset(adapter, off);
667 writel(data, addr);
668 do {
669 if (readl(addr) == data)
670 break;
671 msleep(100);
672 writel(data, addr);
673 } while (--retries);
674 if (!retries) {
675 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
676 netxen_nic_driver_name, memaddr);
677 return -EIO;
678 }
679 flashaddr += 4; 1006 flashaddr += 4;
680 memaddr += 4; 1007 memaddr += 4;
1008 cond_resched();
681 } 1009 }
682 udelay(100); 1010 udelay(100);
683 /* make sure Casper is powered on */ 1011 /* make sure Casper is powered on */
684 writel(0x3fff, 1012 adapter->pci_write_normalize(adapter,
685 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL)); 1013 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
686 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); 1014 adapter->pci_write_normalize(adapter,
1015 NETXEN_ROMUSB_GLB_CAS_RST, 0);
687 1016
688 return 0; 1017 return 0;
689} 1018}
690 1019
691int 1020int
692netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, 1021netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
693 int len) 1022 ulong off, void *data, int len)
694{ 1023{
695 void __iomem *addr; 1024 void __iomem *addr;
696 1025
@@ -698,7 +1027,7 @@ netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
698 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1027 addr = NETXEN_CRB_NORMALIZE(adapter, off);
699 } else { /* Window 0 */ 1028 } else { /* Window 0 */
700 addr = pci_base_offset(adapter, off); 1029 addr = pci_base_offset(adapter, off);
701 netxen_nic_pci_change_crbwindow(adapter, 0); 1030 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
702 } 1031 }
703 1032
704 DPRINTK(INFO, "writing to base %lx offset %llx addr %p" 1033 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
@@ -706,7 +1035,7 @@ netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
706 pci_base(adapter, off), off, addr, 1035 pci_base(adapter, off), off, addr,
707 *(unsigned long long *)data, len); 1036 *(unsigned long long *)data, len);
708 if (!addr) { 1037 if (!addr) {
709 netxen_nic_pci_change_crbwindow(adapter, 1); 1038 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
710 return 1; 1039 return 1;
711 } 1040 }
712 1041
@@ -733,14 +1062,14 @@ netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
733 break; 1062 break;
734 } 1063 }
735 if (!ADDR_IN_WINDOW1(off)) 1064 if (!ADDR_IN_WINDOW1(off))
736 netxen_nic_pci_change_crbwindow(adapter, 1); 1065 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
737 1066
738 return 0; 1067 return 0;
739} 1068}
740 1069
741int 1070int
742netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, 1071netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
743 int len) 1072 ulong off, void *data, int len)
744{ 1073{
745 void __iomem *addr; 1074 void __iomem *addr;
746 1075
@@ -748,13 +1077,13 @@ netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
748 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1077 addr = NETXEN_CRB_NORMALIZE(adapter, off);
749 } else { /* Window 0 */ 1078 } else { /* Window 0 */
750 addr = pci_base_offset(adapter, off); 1079 addr = pci_base_offset(adapter, off);
751 netxen_nic_pci_change_crbwindow(adapter, 0); 1080 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
752 } 1081 }
753 1082
754 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", 1083 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
755 pci_base(adapter, off), off, addr); 1084 pci_base(adapter, off), off, addr);
756 if (!addr) { 1085 if (!addr) {
757 netxen_nic_pci_change_crbwindow(adapter, 1); 1086 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
758 return 1; 1087 return 1;
759 } 1088 }
760 switch (len) { 1089 switch (len) {
@@ -778,76 +1107,190 @@ netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
778 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); 1107 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
779 1108
780 if (!ADDR_IN_WINDOW1(off)) 1109 if (!ADDR_IN_WINDOW1(off))
781 netxen_nic_pci_change_crbwindow(adapter, 1); 1110 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
782 1111
783 return 0; 1112 return 0;
784} 1113}
785 1114
786void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) 1115int
787{ /* Only for window 1 */ 1116netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
788 void __iomem *addr; 1117 ulong off, void *data, int len)
1118{
1119 unsigned long flags = 0;
1120 int rv;
789 1121
790 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1122 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
791 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
792 pci_base(adapter, off), off, addr, val);
793 writel(val, addr);
794 1123
1124 if (rv == -1) {
1125 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1126 __func__, off);
1127 dump_stack();
1128 return -1;
1129 }
1130
1131 if (rv == 1) {
1132 write_lock_irqsave(&adapter->adapter_lock, flags);
1133 crb_win_lock(adapter);
1134 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1135 }
1136
1137 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1138 *(unsigned long *)data, off, len);
1139
1140 switch (len) {
1141 case 1:
1142 writeb(*(uint8_t *)data, (void *)off);
1143 break;
1144 case 2:
1145 writew(*(uint16_t *)data, (void *)off);
1146 break;
1147 case 4:
1148 writel(*(uint32_t *)data, (void *)off);
1149 break;
1150 case 8:
1151 writeq(*(uint64_t *)data, (void *)off);
1152 break;
1153 default:
1154 DPRINTK(1, INFO,
1155 "writing data %lx to offset %llx, num words=%d\n",
1156 *(unsigned long *)data, off, (len>>3));
1157 break;
1158 }
1159 if (rv == 1) {
1160 crb_win_unlock(adapter);
1161 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1162 }
1163
1164 return 0;
795} 1165}
796 1166
797int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) 1167int
798{ /* Only for window 1 */ 1168netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
799 void __iomem *addr; 1169 ulong off, void *data, int len)
800 int val; 1170{
1171 unsigned long flags = 0;
1172 int rv;
801 1173
802 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1174 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
803 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", 1175
804 pci_base(adapter, off), off, addr); 1176 if (rv == -1) {
805 val = readl(addr); 1177 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
806 writel(val, addr); 1178 __func__, off);
1179 dump_stack();
1180 return -1;
1181 }
1182
1183 if (rv == 1) {
1184 write_lock_irqsave(&adapter->adapter_lock, flags);
1185 crb_win_lock(adapter);
1186 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1187 }
1188
1189 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1190
1191 switch (len) {
1192 case 1:
1193 *(uint8_t *)data = readb((void *)off);
1194 break;
1195 case 2:
1196 *(uint16_t *)data = readw((void *)off);
1197 break;
1198 case 4:
1199 *(uint32_t *)data = readl((void *)off);
1200 break;
1201 case 8:
1202 *(uint64_t *)data = readq((void *)off);
1203 break;
1204 default:
1205 break;
1206 }
1207
1208 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
807 1209
1210 if (rv == 1) {
1211 crb_win_unlock(adapter);
1212 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1213 }
1214
1215 return 0;
1216}
1217
1218void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1219{
1220 adapter->hw_write_wx(adapter, off, &val, 4);
1221}
1222
1223int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1224{
1225 int val;
1226 adapter->hw_read_wx(adapter, off, &val, 4);
808 return val; 1227 return val;
809} 1228}
810 1229
811/* Change the window to 0, write and change back to window 1. */ 1230/* Change the window to 0, write and change back to window 1. */
812void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) 1231void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
813{ 1232{
814 void __iomem *addr; 1233 adapter->hw_write_wx(adapter, index, &value, 4);
815
816 netxen_nic_pci_change_crbwindow(adapter, 0);
817 addr = pci_base_offset(adapter, index);
818 writel(value, addr);
819 netxen_nic_pci_change_crbwindow(adapter, 1);
820} 1234}
821 1235
822/* Change the window to 0, read and change back to window 1. */ 1236/* Change the window to 0, read and change back to window 1. */
823void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value) 1237void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
824{ 1238{
825 void __iomem *addr; 1239 adapter->hw_read_wx(adapter, index, value, 4);
1240}
826 1241
827 addr = pci_base_offset(adapter, index); 1242void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1243{
1244 adapter->hw_write_wx(adapter, index, &value, 4);
1245}
1246
1247void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1248{
1249 adapter->hw_read_wx(adapter, index, value, 4);
1250}
1251
1252/*
1253 * check memory access boundary.
1254 * used by test agent. support ddr access only for now
1255 */
1256static unsigned long
1257netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1258 unsigned long long addr, int size)
1259{
1260 if (!ADDR_IN_RANGE(addr,
1261 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1262 !ADDR_IN_RANGE(addr+size-1,
1263 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1264 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1265 return 0;
1266 }
828 1267
829 netxen_nic_pci_change_crbwindow(adapter, 0); 1268 return 1;
830 *value = readl(addr);
831 netxen_nic_pci_change_crbwindow(adapter, 1);
832} 1269}
833 1270
834static int netxen_pci_set_window_warning_count; 1271static int netxen_pci_set_window_warning_count;
835 1272
836static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, 1273unsigned long
837 unsigned long long addr) 1274netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1275 unsigned long long addr)
838{ 1276{
839 void __iomem *offset; 1277 void __iomem *offset;
840 static int ddr_mn_window = -1;
841 static int qdr_sn_window = -1;
842 int window; 1278 int window;
1279 unsigned long long qdr_max;
843 uint8_t func = adapter->ahw.pci_func; 1280 uint8_t func = adapter->ahw.pci_func;
844 1281
1282 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1283 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1284 } else {
1285 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1286 }
1287
845 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1288 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
846 /* DDR network side */ 1289 /* DDR network side */
847 addr -= NETXEN_ADDR_DDR_NET; 1290 addr -= NETXEN_ADDR_DDR_NET;
848 window = (addr >> 25) & 0x3ff; 1291 window = (addr >> 25) & 0x3ff;
849 if (ddr_mn_window != window) { 1292 if (adapter->ahw.ddr_mn_window != window) {
850 ddr_mn_window = window; 1293 adapter->ahw.ddr_mn_window = window;
851 offset = PCI_OFFSET_SECOND_RANGE(adapter, 1294 offset = PCI_OFFSET_SECOND_RANGE(adapter,
852 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func))); 1295 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
853 writel(window, offset); 1296 writel(window, offset);
@@ -862,14 +1305,12 @@ static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
862 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1305 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
863 addr -= NETXEN_ADDR_OCM1; 1306 addr -= NETXEN_ADDR_OCM1;
864 addr += NETXEN_PCI_OCM1; 1307 addr += NETXEN_PCI_OCM1;
865 } else 1308 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
866 if (ADDR_IN_RANGE
867 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P2)) {
868 /* QDR network side */ 1309 /* QDR network side */
869 addr -= NETXEN_ADDR_QDR_NET; 1310 addr -= NETXEN_ADDR_QDR_NET;
870 window = (addr >> 22) & 0x3f; 1311 window = (addr >> 22) & 0x3f;
871 if (qdr_sn_window != window) { 1312 if (adapter->ahw.qdr_sn_window != window) {
872 qdr_sn_window = window; 1313 adapter->ahw.qdr_sn_window = window;
873 offset = PCI_OFFSET_SECOND_RANGE(adapter, 1314 offset = PCI_OFFSET_SECOND_RANGE(adapter,
874 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func))); 1315 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
875 writel((window << 22), offset); 1316 writel((window << 22), offset);
@@ -888,11 +1329,711 @@ static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
888 printk("%s: Warning:netxen_nic_pci_set_window()" 1329 printk("%s: Warning:netxen_nic_pci_set_window()"
889 " Unknown address range!\n", 1330 " Unknown address range!\n",
890 netxen_nic_driver_name); 1331 netxen_nic_driver_name);
1332 addr = -1UL;
1333 }
1334 return addr;
1335}
1336
1337/*
1338 * Note : only 32-bit writes!
1339 */
1340int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1341 u64 off, u32 data)
1342{
1343 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1344 return 0;
1345}
1346
1347u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1348{
1349 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1350}
1351
1352void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1353 u64 off, u32 data)
1354{
1355 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1356}
1357
1358u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1359{
1360 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1361}
1362
1363unsigned long
1364netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1365 unsigned long long addr)
1366{
1367 int window;
1368 u32 win_read;
891 1369
1370 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1371 /* DDR network side */
1372 window = MN_WIN(addr);
1373 adapter->ahw.ddr_mn_window = window;
1374 adapter->hw_write_wx(adapter,
1375 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1376 &window, 4);
1377 adapter->hw_read_wx(adapter,
1378 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1379 &win_read, 4);
1380 if ((win_read << 17) != window) {
1381 printk(KERN_INFO "Written MNwin (0x%x) != "
1382 "Read MNwin (0x%x)\n", window, win_read);
1383 }
1384 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1385 } else if (ADDR_IN_RANGE(addr,
1386 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1387 if ((addr & 0x00ff800) == 0xff800) {
1388 printk("%s: QM access not handled.\n", __func__);
1389 addr = -1UL;
1390 }
1391
1392 window = OCM_WIN(addr);
1393 adapter->ahw.ddr_mn_window = window;
1394 adapter->hw_write_wx(adapter,
1395 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1396 &window, 4);
1397 adapter->hw_read_wx(adapter,
1398 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1399 &win_read, 4);
1400 if ((win_read >> 7) != window) {
1401 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1402 "Read OCMwin (0x%x)\n",
1403 __func__, window, win_read);
1404 }
1405 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1406
1407 } else if (ADDR_IN_RANGE(addr,
1408 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1409 /* QDR network side */
1410 window = MS_WIN(addr);
1411 adapter->ahw.qdr_sn_window = window;
1412 adapter->hw_write_wx(adapter,
1413 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1414 &window, 4);
1415 adapter->hw_read_wx(adapter,
1416 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1417 &win_read, 4);
1418 if (win_read != window) {
1419 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1420 "Read MSwin (0x%x)\n",
1421 __func__, window, win_read);
1422 }
1423 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1424
1425 } else {
1426 /*
1427 * peg gdb frequently accesses memory that doesn't exist,
1428 * this limits the chit chat so debugging isn't slowed down.
1429 */
1430 if ((netxen_pci_set_window_warning_count++ < 8)
1431 || (netxen_pci_set_window_warning_count%64 == 0)) {
1432 printk("%s: Warning:%s Unknown address range!\n",
1433 __func__, netxen_nic_driver_name);
1434}
1435 addr = -1UL;
892 } 1436 }
893 return addr; 1437 return addr;
894} 1438}
895 1439
1440static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1441 unsigned long long addr)
1442{
1443 int window;
1444 unsigned long long qdr_max;
1445
1446 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1447 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1448 else
1449 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1450
1451 if (ADDR_IN_RANGE(addr,
1452 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1453 /* DDR network side */
1454 BUG(); /* MN access can not come here */
1455 } else if (ADDR_IN_RANGE(addr,
1456 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1457 return 1;
1458 } else if (ADDR_IN_RANGE(addr,
1459 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1460 return 1;
1461 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1462 /* QDR network side */
1463 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1464 if (adapter->ahw.qdr_sn_window == window)
1465 return 1;
1466 }
1467
1468 return 0;
1469}
1470
1471static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1472 u64 off, void *data, int size)
1473{
1474 unsigned long flags;
1475 void *addr;
1476 int ret = 0;
1477 u64 start;
1478 uint8_t *mem_ptr = NULL;
1479 unsigned long mem_base;
1480 unsigned long mem_page;
1481
1482 write_lock_irqsave(&adapter->adapter_lock, flags);
1483
1484 /*
1485 * If attempting to access unknown address or straddle hw windows,
1486 * do not access.
1487 */
1488 start = adapter->pci_set_window(adapter, off);
1489 if ((start == -1UL) ||
1490 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1491 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1492 printk(KERN_ERR "%s out of bound pci memory access. "
1493 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1494 return -1;
1495 }
1496
1497 addr = (void *)(pci_base_offset(adapter, start));
1498 if (!addr) {
1499 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1500 mem_base = pci_resource_start(adapter->pdev, 0);
1501 mem_page = start & PAGE_MASK;
1502 /* Map two pages whenever user tries to access addresses in two
1503 consecutive pages.
1504 */
1505 if (mem_page != ((start + size - 1) & PAGE_MASK))
1506 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1507 else
1508 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1509 if (mem_ptr == 0UL) {
1510 *(uint8_t *)data = 0;
1511 return -1;
1512 }
1513 addr = mem_ptr;
1514 addr += start & (PAGE_SIZE - 1);
1515 write_lock_irqsave(&adapter->adapter_lock, flags);
1516 }
1517
1518 switch (size) {
1519 case 1:
1520 *(uint8_t *)data = readb(addr);
1521 break;
1522 case 2:
1523 *(uint16_t *)data = readw(addr);
1524 break;
1525 case 4:
1526 *(uint32_t *)data = readl(addr);
1527 break;
1528 case 8:
1529 *(uint64_t *)data = readq(addr);
1530 break;
1531 default:
1532 ret = -1;
1533 break;
1534 }
1535 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1536 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1537
1538 if (mem_ptr)
1539 iounmap(mem_ptr);
1540 return ret;
1541}
1542
1543static int
1544netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1545 void *data, int size)
1546{
1547 unsigned long flags;
1548 void *addr;
1549 int ret = 0;
1550 u64 start;
1551 uint8_t *mem_ptr = NULL;
1552 unsigned long mem_base;
1553 unsigned long mem_page;
1554
1555 write_lock_irqsave(&adapter->adapter_lock, flags);
1556
1557 /*
1558 * If attempting to access unknown address or straddle hw windows,
1559 * do not access.
1560 */
1561 start = adapter->pci_set_window(adapter, off);
1562 if ((start == -1UL) ||
1563 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1564 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1565 printk(KERN_ERR "%s out of bound pci memory access. "
1566 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1567 return -1;
1568 }
1569
1570 addr = (void *)(pci_base_offset(adapter, start));
1571 if (!addr) {
1572 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1573 mem_base = pci_resource_start(adapter->pdev, 0);
1574 mem_page = start & PAGE_MASK;
1575 /* Map two pages whenever user tries to access addresses in two
1576 * consecutive pages.
1577 */
1578 if (mem_page != ((start + size - 1) & PAGE_MASK))
1579 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1580 else
1581 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1582 if (mem_ptr == 0UL)
1583 return -1;
1584 addr = mem_ptr;
1585 addr += start & (PAGE_SIZE - 1);
1586 write_lock_irqsave(&adapter->adapter_lock, flags);
1587 }
1588
1589 switch (size) {
1590 case 1:
1591 writeb(*(uint8_t *)data, addr);
1592 break;
1593 case 2:
1594 writew(*(uint16_t *)data, addr);
1595 break;
1596 case 4:
1597 writel(*(uint32_t *)data, addr);
1598 break;
1599 case 8:
1600 writeq(*(uint64_t *)data, addr);
1601 break;
1602 default:
1603 ret = -1;
1604 break;
1605 }
1606 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1607 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1608 *(unsigned long long *)data, start);
1609 if (mem_ptr)
1610 iounmap(mem_ptr);
1611 return ret;
1612}
1613
1614#define MAX_CTL_CHECK 1000
1615
1616int
1617netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1618 u64 off, void *data, int size)
1619{
1620 unsigned long flags, mem_crb;
1621 int i, j, ret = 0, loop, sz[2], off0;
1622 uint32_t temp;
1623 uint64_t off8, tmpw, word[2] = {0, 0};
1624
1625 /*
1626 * If not MN, go check for MS or invalid.
1627 */
1628 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1629 return netxen_nic_pci_mem_write_direct(adapter,
1630 off, data, size);
1631
1632 off8 = off & 0xfffffff8;
1633 off0 = off & 0x7;
1634 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1635 sz[1] = size - sz[0];
1636 loop = ((off0 + size - 1) >> 3) + 1;
1637 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1638
1639 if ((size != 8) || (off0 != 0)) {
1640 for (i = 0; i < loop; i++) {
1641 if (adapter->pci_mem_read(adapter,
1642 off8 + (i << 3), &word[i], 8))
1643 return -1;
1644 }
1645 }
1646
1647 switch (size) {
1648 case 1:
1649 tmpw = *((uint8_t *)data);
1650 break;
1651 case 2:
1652 tmpw = *((uint16_t *)data);
1653 break;
1654 case 4:
1655 tmpw = *((uint32_t *)data);
1656 break;
1657 case 8:
1658 default:
1659 tmpw = *((uint64_t *)data);
1660 break;
1661 }
1662 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1663 word[0] |= tmpw << (off0 * 8);
1664
1665 if (loop == 2) {
1666 word[1] &= ~(~0ULL << (sz[1] * 8));
1667 word[1] |= tmpw >> (sz[0] * 8);
1668 }
1669
1670 write_lock_irqsave(&adapter->adapter_lock, flags);
1671 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1672
1673 for (i = 0; i < loop; i++) {
1674 writel((uint32_t)(off8 + (i << 3)),
1675 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1676 writel(0,
1677 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1678 writel(word[i] & 0xffffffff,
1679 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1680 writel((word[i] >> 32) & 0xffffffff,
1681 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1682 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1683 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1684 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1685 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1686
1687 for (j = 0; j < MAX_CTL_CHECK; j++) {
1688 temp = readl(
1689 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1690 if ((temp & MIU_TA_CTL_BUSY) == 0)
1691 break;
1692 }
1693
1694 if (j >= MAX_CTL_CHECK) {
1695 printk("%s: %s Fail to write through agent\n",
1696 __func__, netxen_nic_driver_name);
1697 ret = -1;
1698 break;
1699 }
1700 }
1701
1702 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1703 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1704 return ret;
1705}
1706
1707int
1708netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1709 u64 off, void *data, int size)
1710{
1711 unsigned long flags, mem_crb;
1712 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1713 uint32_t temp;
1714 uint64_t off8, val, word[2] = {0, 0};
1715
1716
1717 /*
1718 * If not MN, go check for MS or invalid.
1719 */
1720 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1721 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1722
1723 off8 = off & 0xfffffff8;
1724 off0[0] = off & 0x7;
1725 off0[1] = 0;
1726 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1727 sz[1] = size - sz[0];
1728 loop = ((off0[0] + size - 1) >> 3) + 1;
1729 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1730
1731 write_lock_irqsave(&adapter->adapter_lock, flags);
1732 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1733
1734 for (i = 0; i < loop; i++) {
1735 writel((uint32_t)(off8 + (i << 3)),
1736 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1737 writel(0,
1738 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1739 writel(MIU_TA_CTL_ENABLE,
1740 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1741 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1742 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1743
1744 for (j = 0; j < MAX_CTL_CHECK; j++) {
1745 temp = readl(
1746 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1747 if ((temp & MIU_TA_CTL_BUSY) == 0)
1748 break;
1749 }
1750
1751 if (j >= MAX_CTL_CHECK) {
1752 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1753 __func__, netxen_nic_driver_name);
1754 break;
1755 }
1756
1757 start = off0[i] >> 2;
1758 end = (off0[i] + sz[i] - 1) >> 2;
1759 for (k = start; k <= end; k++) {
1760 word[i] |= ((uint64_t) readl(
1761 (void *)(mem_crb +
1762 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1763 }
1764 }
1765
1766 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1767 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1768
1769 if (j >= MAX_CTL_CHECK)
1770 return -1;
1771
1772 if (sz[0] == 8) {
1773 val = word[0];
1774 } else {
1775 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1776 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1777 }
1778
1779 switch (size) {
1780 case 1:
1781 *(uint8_t *)data = val;
1782 break;
1783 case 2:
1784 *(uint16_t *)data = val;
1785 break;
1786 case 4:
1787 *(uint32_t *)data = val;
1788 break;
1789 case 8:
1790 *(uint64_t *)data = val;
1791 break;
1792 }
1793 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1794 return 0;
1795}
1796
1797int
1798netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1799 u64 off, void *data, int size)
1800{
1801 int i, j, ret = 0, loop, sz[2], off0;
1802 uint32_t temp;
1803 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1804
1805 /*
1806 * If not MN, go check for MS or invalid.
1807 */
1808 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1809 mem_crb = NETXEN_CRB_QDR_NET;
1810 else {
1811 mem_crb = NETXEN_CRB_DDR_NET;
1812 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1813 return netxen_nic_pci_mem_write_direct(adapter,
1814 off, data, size);
1815 }
1816
1817 off8 = off & 0xfffffff8;
1818 off0 = off & 0x7;
1819 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1820 sz[1] = size - sz[0];
1821 loop = ((off0 + size - 1) >> 3) + 1;
1822
1823 if ((size != 8) || (off0 != 0)) {
1824 for (i = 0; i < loop; i++) {
1825 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1826 &word[i], 8))
1827 return -1;
1828 }
1829 }
1830
1831 switch (size) {
1832 case 1:
1833 tmpw = *((uint8_t *)data);
1834 break;
1835 case 2:
1836 tmpw = *((uint16_t *)data);
1837 break;
1838 case 4:
1839 tmpw = *((uint32_t *)data);
1840 break;
1841 case 8:
1842 default:
1843 tmpw = *((uint64_t *)data);
1844 break;
1845 }
1846
1847 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1848 word[0] |= tmpw << (off0 * 8);
1849
1850 if (loop == 2) {
1851 word[1] &= ~(~0ULL << (sz[1] * 8));
1852 word[1] |= tmpw >> (sz[0] * 8);
1853 }
1854
1855 /*
1856 * don't lock here - write_wx gets the lock if each time
1857 * write_lock_irqsave(&adapter->adapter_lock, flags);
1858 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1859 */
1860
1861 for (i = 0; i < loop; i++) {
1862 temp = off8 + (i << 3);
1863 adapter->hw_write_wx(adapter,
1864 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1865 temp = 0;
1866 adapter->hw_write_wx(adapter,
1867 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1868 temp = word[i] & 0xffffffff;
1869 adapter->hw_write_wx(adapter,
1870 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1871 temp = (word[i] >> 32) & 0xffffffff;
1872 adapter->hw_write_wx(adapter,
1873 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1874 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1875 adapter->hw_write_wx(adapter,
1876 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1877 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1878 adapter->hw_write_wx(adapter,
1879 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1880
1881 for (j = 0; j < MAX_CTL_CHECK; j++) {
1882 adapter->hw_read_wx(adapter,
1883 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1884 if ((temp & MIU_TA_CTL_BUSY) == 0)
1885 break;
1886 }
1887
1888 if (j >= MAX_CTL_CHECK) {
1889 printk(KERN_ERR "%s: Fail to write through agent\n",
1890 netxen_nic_driver_name);
1891 ret = -1;
1892 break;
1893 }
1894 }
1895
1896 /*
1897 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1898 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1899 */
1900 return ret;
1901}
1902
1903int
1904netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1905 u64 off, void *data, int size)
1906{
1907 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1908 uint32_t temp;
1909 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1910
1911 /*
1912 * If not MN, go check for MS or invalid.
1913 */
1914
1915 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1916 mem_crb = NETXEN_CRB_QDR_NET;
1917 else {
1918 mem_crb = NETXEN_CRB_DDR_NET;
1919 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1920 return netxen_nic_pci_mem_read_direct(adapter,
1921 off, data, size);
1922 }
1923
1924 off8 = off & 0xfffffff8;
1925 off0[0] = off & 0x7;
1926 off0[1] = 0;
1927 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1928 sz[1] = size - sz[0];
1929 loop = ((off0[0] + size - 1) >> 3) + 1;
1930
1931 /*
1932 * don't lock here - write_wx gets the lock if each time
1933 * write_lock_irqsave(&adapter->adapter_lock, flags);
1934 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1935 */
1936
1937 for (i = 0; i < loop; i++) {
1938 temp = off8 + (i << 3);
1939 adapter->hw_write_wx(adapter,
1940 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1941 temp = 0;
1942 adapter->hw_write_wx(adapter,
1943 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1944 temp = MIU_TA_CTL_ENABLE;
1945 adapter->hw_write_wx(adapter,
1946 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1947 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1948 adapter->hw_write_wx(adapter,
1949 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1950
1951 for (j = 0; j < MAX_CTL_CHECK; j++) {
1952 adapter->hw_read_wx(adapter,
1953 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1954 if ((temp & MIU_TA_CTL_BUSY) == 0)
1955 break;
1956 }
1957
1958 if (j >= MAX_CTL_CHECK) {
1959 printk(KERN_ERR "%s: Fail to read through agent\n",
1960 netxen_nic_driver_name);
1961 break;
1962 }
1963
1964 start = off0[i] >> 2;
1965 end = (off0[i] + sz[i] - 1) >> 2;
1966 for (k = start; k <= end; k++) {
1967 adapter->hw_read_wx(adapter,
1968 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1969 word[i] |= ((uint64_t)temp << (32 * k));
1970 }
1971 }
1972
1973 /*
1974 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1975 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1976 */
1977
1978 if (j >= MAX_CTL_CHECK)
1979 return -1;
1980
1981 if (sz[0] == 8) {
1982 val = word[0];
1983 } else {
1984 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1985 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1986 }
1987
1988 switch (size) {
1989 case 1:
1990 *(uint8_t *)data = val;
1991 break;
1992 case 2:
1993 *(uint16_t *)data = val;
1994 break;
1995 case 4:
1996 *(uint32_t *)data = val;
1997 break;
1998 case 8:
1999 *(uint64_t *)data = val;
2000 break;
2001 }
2002 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
2003 return 0;
2004}
2005
2006/*
2007 * Note : only 32-bit writes!
2008 */
2009int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2010 u64 off, u32 data)
2011{
2012 adapter->hw_write_wx(adapter, off, &data, 4);
2013
2014 return 0;
2015}
2016
2017u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2018{
2019 u32 temp;
2020 adapter->hw_read_wx(adapter, off, &temp, 4);
2021 return temp;
2022}
2023
2024void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2025 u64 off, u32 data)
2026{
2027 adapter->hw_write_wx(adapter, off, &data, 4);
2028}
2029
2030u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2031{
2032 u32 temp;
2033 adapter->hw_read_wx(adapter, off, &temp, 4);
2034 return temp;
2035}
2036
896#if 0 2037#if 0
897int 2038int
898netxen_nic_erase_pxe(struct netxen_adapter *adapter) 2039netxen_nic_erase_pxe(struct netxen_adapter *adapter)
@@ -1006,19 +2147,10 @@ void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1006} 2147}
1007 2148
1008void 2149void
1009netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off, 2150netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1010 int data) 2151 unsigned long off, int data)
1011{ 2152{
1012 void __iomem *addr; 2153 adapter->hw_write_wx(adapter, off, &data, 4);
1013
1014 if (ADDR_IN_WINDOW1(off)) {
1015 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1016 } else {
1017 netxen_nic_pci_change_crbwindow(adapter, 0);
1018 addr = pci_base_offset(adapter, off);
1019 writel(data, addr);
1020 netxen_nic_pci_change_crbwindow(adapter, 1);
1021 }
1022} 2154}
1023 2155
1024void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 2156void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
@@ -1105,12 +2237,9 @@ void netxen_nic_flash_print(struct netxen_adapter *adapter)
1105 addr += sizeof(u32); 2237 addr += sizeof(u32);
1106 } 2238 }
1107 2239
1108 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter, 2240 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
1109 NETXEN_FW_VERSION_MAJOR)); 2241 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
1110 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter, 2242 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
1111 NETXEN_FW_VERSION_MINOR));
1112 fw_build =
1113 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1114 2243
1115 if (adapter->portnum == 0) { 2244 if (adapter->portnum == 0) {
1116 get_brd_name_by_type(board_info->board_type, brd_name); 2245 get_brd_name_by_type(board_info->board_type, brd_name);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 20:12:33 -0400