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Diffstat (limited to 'drivers/net/netxen/netxen_nic_hdr.h')
-rw-r--r--drivers/net/netxen/netxen_nic_hdr.h69
1 files changed, 38 insertions, 31 deletions
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
index 7a7177421d7c..34613503262f 100644
--- a/drivers/net/netxen/netxen_nic_hdr.h
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -661,40 +661,47 @@ enum {
661#define NETXEN_NIU_AP_STATION_ADDR_0(I) (NETXEN_CRB_NIU+0xa0040+(I)*0x10000) 661#define NETXEN_NIU_AP_STATION_ADDR_0(I) (NETXEN_CRB_NIU+0xa0040+(I)*0x10000)
662#define NETXEN_NIU_AP_STATION_ADDR_1(I) (NETXEN_CRB_NIU+0xa0044+(I)*0x10000) 662#define NETXEN_NIU_AP_STATION_ADDR_1(I) (NETXEN_CRB_NIU+0xa0044+(I)*0x10000)
663 663
664
665#define TEST_AGT_CTRL (0x00)
666
667#define TA_CTL_START 1
668#define TA_CTL_ENABLE 2
669#define TA_CTL_WRITE 4
670#define TA_CTL_BUSY 8
671
664/* 672/*
665 * Register offsets for MN 673 * Register offsets for MN
666 */ 674 */
667#define MIU_CONTROL (0x000) 675#define MIU_TEST_AGT_BASE (0x90)
668#define MIU_TEST_AGT_CTRL (0x090) 676
669#define MIU_TEST_AGT_ADDR_LO (0x094) 677#define MIU_TEST_AGT_ADDR_LO (0x04)
670#define MIU_TEST_AGT_ADDR_HI (0x098) 678#define MIU_TEST_AGT_ADDR_HI (0x08)
671#define MIU_TEST_AGT_WRDATA_LO (0x0a0) 679#define MIU_TEST_AGT_WRDATA_LO (0x10)
672#define MIU_TEST_AGT_WRDATA_HI (0x0a4) 680#define MIU_TEST_AGT_WRDATA_HI (0x14)
673#define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 681#define MIU_TEST_AGT_WRDATA(i) (0x10+(4*(i)))
674#define MIU_TEST_AGT_RDDATA_LO (0x0a8) 682#define MIU_TEST_AGT_RDDATA_LO (0x18)
675#define MIU_TEST_AGT_RDDATA_HI (0x0ac) 683#define MIU_TEST_AGT_RDDATA_HI (0x1c)
676#define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 684#define MIU_TEST_AGT_RDDATA(i) (0x18+(4*(i)))
677#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 685
678#define MIU_TEST_AGT_UPPER_ADDR(off) (0) 686#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
679 687#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
680/* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 688
681#define MIU_TA_CTL_START 1 689/*
682#define MIU_TA_CTL_ENABLE 2 690 * Register offsets for MS
683#define MIU_TA_CTL_WRITE 4 691 */
684#define MIU_TA_CTL_BUSY 8 692#define SIU_TEST_AGT_BASE (0x60)
685 693
686#define SIU_TEST_AGT_CTRL (0x060) 694#define SIU_TEST_AGT_ADDR_LO (0x04)
687#define SIU_TEST_AGT_ADDR_LO (0x064) 695#define SIU_TEST_AGT_ADDR_HI (0x18)
688#define SIU_TEST_AGT_ADDR_HI (0x078) 696#define SIU_TEST_AGT_WRDATA_LO (0x08)
689#define SIU_TEST_AGT_WRDATA_LO (0x068) 697#define SIU_TEST_AGT_WRDATA_HI (0x0c)
690#define SIU_TEST_AGT_WRDATA_HI (0x06c) 698#define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i)))
691#define SIU_TEST_AGT_WRDATA(i) (0x068+(4*(i))) 699#define SIU_TEST_AGT_RDDATA_LO (0x10)
692#define SIU_TEST_AGT_RDDATA_LO (0x070) 700#define SIU_TEST_AGT_RDDATA_HI (0x14)
693#define SIU_TEST_AGT_RDDATA_HI (0x074) 701#define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i)))
694#define SIU_TEST_AGT_RDDATA(i) (0x070+(4*(i))) 702
695 703#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
696#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8 704#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
697#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
698 705
699/* XG Link status */ 706/* XG Link status */
700#define XG_LINK_UP 0x10 707#define XG_LINK_UP 0x10