aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/natsemi.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/natsemi.c')
-rw-r--r--drivers/net/natsemi.c3273
1 files changed, 3273 insertions, 0 deletions
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
new file mode 100644
index 000000000000..223bdadd4c0d
--- /dev/null
+++ b/drivers/net/natsemi.c
@@ -0,0 +1,3273 @@
1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL. License for under other terms may be
13 available. Contact the original author for details.
14
15 The original author may be reached as becker@scyld.com, or at
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support information and updates available at
21 http://www.scyld.com/network/netsemi.html
22
23
24 Linux kernel modifications:
25
26 Version 1.0.1:
27 - Spinlock fixes
28 - Bug fixes and better intr performance (Tjeerd)
29 Version 1.0.2:
30 - Now reads correct MAC address from eeprom
31 Version 1.0.3:
32 - Eliminate redundant priv->tx_full flag
33 - Call netif_start_queue from dev->tx_timeout
34 - wmb() in start_tx() to flush data
35 - Update Tx locking
36 - Clean up PCI enable (davej)
37 Version 1.0.4:
38 - Merge Donald Becker's natsemi.c version 1.07
39 Version 1.0.5:
40 - { fill me in }
41 Version 1.0.6:
42 * ethtool support (jgarzik)
43 * Proper initialization of the card (which sometimes
44 fails to occur and leaves the card in a non-functional
45 state). (uzi)
46
47 * Some documented register settings to optimize some
48 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
49
50 * Polling of the PHY intr for stuff like link state
51 change and auto- negotiation to finally work properly. (uzi)
52
53 * One-liner removal of a duplicate declaration of
54 netdev_error(). (uzi)
55
56 Version 1.0.7: (Manfred Spraul)
57 * pci dma
58 * SMP locking update
59 * full reset added into tx_timeout
60 * correct multicast hash generation (both big and little endian)
61 [copied from a natsemi driver version
62 from Myrio Corporation, Greg Smith]
63 * suspend/resume
64
65 version 1.0.8 (Tim Hockin <thockin@sun.com>)
66 * ETHTOOL_* support
67 * Wake on lan support (Erik Gilling)
68 * MXDMA fixes for serverworks
69 * EEPROM reload
70
71 version 1.0.9 (Manfred Spraul)
72 * Main change: fix lack of synchronize
73 netif_close/netif_suspend against a last interrupt
74 or packet.
75 * do not enable superflous interrupts (e.g. the
76 drivers relies on TxDone - TxIntr not needed)
77 * wait that the hardware has really stopped in close
78 and suspend.
79 * workaround for the (at least) gcc-2.95.1 compiler
80 problem. Also simplifies the code a bit.
81 * disable_irq() in tx_timeout - needed to protect
82 against rx interrupts.
83 * stop the nic before switching into silent rx mode
84 for wol (required according to docu).
85
86 version 1.0.10:
87 * use long for ee_addr (various)
88 * print pointers properly (DaveM)
89 * include asm/irq.h (?)
90
91 version 1.0.11:
92 * check and reset if PHY errors appear (Adrian Sun)
93 * WoL cleanup (Tim Hockin)
94 * Magic number cleanup (Tim Hockin)
95 * Don't reload EEPROM on every reset (Tim Hockin)
96 * Save and restore EEPROM state across reset (Tim Hockin)
97 * MDIO Cleanup (Tim Hockin)
98 * Reformat register offsets/bits (jgarzik)
99
100 version 1.0.12:
101 * ETHTOOL_* further support (Tim Hockin)
102
103 version 1.0.13:
104 * ETHTOOL_[G]EEPROM support (Tim Hockin)
105
106 version 1.0.13:
107 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
108
109 version 1.0.14:
110 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
111
112 version 1.0.15:
113 * Get rid of cable_magic flag
114 * use new (National provided) solution for cable magic issue
115
116 version 1.0.16:
117 * call netdev_rx() for RxErrors (Manfred Spraul)
118 * formatting and cleanups
119 * change options and full_duplex arrays to be zero
120 initialized
121 * enable only the WoL and PHY interrupts in wol mode
122
123 version 1.0.17:
124 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
125 * create a function for rx refill (Manfred Spraul)
126 * combine drain_ring and init_ring (Manfred Spraul)
127 * oom handling (Manfred Spraul)
128 * hands_off instead of playing with netif_device_{de,a}ttach
129 (Manfred Spraul)
130 * be sure to write the MAC back to the chip (Manfred Spraul)
131 * lengthen EEPROM timeout, and always warn about timeouts
132 (Manfred Spraul)
133 * comments update (Manfred)
134 * do the right thing on a phy-reset (Manfred and Tim)
135
136 TODO:
137 * big endian support with CFG:BEM instead of cpu_to_le32
138 * support for an external PHY
139 * NAPI
140*/
141
142#include <linux/config.h>
143#include <linux/module.h>
144#include <linux/kernel.h>
145#include <linux/string.h>
146#include <linux/timer.h>
147#include <linux/errno.h>
148#include <linux/ioport.h>
149#include <linux/slab.h>
150#include <linux/interrupt.h>
151#include <linux/pci.h>
152#include <linux/netdevice.h>
153#include <linux/etherdevice.h>
154#include <linux/skbuff.h>
155#include <linux/init.h>
156#include <linux/spinlock.h>
157#include <linux/ethtool.h>
158#include <linux/delay.h>
159#include <linux/rtnetlink.h>
160#include <linux/mii.h>
161#include <linux/crc32.h>
162#include <linux/bitops.h>
163#include <asm/processor.h> /* Processor type for cache alignment. */
164#include <asm/io.h>
165#include <asm/irq.h>
166#include <asm/uaccess.h>
167
168#define DRV_NAME "natsemi"
169#define DRV_VERSION "1.07+LK1.0.17"
170#define DRV_RELDATE "Sep 27, 2002"
171
172#define RX_OFFSET 2
173
174/* Updated to recommendations in pci-skeleton v2.03. */
175
176/* The user-configurable values.
177 These may be modified when a driver module is loaded.*/
178
179#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
180 NETIF_MSG_LINK | \
181 NETIF_MSG_WOL | \
182 NETIF_MSG_RX_ERR | \
183 NETIF_MSG_TX_ERR)
184static int debug = -1;
185
186/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
187static int max_interrupt_work = 20;
188static int mtu;
189
190/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
191 This chip uses a 512 element hash table based on the Ethernet CRC. */
192static int multicast_filter_limit = 100;
193
194/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
195 Setting to > 1518 effectively disables this feature. */
196static int rx_copybreak;
197
198/* Used to pass the media type, etc.
199 Both 'options[]' and 'full_duplex[]' should exist for driver
200 interoperability.
201 The media type is usually passed in 'options[]'.
202*/
203#define MAX_UNITS 8 /* More are supported, limit only on options */
204static int options[MAX_UNITS];
205static int full_duplex[MAX_UNITS];
206
207/* Operational parameters that are set at compile time. */
208
209/* Keep the ring sizes a power of two for compile efficiency.
210 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
211 Making the Tx ring too large decreases the effectiveness of channel
212 bonding and packet priority.
213 There are no ill effects from too-large receive rings. */
214#define TX_RING_SIZE 16
215#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
216#define RX_RING_SIZE 32
217
218/* Operational parameters that usually are not changed. */
219/* Time in jiffies before concluding the transmitter is hung. */
220#define TX_TIMEOUT (2*HZ)
221
222#define NATSEMI_HW_TIMEOUT 400
223#define NATSEMI_TIMER_FREQ 3*HZ
224#define NATSEMI_PG0_NREGS 64
225#define NATSEMI_RFDR_NREGS 8
226#define NATSEMI_PG1_NREGS 4
227#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
228 NATSEMI_PG1_NREGS)
229#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
230#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
231#define NATSEMI_EEPROM_SIZE 24 /* 12 16-bit values */
232
233/* Buffer sizes:
234 * The nic writes 32-bit values, even if the upper bytes of
235 * a 32-bit value are beyond the end of the buffer.
236 */
237#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
238#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
239#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
240#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
241
242/* These identify the driver base version and may not be removed. */
243static char version[] __devinitdata =
244 KERN_INFO DRV_NAME " dp8381x driver, version "
245 DRV_VERSION ", " DRV_RELDATE "\n"
246 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
247 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
248 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
249
250MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
251MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
252MODULE_LICENSE("GPL");
253
254module_param(max_interrupt_work, int, 0);
255module_param(mtu, int, 0);
256module_param(debug, int, 0);
257module_param(rx_copybreak, int, 0);
258module_param_array(options, int, NULL, 0);
259module_param_array(full_duplex, int, NULL, 0);
260MODULE_PARM_DESC(max_interrupt_work,
261 "DP8381x maximum events handled per interrupt");
262MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
263MODULE_PARM_DESC(debug, "DP8381x default debug level");
264MODULE_PARM_DESC(rx_copybreak,
265 "DP8381x copy breakpoint for copy-only-tiny-frames");
266MODULE_PARM_DESC(options,
267 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
268MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
269
270/*
271 Theory of Operation
272
273I. Board Compatibility
274
275This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
276It also works with other chips in in the DP83810 series.
277
278II. Board-specific settings
279
280This driver requires the PCI interrupt line to be valid.
281It honors the EEPROM-set values.
282
283III. Driver operation
284
285IIIa. Ring buffers
286
287This driver uses two statically allocated fixed-size descriptor lists
288formed into rings by a branch from the final descriptor to the beginning of
289the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
290The NatSemi design uses a 'next descriptor' pointer that the driver forms
291into a list.
292
293IIIb/c. Transmit/Receive Structure
294
295This driver uses a zero-copy receive and transmit scheme.
296The driver allocates full frame size skbuffs for the Rx ring buffers at
297open() time and passes the skb->data field to the chip as receive data
298buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
299a fresh skbuff is allocated and the frame is copied to the new skbuff.
300When the incoming frame is larger, the skbuff is passed directly up the
301protocol stack. Buffers consumed this way are replaced by newly allocated
302skbuffs in a later phase of receives.
303
304The RX_COPYBREAK value is chosen to trade-off the memory wasted by
305using a full-sized skbuff for small frames vs. the copying costs of larger
306frames. New boards are typically used in generously configured machines
307and the underfilled buffers have negligible impact compared to the benefit of
308a single allocation size, so the default value of zero results in never
309copying packets. When copying is done, the cost is usually mitigated by using
310a combined copy/checksum routine. Copying also preloads the cache, which is
311most useful with small frames.
312
313A subtle aspect of the operation is that unaligned buffers are not permitted
314by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
315longword aligned for further processing. On copies frames are put into the
316skbuff at an offset of "+2", 16-byte aligning the IP header.
317
318IIId. Synchronization
319
320Most operations are synchronized on the np->lock irq spinlock, except the
321performance critical codepaths:
322
323The rx process only runs in the interrupt handler. Access from outside
324the interrupt handler is only permitted after disable_irq().
325
326The rx process usually runs under the dev->xmit_lock. If np->intr_tx_reap
327is set, then access is permitted under spin_lock_irq(&np->lock).
328
329Thus configuration functions that want to access everything must call
330 disable_irq(dev->irq);
331 spin_lock_bh(dev->xmit_lock);
332 spin_lock_irq(&np->lock);
333
334IV. Notes
335
336NatSemi PCI network controllers are very uncommon.
337
338IVb. References
339
340http://www.scyld.com/expert/100mbps.html
341http://www.scyld.com/expert/NWay.html
342Datasheet is available from:
343http://www.national.com/pf/DP/DP83815.html
344
345IVc. Errata
346
347None characterised.
348*/
349
350
351
352enum pcistuff {
353 PCI_USES_IO = 0x01,
354 PCI_USES_MEM = 0x02,
355 PCI_USES_MASTER = 0x04,
356 PCI_ADDR0 = 0x08,
357 PCI_ADDR1 = 0x10,
358};
359
360/* MMIO operations required */
361#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
362
363
364/*
365 * Support for fibre connections on Am79C874:
366 * This phy needs a special setup when connected to a fibre cable.
367 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
368 */
369#define PHYID_AM79C874 0x0022561b
370
371#define MII_MCTRL 0x15 /* mode control register */
372#define MII_FX_SEL 0x0001 /* 100BASE-FX (fiber) */
373#define MII_EN_SCRM 0x0004 /* enable scrambler (tp) */
374
375
376/* array of board data directly indexed by pci_tbl[x].driver_data */
377static struct {
378 const char *name;
379 unsigned long flags;
380} natsemi_pci_info[] __devinitdata = {
381 { "NatSemi DP8381[56]", PCI_IOTYPE },
382};
383
384static struct pci_device_id natsemi_pci_tbl[] = {
385 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, PCI_ANY_ID, },
386 { 0, },
387};
388MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
389
390/* Offsets to the device registers.
391 Unlike software-only systems, device drivers interact with complex hardware.
392 It's not useful to define symbolic names for every register bit in the
393 device.
394*/
395enum register_offsets {
396 ChipCmd = 0x00,
397 ChipConfig = 0x04,
398 EECtrl = 0x08,
399 PCIBusCfg = 0x0C,
400 IntrStatus = 0x10,
401 IntrMask = 0x14,
402 IntrEnable = 0x18,
403 IntrHoldoff = 0x1C, /* DP83816 only */
404 TxRingPtr = 0x20,
405 TxConfig = 0x24,
406 RxRingPtr = 0x30,
407 RxConfig = 0x34,
408 ClkRun = 0x3C,
409 WOLCmd = 0x40,
410 PauseCmd = 0x44,
411 RxFilterAddr = 0x48,
412 RxFilterData = 0x4C,
413 BootRomAddr = 0x50,
414 BootRomData = 0x54,
415 SiliconRev = 0x58,
416 StatsCtrl = 0x5C,
417 StatsData = 0x60,
418 RxPktErrs = 0x60,
419 RxMissed = 0x68,
420 RxCRCErrs = 0x64,
421 BasicControl = 0x80,
422 BasicStatus = 0x84,
423 AnegAdv = 0x90,
424 AnegPeer = 0x94,
425 PhyStatus = 0xC0,
426 MIntrCtrl = 0xC4,
427 MIntrStatus = 0xC8,
428 PhyCtrl = 0xE4,
429
430 /* These are from the spec, around page 78... on a separate table.
431 * The meaning of these registers depend on the value of PGSEL. */
432 PGSEL = 0xCC,
433 PMDCSR = 0xE4,
434 TSTDAT = 0xFC,
435 DSPCFG = 0xF4,
436 SDCFG = 0xF8
437};
438/* the values for the 'magic' registers above (PGSEL=1) */
439#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
440#define TSTDAT_VAL 0x0
441#define DSPCFG_VAL 0x5040
442#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
443#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
444#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
445#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
446
447/* misc PCI space registers */
448enum pci_register_offsets {
449 PCIPM = 0x44,
450};
451
452enum ChipCmd_bits {
453 ChipReset = 0x100,
454 RxReset = 0x20,
455 TxReset = 0x10,
456 RxOff = 0x08,
457 RxOn = 0x04,
458 TxOff = 0x02,
459 TxOn = 0x01,
460};
461
462enum ChipConfig_bits {
463 CfgPhyDis = 0x200,
464 CfgPhyRst = 0x400,
465 CfgExtPhy = 0x1000,
466 CfgAnegEnable = 0x2000,
467 CfgAneg100 = 0x4000,
468 CfgAnegFull = 0x8000,
469 CfgAnegDone = 0x8000000,
470 CfgFullDuplex = 0x20000000,
471 CfgSpeed100 = 0x40000000,
472 CfgLink = 0x80000000,
473};
474
475enum EECtrl_bits {
476 EE_ShiftClk = 0x04,
477 EE_DataIn = 0x01,
478 EE_ChipSelect = 0x08,
479 EE_DataOut = 0x02,
480 MII_Data = 0x10,
481 MII_Write = 0x20,
482 MII_ShiftClk = 0x40,
483};
484
485enum PCIBusCfg_bits {
486 EepromReload = 0x4,
487};
488
489/* Bits in the interrupt status/mask registers. */
490enum IntrStatus_bits {
491 IntrRxDone = 0x0001,
492 IntrRxIntr = 0x0002,
493 IntrRxErr = 0x0004,
494 IntrRxEarly = 0x0008,
495 IntrRxIdle = 0x0010,
496 IntrRxOverrun = 0x0020,
497 IntrTxDone = 0x0040,
498 IntrTxIntr = 0x0080,
499 IntrTxErr = 0x0100,
500 IntrTxIdle = 0x0200,
501 IntrTxUnderrun = 0x0400,
502 StatsMax = 0x0800,
503 SWInt = 0x1000,
504 WOLPkt = 0x2000,
505 LinkChange = 0x4000,
506 IntrHighBits = 0x8000,
507 RxStatusFIFOOver = 0x10000,
508 IntrPCIErr = 0xf00000,
509 RxResetDone = 0x1000000,
510 TxResetDone = 0x2000000,
511 IntrAbnormalSummary = 0xCD20,
512};
513
514/*
515 * Default Interrupts:
516 * Rx OK, Rx Packet Error, Rx Overrun,
517 * Tx OK, Tx Packet Error, Tx Underrun,
518 * MIB Service, Phy Interrupt, High Bits,
519 * Rx Status FIFO overrun,
520 * Received Target Abort, Received Master Abort,
521 * Signalled System Error, Received Parity Error
522 */
523#define DEFAULT_INTR 0x00f1cd65
524
525enum TxConfig_bits {
526 TxDrthMask = 0x3f,
527 TxFlthMask = 0x3f00,
528 TxMxdmaMask = 0x700000,
529 TxMxdma_512 = 0x0,
530 TxMxdma_4 = 0x100000,
531 TxMxdma_8 = 0x200000,
532 TxMxdma_16 = 0x300000,
533 TxMxdma_32 = 0x400000,
534 TxMxdma_64 = 0x500000,
535 TxMxdma_128 = 0x600000,
536 TxMxdma_256 = 0x700000,
537 TxCollRetry = 0x800000,
538 TxAutoPad = 0x10000000,
539 TxMacLoop = 0x20000000,
540 TxHeartIgn = 0x40000000,
541 TxCarrierIgn = 0x80000000
542};
543
544/*
545 * Tx Configuration:
546 * - 256 byte DMA burst length
547 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
548 * - 64 bytes initial drain threshold (i.e. begin actual transmission
549 * when 64 byte are in the fifo)
550 * - on tx underruns, increase drain threshold by 64.
551 * - at most use a drain threshold of 1472 bytes: The sum of the fill
552 * threshold and the drain threshold must be less than 2016 bytes.
553 *
554 */
555#define TX_FLTH_VAL ((512/32) << 8)
556#define TX_DRTH_VAL_START (64/32)
557#define TX_DRTH_VAL_INC 2
558#define TX_DRTH_VAL_LIMIT (1472/32)
559
560enum RxConfig_bits {
561 RxDrthMask = 0x3e,
562 RxMxdmaMask = 0x700000,
563 RxMxdma_512 = 0x0,
564 RxMxdma_4 = 0x100000,
565 RxMxdma_8 = 0x200000,
566 RxMxdma_16 = 0x300000,
567 RxMxdma_32 = 0x400000,
568 RxMxdma_64 = 0x500000,
569 RxMxdma_128 = 0x600000,
570 RxMxdma_256 = 0x700000,
571 RxAcceptLong = 0x8000000,
572 RxAcceptTx = 0x10000000,
573 RxAcceptRunt = 0x40000000,
574 RxAcceptErr = 0x80000000
575};
576#define RX_DRTH_VAL (128/8)
577
578enum ClkRun_bits {
579 PMEEnable = 0x100,
580 PMEStatus = 0x8000,
581};
582
583enum WolCmd_bits {
584 WakePhy = 0x1,
585 WakeUnicast = 0x2,
586 WakeMulticast = 0x4,
587 WakeBroadcast = 0x8,
588 WakeArp = 0x10,
589 WakePMatch0 = 0x20,
590 WakePMatch1 = 0x40,
591 WakePMatch2 = 0x80,
592 WakePMatch3 = 0x100,
593 WakeMagic = 0x200,
594 WakeMagicSecure = 0x400,
595 SecureHack = 0x100000,
596 WokePhy = 0x400000,
597 WokeUnicast = 0x800000,
598 WokeMulticast = 0x1000000,
599 WokeBroadcast = 0x2000000,
600 WokeArp = 0x4000000,
601 WokePMatch0 = 0x8000000,
602 WokePMatch1 = 0x10000000,
603 WokePMatch2 = 0x20000000,
604 WokePMatch3 = 0x40000000,
605 WokeMagic = 0x80000000,
606 WakeOptsSummary = 0x7ff
607};
608
609enum RxFilterAddr_bits {
610 RFCRAddressMask = 0x3ff,
611 AcceptMulticast = 0x00200000,
612 AcceptMyPhys = 0x08000000,
613 AcceptAllPhys = 0x10000000,
614 AcceptAllMulticast = 0x20000000,
615 AcceptBroadcast = 0x40000000,
616 RxFilterEnable = 0x80000000
617};
618
619enum StatsCtrl_bits {
620 StatsWarn = 0x1,
621 StatsFreeze = 0x2,
622 StatsClear = 0x4,
623 StatsStrobe = 0x8,
624};
625
626enum MIntrCtrl_bits {
627 MICRIntEn = 0x2,
628};
629
630enum PhyCtrl_bits {
631 PhyAddrMask = 0x1f,
632};
633
634#define PHY_ADDR_NONE 32
635#define PHY_ADDR_INTERNAL 1
636
637/* values we might find in the silicon revision register */
638#define SRR_DP83815_C 0x0302
639#define SRR_DP83815_D 0x0403
640#define SRR_DP83816_A4 0x0504
641#define SRR_DP83816_A5 0x0505
642
643/* The Rx and Tx buffer descriptors. */
644/* Note that using only 32 bit fields simplifies conversion to big-endian
645 architectures. */
646struct netdev_desc {
647 u32 next_desc;
648 s32 cmd_status;
649 u32 addr;
650 u32 software_use;
651};
652
653/* Bits in network_desc.status */
654enum desc_status_bits {
655 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
656 DescNoCRC=0x10000000, DescPktOK=0x08000000,
657 DescSizeMask=0xfff,
658
659 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
660 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
661 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
662 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
663
664 DescRxAbort=0x04000000, DescRxOver=0x02000000,
665 DescRxDest=0x01800000, DescRxLong=0x00400000,
666 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
667 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
668 DescRxLoop=0x00020000, DesRxColl=0x00010000,
669};
670
671struct netdev_private {
672 /* Descriptor rings first for alignment */
673 dma_addr_t ring_dma;
674 struct netdev_desc *rx_ring;
675 struct netdev_desc *tx_ring;
676 /* The addresses of receive-in-place skbuffs */
677 struct sk_buff *rx_skbuff[RX_RING_SIZE];
678 dma_addr_t rx_dma[RX_RING_SIZE];
679 /* address of a sent-in-place packet/buffer, for later free() */
680 struct sk_buff *tx_skbuff[TX_RING_SIZE];
681 dma_addr_t tx_dma[TX_RING_SIZE];
682 struct net_device_stats stats;
683 /* Media monitoring timer */
684 struct timer_list timer;
685 /* Frequently used values: keep some adjacent for cache effect */
686 struct pci_dev *pci_dev;
687 struct netdev_desc *rx_head_desc;
688 /* Producer/consumer ring indices */
689 unsigned int cur_rx, dirty_rx;
690 unsigned int cur_tx, dirty_tx;
691 /* Based on MTU+slack. */
692 unsigned int rx_buf_sz;
693 int oom;
694 /* Do not touch the nic registers */
695 int hands_off;
696 /* external phy that is used: only valid if dev->if_port != PORT_TP */
697 int mii;
698 int phy_addr_external;
699 unsigned int full_duplex;
700 /* Rx filter */
701 u32 cur_rx_mode;
702 u32 rx_filter[16];
703 /* FIFO and PCI burst thresholds */
704 u32 tx_config, rx_config;
705 /* original contents of ClkRun register */
706 u32 SavedClkRun;
707 /* silicon revision */
708 u32 srr;
709 /* expected DSPCFG value */
710 u16 dspcfg;
711 /* parms saved in ethtool format */
712 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
713 u8 duplex; /* Duplex, half or full */
714 u8 autoneg; /* Autonegotiation enabled */
715 /* MII transceiver section */
716 u16 advertising;
717 unsigned int iosize;
718 spinlock_t lock;
719 u32 msg_enable;
720};
721
722static void move_int_phy(struct net_device *dev, int addr);
723static int eeprom_read(void __iomem *ioaddr, int location);
724static int mdio_read(struct net_device *dev, int reg);
725static void mdio_write(struct net_device *dev, int reg, u16 data);
726static void init_phy_fixup(struct net_device *dev);
727static int miiport_read(struct net_device *dev, int phy_id, int reg);
728static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
729static int find_mii(struct net_device *dev);
730static void natsemi_reset(struct net_device *dev);
731static void natsemi_reload_eeprom(struct net_device *dev);
732static void natsemi_stop_rxtx(struct net_device *dev);
733static int netdev_open(struct net_device *dev);
734static void do_cable_magic(struct net_device *dev);
735static void undo_cable_magic(struct net_device *dev);
736static void check_link(struct net_device *dev);
737static void netdev_timer(unsigned long data);
738static void dump_ring(struct net_device *dev);
739static void tx_timeout(struct net_device *dev);
740static int alloc_ring(struct net_device *dev);
741static void refill_rx(struct net_device *dev);
742static void init_ring(struct net_device *dev);
743static void drain_tx(struct net_device *dev);
744static void drain_ring(struct net_device *dev);
745static void free_ring(struct net_device *dev);
746static void reinit_ring(struct net_device *dev);
747static void init_registers(struct net_device *dev);
748static int start_tx(struct sk_buff *skb, struct net_device *dev);
749static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
750static void netdev_error(struct net_device *dev, int intr_status);
751static void netdev_rx(struct net_device *dev);
752static void netdev_tx_done(struct net_device *dev);
753static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
754#ifdef CONFIG_NET_POLL_CONTROLLER
755static void natsemi_poll_controller(struct net_device *dev);
756#endif
757static void __set_rx_mode(struct net_device *dev);
758static void set_rx_mode(struct net_device *dev);
759static void __get_stats(struct net_device *dev);
760static struct net_device_stats *get_stats(struct net_device *dev);
761static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
762static int netdev_set_wol(struct net_device *dev, u32 newval);
763static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
764static int netdev_set_sopass(struct net_device *dev, u8 *newval);
765static int netdev_get_sopass(struct net_device *dev, u8 *data);
766static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
767static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
768static void enable_wol_mode(struct net_device *dev, int enable_intr);
769static int netdev_close(struct net_device *dev);
770static int netdev_get_regs(struct net_device *dev, u8 *buf);
771static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
772static struct ethtool_ops ethtool_ops;
773
774static inline void __iomem *ns_ioaddr(struct net_device *dev)
775{
776 return (void __iomem *) dev->base_addr;
777}
778
779static void move_int_phy(struct net_device *dev, int addr)
780{
781 struct netdev_private *np = netdev_priv(dev);
782 void __iomem *ioaddr = ns_ioaddr(dev);
783 int target = 31;
784
785 /*
786 * The internal phy is visible on the external mii bus. Therefore we must
787 * move it away before we can send commands to an external phy.
788 * There are two addresses we must avoid:
789 * - the address on the external phy that is used for transmission.
790 * - the address that we want to access. User space can access phys
791 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
792 * phy that is used for transmission.
793 */
794
795 if (target == addr)
796 target--;
797 if (target == np->phy_addr_external)
798 target--;
799 writew(target, ioaddr + PhyCtrl);
800 readw(ioaddr + PhyCtrl);
801 udelay(1);
802}
803
804static int __devinit natsemi_probe1 (struct pci_dev *pdev,
805 const struct pci_device_id *ent)
806{
807 struct net_device *dev;
808 struct netdev_private *np;
809 int i, option, irq, chip_idx = ent->driver_data;
810 static int find_cnt = -1;
811 unsigned long iostart, iosize;
812 void __iomem *ioaddr;
813 const int pcibar = 1; /* PCI base address register */
814 int prev_eedata;
815 u32 tmp;
816
817/* when built into the kernel, we only print version if device is found */
818#ifndef MODULE
819 static int printed_version;
820 if (!printed_version++)
821 printk(version);
822#endif
823
824 i = pci_enable_device(pdev);
825 if (i) return i;
826
827 /* natsemi has a non-standard PM control register
828 * in PCI config space. Some boards apparently need
829 * to be brought to D0 in this manner.
830 */
831 pci_read_config_dword(pdev, PCIPM, &tmp);
832 if (tmp & PCI_PM_CTRL_STATE_MASK) {
833 /* D0 state, disable PME assertion */
834 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
835 pci_write_config_dword(pdev, PCIPM, newtmp);
836 }
837
838 find_cnt++;
839 iostart = pci_resource_start(pdev, pcibar);
840 iosize = pci_resource_len(pdev, pcibar);
841 irq = pdev->irq;
842
843 if (natsemi_pci_info[chip_idx].flags & PCI_USES_MASTER)
844 pci_set_master(pdev);
845
846 dev = alloc_etherdev(sizeof (struct netdev_private));
847 if (!dev)
848 return -ENOMEM;
849 SET_MODULE_OWNER(dev);
850 SET_NETDEV_DEV(dev, &pdev->dev);
851
852 i = pci_request_regions(pdev, DRV_NAME);
853 if (i)
854 goto err_pci_request_regions;
855
856 ioaddr = ioremap(iostart, iosize);
857 if (!ioaddr) {
858 i = -ENOMEM;
859 goto err_ioremap;
860 }
861
862 /* Work around the dropped serial bit. */
863 prev_eedata = eeprom_read(ioaddr, 6);
864 for (i = 0; i < 3; i++) {
865 int eedata = eeprom_read(ioaddr, i + 7);
866 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
867 dev->dev_addr[i*2+1] = eedata >> 7;
868 prev_eedata = eedata;
869 }
870
871 dev->base_addr = (unsigned long __force) ioaddr;
872 dev->irq = irq;
873
874 np = netdev_priv(dev);
875
876 np->pci_dev = pdev;
877 pci_set_drvdata(pdev, dev);
878 np->iosize = iosize;
879 spin_lock_init(&np->lock);
880 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
881 np->hands_off = 0;
882
883 /* Initial port:
884 * - If the nic was configured to use an external phy and if find_mii
885 * finds a phy: use external port, first phy that replies.
886 * - Otherwise: internal port.
887 * Note that the phy address for the internal phy doesn't matter:
888 * The address would be used to access a phy over the mii bus, but
889 * the internal phy is accessed through mapped registers.
890 */
891 if (readl(ioaddr + ChipConfig) & CfgExtPhy)
892 dev->if_port = PORT_MII;
893 else
894 dev->if_port = PORT_TP;
895 /* Reset the chip to erase previous misconfiguration. */
896 natsemi_reload_eeprom(dev);
897 natsemi_reset(dev);
898
899 if (dev->if_port != PORT_TP) {
900 np->phy_addr_external = find_mii(dev);
901 if (np->phy_addr_external == PHY_ADDR_NONE) {
902 dev->if_port = PORT_TP;
903 np->phy_addr_external = PHY_ADDR_INTERNAL;
904 }
905 } else {
906 np->phy_addr_external = PHY_ADDR_INTERNAL;
907 }
908
909 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
910 if (dev->mem_start)
911 option = dev->mem_start;
912
913 /* The lower four bits are the media type. */
914 if (option) {
915 if (option & 0x200)
916 np->full_duplex = 1;
917 if (option & 15)
918 printk(KERN_INFO
919 "natsemi %s: ignoring user supplied media type %d",
920 pci_name(np->pci_dev), option & 15);
921 }
922 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
923 np->full_duplex = 1;
924
925 /* The chip-specific entries in the device structure. */
926 dev->open = &netdev_open;
927 dev->hard_start_xmit = &start_tx;
928 dev->stop = &netdev_close;
929 dev->get_stats = &get_stats;
930 dev->set_multicast_list = &set_rx_mode;
931 dev->change_mtu = &natsemi_change_mtu;
932 dev->do_ioctl = &netdev_ioctl;
933 dev->tx_timeout = &tx_timeout;
934 dev->watchdog_timeo = TX_TIMEOUT;
935#ifdef CONFIG_NET_POLL_CONTROLLER
936 dev->poll_controller = &natsemi_poll_controller;
937#endif
938 SET_ETHTOOL_OPS(dev, &ethtool_ops);
939
940 if (mtu)
941 dev->mtu = mtu;
942
943 netif_carrier_off(dev);
944
945 /* get the initial settings from hardware */
946 tmp = mdio_read(dev, MII_BMCR);
947 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
948 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
949 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
950 np->advertising= mdio_read(dev, MII_ADVERTISE);
951
952 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
953 && netif_msg_probe(np)) {
954 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
955 "10%s %s duplex.\n",
956 pci_name(np->pci_dev),
957 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
958 "enabled, advertise" : "disabled, force",
959 (np->advertising &
960 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
961 "0" : "",
962 (np->advertising &
963 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
964 "full" : "half");
965 }
966 if (netif_msg_probe(np))
967 printk(KERN_INFO
968 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
969 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
970 np->advertising);
971
972 /* save the silicon revision for later querying */
973 np->srr = readl(ioaddr + SiliconRev);
974 if (netif_msg_hw(np))
975 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
976 pci_name(np->pci_dev), np->srr);
977
978 i = register_netdev(dev);
979 if (i)
980 goto err_register_netdev;
981
982 if (netif_msg_drv(np)) {
983 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
984 dev->name, natsemi_pci_info[chip_idx].name, iostart,
985 pci_name(np->pci_dev));
986 for (i = 0; i < ETH_ALEN-1; i++)
987 printk("%02x:", dev->dev_addr[i]);
988 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
989 if (dev->if_port == PORT_TP)
990 printk(", port TP.\n");
991 else
992 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
993 }
994 return 0;
995
996 err_register_netdev:
997 iounmap(ioaddr);
998
999 err_ioremap:
1000 pci_release_regions(pdev);
1001 pci_set_drvdata(pdev, NULL);
1002
1003 err_pci_request_regions:
1004 free_netdev(dev);
1005 return i;
1006}
1007
1008
1009/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
1010 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
1011
1012/* Delay between EEPROM clock transitions.
1013 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
1014 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
1015 made udelay() unreliable.
1016 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1017 depricated.
1018*/
1019#define eeprom_delay(ee_addr) readl(ee_addr)
1020
1021#define EE_Write0 (EE_ChipSelect)
1022#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1023
1024/* The EEPROM commands include the alway-set leading bit. */
1025enum EEPROM_Cmds {
1026 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1027};
1028
1029static int eeprom_read(void __iomem *addr, int location)
1030{
1031 int i;
1032 int retval = 0;
1033 void __iomem *ee_addr = addr + EECtrl;
1034 int read_cmd = location | EE_ReadCmd;
1035
1036 writel(EE_Write0, ee_addr);
1037
1038 /* Shift the read command bits out. */
1039 for (i = 10; i >= 0; i--) {
1040 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1041 writel(dataval, ee_addr);
1042 eeprom_delay(ee_addr);
1043 writel(dataval | EE_ShiftClk, ee_addr);
1044 eeprom_delay(ee_addr);
1045 }
1046 writel(EE_ChipSelect, ee_addr);
1047 eeprom_delay(ee_addr);
1048
1049 for (i = 0; i < 16; i++) {
1050 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1051 eeprom_delay(ee_addr);
1052 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1053 writel(EE_ChipSelect, ee_addr);
1054 eeprom_delay(ee_addr);
1055 }
1056
1057 /* Terminate the EEPROM access. */
1058 writel(EE_Write0, ee_addr);
1059 writel(0, ee_addr);
1060 return retval;
1061}
1062
1063/* MII transceiver control section.
1064 * The 83815 series has an internal transceiver, and we present the
1065 * internal management registers as if they were MII connected.
1066 * External Phy registers are referenced through the MII interface.
1067 */
1068
1069/* clock transitions >= 20ns (25MHz)
1070 * One readl should be good to PCI @ 100MHz
1071 */
1072#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1073
1074static int mii_getbit (struct net_device *dev)
1075{
1076 int data;
1077 void __iomem *ioaddr = ns_ioaddr(dev);
1078
1079 writel(MII_ShiftClk, ioaddr + EECtrl);
1080 data = readl(ioaddr + EECtrl);
1081 writel(0, ioaddr + EECtrl);
1082 mii_delay(ioaddr);
1083 return (data & MII_Data)? 1 : 0;
1084}
1085
1086static void mii_send_bits (struct net_device *dev, u32 data, int len)
1087{
1088 u32 i;
1089 void __iomem *ioaddr = ns_ioaddr(dev);
1090
1091 for (i = (1 << (len-1)); i; i >>= 1)
1092 {
1093 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1094 writel(mdio_val, ioaddr + EECtrl);
1095 mii_delay(ioaddr);
1096 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1097 mii_delay(ioaddr);
1098 }
1099 writel(0, ioaddr + EECtrl);
1100 mii_delay(ioaddr);
1101}
1102
1103static int miiport_read(struct net_device *dev, int phy_id, int reg)
1104{
1105 u32 cmd;
1106 int i;
1107 u32 retval = 0;
1108
1109 /* Ensure sync */
1110 mii_send_bits (dev, 0xffffffff, 32);
1111 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1112 /* ST,OP = 0110'b for read operation */
1113 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1114 mii_send_bits (dev, cmd, 14);
1115 /* Turnaround */
1116 if (mii_getbit (dev))
1117 return 0;
1118 /* Read data */
1119 for (i = 0; i < 16; i++) {
1120 retval <<= 1;
1121 retval |= mii_getbit (dev);
1122 }
1123 /* End cycle */
1124 mii_getbit (dev);
1125 return retval;
1126}
1127
1128static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1129{
1130 u32 cmd;
1131
1132 /* Ensure sync */
1133 mii_send_bits (dev, 0xffffffff, 32);
1134 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1135 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1136 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1137 mii_send_bits (dev, cmd, 32);
1138 /* End cycle */
1139 mii_getbit (dev);
1140}
1141
1142static int mdio_read(struct net_device *dev, int reg)
1143{
1144 struct netdev_private *np = netdev_priv(dev);
1145 void __iomem *ioaddr = ns_ioaddr(dev);
1146
1147 /* The 83815 series has two ports:
1148 * - an internal transceiver
1149 * - an external mii bus
1150 */
1151 if (dev->if_port == PORT_TP)
1152 return readw(ioaddr+BasicControl+(reg<<2));
1153 else
1154 return miiport_read(dev, np->phy_addr_external, reg);
1155}
1156
1157static void mdio_write(struct net_device *dev, int reg, u16 data)
1158{
1159 struct netdev_private *np = netdev_priv(dev);
1160 void __iomem *ioaddr = ns_ioaddr(dev);
1161
1162 /* The 83815 series has an internal transceiver; handle separately */
1163 if (dev->if_port == PORT_TP)
1164 writew(data, ioaddr+BasicControl+(reg<<2));
1165 else
1166 miiport_write(dev, np->phy_addr_external, reg, data);
1167}
1168
1169static void init_phy_fixup(struct net_device *dev)
1170{
1171 struct netdev_private *np = netdev_priv(dev);
1172 void __iomem *ioaddr = ns_ioaddr(dev);
1173 int i;
1174 u32 cfg;
1175 u16 tmp;
1176
1177 /* restore stuff lost when power was out */
1178 tmp = mdio_read(dev, MII_BMCR);
1179 if (np->autoneg == AUTONEG_ENABLE) {
1180 /* renegotiate if something changed */
1181 if ((tmp & BMCR_ANENABLE) == 0
1182 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1183 {
1184 /* turn on autonegotiation and force negotiation */
1185 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1186 mdio_write(dev, MII_ADVERTISE, np->advertising);
1187 }
1188 } else {
1189 /* turn off auto negotiation, set speed and duplexity */
1190 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1191 if (np->speed == SPEED_100)
1192 tmp |= BMCR_SPEED100;
1193 if (np->duplex == DUPLEX_FULL)
1194 tmp |= BMCR_FULLDPLX;
1195 /*
1196 * Note: there is no good way to inform the link partner
1197 * that our capabilities changed. The user has to unplug
1198 * and replug the network cable after some changes, e.g.
1199 * after switching from 10HD, autoneg off to 100 HD,
1200 * autoneg off.
1201 */
1202 }
1203 mdio_write(dev, MII_BMCR, tmp);
1204 readl(ioaddr + ChipConfig);
1205 udelay(1);
1206
1207 /* find out what phy this is */
1208 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1209 + mdio_read(dev, MII_PHYSID2);
1210
1211 /* handle external phys here */
1212 switch (np->mii) {
1213 case PHYID_AM79C874:
1214 /* phy specific configuration for fibre/tp operation */
1215 tmp = mdio_read(dev, MII_MCTRL);
1216 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1217 if (dev->if_port == PORT_FIBRE)
1218 tmp |= MII_FX_SEL;
1219 else
1220 tmp |= MII_EN_SCRM;
1221 mdio_write(dev, MII_MCTRL, tmp);
1222 break;
1223 default:
1224 break;
1225 }
1226 cfg = readl(ioaddr + ChipConfig);
1227 if (cfg & CfgExtPhy)
1228 return;
1229
1230 /* On page 78 of the spec, they recommend some settings for "optimum
1231 performance" to be done in sequence. These settings optimize some
1232 of the 100Mbit autodetection circuitry. They say we only want to
1233 do this for rev C of the chip, but engineers at NSC (Bradley
1234 Kennedy) recommends always setting them. If you don't, you get
1235 errors on some autonegotiations that make the device unusable.
1236
1237 It seems that the DSP needs a few usec to reinitialize after
1238 the start of the phy. Just retry writing these values until they
1239 stick.
1240 */
1241 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1242
1243 int dspcfg;
1244 writew(1, ioaddr + PGSEL);
1245 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1246 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1247 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1248 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1249 writew(np->dspcfg, ioaddr + DSPCFG);
1250 writew(SDCFG_VAL, ioaddr + SDCFG);
1251 writew(0, ioaddr + PGSEL);
1252 readl(ioaddr + ChipConfig);
1253 udelay(10);
1254
1255 writew(1, ioaddr + PGSEL);
1256 dspcfg = readw(ioaddr + DSPCFG);
1257 writew(0, ioaddr + PGSEL);
1258 if (np->dspcfg == dspcfg)
1259 break;
1260 }
1261
1262 if (netif_msg_link(np)) {
1263 if (i==NATSEMI_HW_TIMEOUT) {
1264 printk(KERN_INFO
1265 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1266 dev->name, i*10);
1267 } else {
1268 printk(KERN_INFO
1269 "%s: DSPCFG accepted after %d usec.\n",
1270 dev->name, i*10);
1271 }
1272 }
1273 /*
1274 * Enable PHY Specific event based interrupts. Link state change
1275 * and Auto-Negotiation Completion are among the affected.
1276 * Read the intr status to clear it (needed for wake events).
1277 */
1278 readw(ioaddr + MIntrStatus);
1279 writew(MICRIntEn, ioaddr + MIntrCtrl);
1280}
1281
1282static int switch_port_external(struct net_device *dev)
1283{
1284 struct netdev_private *np = netdev_priv(dev);
1285 void __iomem *ioaddr = ns_ioaddr(dev);
1286 u32 cfg;
1287
1288 cfg = readl(ioaddr + ChipConfig);
1289 if (cfg & CfgExtPhy)
1290 return 0;
1291
1292 if (netif_msg_link(np)) {
1293 printk(KERN_INFO "%s: switching to external transceiver.\n",
1294 dev->name);
1295 }
1296
1297 /* 1) switch back to external phy */
1298 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1299 readl(ioaddr + ChipConfig);
1300 udelay(1);
1301
1302 /* 2) reset the external phy: */
1303 /* resetting the external PHY has been known to cause a hub supplying
1304 * power over Ethernet to kill the power. We don't want to kill
1305 * power to this computer, so we avoid resetting the phy.
1306 */
1307
1308 /* 3) reinit the phy fixup, it got lost during power down. */
1309 move_int_phy(dev, np->phy_addr_external);
1310 init_phy_fixup(dev);
1311
1312 return 1;
1313}
1314
1315static int switch_port_internal(struct net_device *dev)
1316{
1317 struct netdev_private *np = netdev_priv(dev);
1318 void __iomem *ioaddr = ns_ioaddr(dev);
1319 int i;
1320 u32 cfg;
1321 u16 bmcr;
1322
1323 cfg = readl(ioaddr + ChipConfig);
1324 if (!(cfg &CfgExtPhy))
1325 return 0;
1326
1327 if (netif_msg_link(np)) {
1328 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1329 dev->name);
1330 }
1331 /* 1) switch back to internal phy: */
1332 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1333 writel(cfg, ioaddr + ChipConfig);
1334 readl(ioaddr + ChipConfig);
1335 udelay(1);
1336
1337 /* 2) reset the internal phy: */
1338 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1339 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1340 readl(ioaddr + ChipConfig);
1341 udelay(10);
1342 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1343 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1344 if (!(bmcr & BMCR_RESET))
1345 break;
1346 udelay(10);
1347 }
1348 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1349 printk(KERN_INFO
1350 "%s: phy reset did not complete in %d usec.\n",
1351 dev->name, i*10);
1352 }
1353 /* 3) reinit the phy fixup, it got lost during power down. */
1354 init_phy_fixup(dev);
1355
1356 return 1;
1357}
1358
1359/* Scan for a PHY on the external mii bus.
1360 * There are two tricky points:
1361 * - Do not scan while the internal phy is enabled. The internal phy will
1362 * crash: e.g. reads from the DSPCFG register will return odd values and
1363 * the nasty random phy reset code will reset the nic every few seconds.
1364 * - The internal phy must be moved around, an external phy could
1365 * have the same address as the internal phy.
1366 */
1367static int find_mii(struct net_device *dev)
1368{
1369 struct netdev_private *np = netdev_priv(dev);
1370 int tmp;
1371 int i;
1372 int did_switch;
1373
1374 /* Switch to external phy */
1375 did_switch = switch_port_external(dev);
1376
1377 /* Scan the possible phy addresses:
1378 *
1379 * PHY address 0 means that the phy is in isolate mode. Not yet
1380 * supported due to lack of test hardware. User space should
1381 * handle it through ethtool.
1382 */
1383 for (i = 1; i <= 31; i++) {
1384 move_int_phy(dev, i);
1385 tmp = miiport_read(dev, i, MII_BMSR);
1386 if (tmp != 0xffff && tmp != 0x0000) {
1387 /* found something! */
1388 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1389 + mdio_read(dev, MII_PHYSID2);
1390 if (netif_msg_probe(np)) {
1391 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1392 pci_name(np->pci_dev), np->mii, i);
1393 }
1394 break;
1395 }
1396 }
1397 /* And switch back to internal phy: */
1398 if (did_switch)
1399 switch_port_internal(dev);
1400 return i;
1401}
1402
1403/* CFG bits [13:16] [18:23] */
1404#define CFG_RESET_SAVE 0xfde000
1405/* WCSR bits [0:4] [9:10] */
1406#define WCSR_RESET_SAVE 0x61f
1407/* RFCR bits [20] [22] [27:31] */
1408#define RFCR_RESET_SAVE 0xf8500000;
1409
1410static void natsemi_reset(struct net_device *dev)
1411{
1412 int i;
1413 u32 cfg;
1414 u32 wcsr;
1415 u32 rfcr;
1416 u16 pmatch[3];
1417 u16 sopass[3];
1418 struct netdev_private *np = netdev_priv(dev);
1419 void __iomem *ioaddr = ns_ioaddr(dev);
1420
1421 /*
1422 * Resetting the chip causes some registers to be lost.
1423 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1424 * we save the state that would have been loaded from EEPROM
1425 * on a normal power-up (see the spec EEPROM map). This assumes
1426 * whoever calls this will follow up with init_registers() eventually.
1427 */
1428
1429 /* CFG */
1430 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1431 /* WCSR */
1432 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1433 /* RFCR */
1434 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1435 /* PMATCH */
1436 for (i = 0; i < 3; i++) {
1437 writel(i*2, ioaddr + RxFilterAddr);
1438 pmatch[i] = readw(ioaddr + RxFilterData);
1439 }
1440 /* SOPAS */
1441 for (i = 0; i < 3; i++) {
1442 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1443 sopass[i] = readw(ioaddr + RxFilterData);
1444 }
1445
1446 /* now whack the chip */
1447 writel(ChipReset, ioaddr + ChipCmd);
1448 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1449 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1450 break;
1451 udelay(5);
1452 }
1453 if (i==NATSEMI_HW_TIMEOUT) {
1454 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1455 dev->name, i*5);
1456 } else if (netif_msg_hw(np)) {
1457 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1458 dev->name, i*5);
1459 }
1460
1461 /* restore CFG */
1462 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1463 /* turn on external phy if it was selected */
1464 if (dev->if_port == PORT_TP)
1465 cfg &= ~(CfgExtPhy | CfgPhyDis);
1466 else
1467 cfg |= (CfgExtPhy | CfgPhyDis);
1468 writel(cfg, ioaddr + ChipConfig);
1469 /* restore WCSR */
1470 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1471 writel(wcsr, ioaddr + WOLCmd);
1472 /* read RFCR */
1473 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1474 /* restore PMATCH */
1475 for (i = 0; i < 3; i++) {
1476 writel(i*2, ioaddr + RxFilterAddr);
1477 writew(pmatch[i], ioaddr + RxFilterData);
1478 }
1479 for (i = 0; i < 3; i++) {
1480 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1481 writew(sopass[i], ioaddr + RxFilterData);
1482 }
1483 /* restore RFCR */
1484 writel(rfcr, ioaddr + RxFilterAddr);
1485}
1486
1487static void natsemi_reload_eeprom(struct net_device *dev)
1488{
1489 struct netdev_private *np = netdev_priv(dev);
1490 void __iomem *ioaddr = ns_ioaddr(dev);
1491 int i;
1492
1493 writel(EepromReload, ioaddr + PCIBusCfg);
1494 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1495 udelay(50);
1496 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1497 break;
1498 }
1499 if (i==NATSEMI_HW_TIMEOUT) {
1500 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1501 pci_name(np->pci_dev), i*50);
1502 } else if (netif_msg_hw(np)) {
1503 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1504 pci_name(np->pci_dev), i*50);
1505 }
1506}
1507
1508static void natsemi_stop_rxtx(struct net_device *dev)
1509{
1510 void __iomem * ioaddr = ns_ioaddr(dev);
1511 struct netdev_private *np = netdev_priv(dev);
1512 int i;
1513
1514 writel(RxOff | TxOff, ioaddr + ChipCmd);
1515 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1516 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1517 break;
1518 udelay(5);
1519 }
1520 if (i==NATSEMI_HW_TIMEOUT) {
1521 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1522 dev->name, i*5);
1523 } else if (netif_msg_hw(np)) {
1524 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1525 dev->name, i*5);
1526 }
1527}
1528
1529static int netdev_open(struct net_device *dev)
1530{
1531 struct netdev_private *np = netdev_priv(dev);
1532 void __iomem * ioaddr = ns_ioaddr(dev);
1533 int i;
1534
1535 /* Reset the chip, just in case. */
1536 natsemi_reset(dev);
1537
1538 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
1539 if (i) return i;
1540
1541 if (netif_msg_ifup(np))
1542 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1543 dev->name, dev->irq);
1544 i = alloc_ring(dev);
1545 if (i < 0) {
1546 free_irq(dev->irq, dev);
1547 return i;
1548 }
1549 init_ring(dev);
1550 spin_lock_irq(&np->lock);
1551 init_registers(dev);
1552 /* now set the MAC address according to dev->dev_addr */
1553 for (i = 0; i < 3; i++) {
1554 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1555
1556 writel(i*2, ioaddr + RxFilterAddr);
1557 writew(mac, ioaddr + RxFilterData);
1558 }
1559 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1560 spin_unlock_irq(&np->lock);
1561
1562 netif_start_queue(dev);
1563
1564 if (netif_msg_ifup(np))
1565 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1566 dev->name, (int)readl(ioaddr + ChipCmd));
1567
1568 /* Set the timer to check for link beat. */
1569 init_timer(&np->timer);
1570 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1571 np->timer.data = (unsigned long)dev;
1572 np->timer.function = &netdev_timer; /* timer handler */
1573 add_timer(&np->timer);
1574
1575 return 0;
1576}
1577
1578static void do_cable_magic(struct net_device *dev)
1579{
1580 struct netdev_private *np = netdev_priv(dev);
1581 void __iomem *ioaddr = ns_ioaddr(dev);
1582
1583 if (dev->if_port != PORT_TP)
1584 return;
1585
1586 if (np->srr >= SRR_DP83816_A5)
1587 return;
1588
1589 /*
1590 * 100 MBit links with short cables can trip an issue with the chip.
1591 * The problem manifests as lots of CRC errors and/or flickering
1592 * activity LED while idle. This process is based on instructions
1593 * from engineers at National.
1594 */
1595 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1596 u16 data;
1597
1598 writew(1, ioaddr + PGSEL);
1599 /*
1600 * coefficient visibility should already be enabled via
1601 * DSPCFG | 0x1000
1602 */
1603 data = readw(ioaddr + TSTDAT) & 0xff;
1604 /*
1605 * the value must be negative, and within certain values
1606 * (these values all come from National)
1607 */
1608 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1609 struct netdev_private *np = netdev_priv(dev);
1610
1611 /* the bug has been triggered - fix the coefficient */
1612 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1613 /* lock the value */
1614 data = readw(ioaddr + DSPCFG);
1615 np->dspcfg = data | DSPCFG_LOCK;
1616 writew(np->dspcfg, ioaddr + DSPCFG);
1617 }
1618 writew(0, ioaddr + PGSEL);
1619 }
1620}
1621
1622static void undo_cable_magic(struct net_device *dev)
1623{
1624 u16 data;
1625 struct netdev_private *np = netdev_priv(dev);
1626 void __iomem * ioaddr = ns_ioaddr(dev);
1627
1628 if (dev->if_port != PORT_TP)
1629 return;
1630
1631 if (np->srr >= SRR_DP83816_A5)
1632 return;
1633
1634 writew(1, ioaddr + PGSEL);
1635 /* make sure the lock bit is clear */
1636 data = readw(ioaddr + DSPCFG);
1637 np->dspcfg = data & ~DSPCFG_LOCK;
1638 writew(np->dspcfg, ioaddr + DSPCFG);
1639 writew(0, ioaddr + PGSEL);
1640}
1641
1642static void check_link(struct net_device *dev)
1643{
1644 struct netdev_private *np = netdev_priv(dev);
1645 void __iomem * ioaddr = ns_ioaddr(dev);
1646 int duplex;
1647 u16 bmsr;
1648
1649 /* The link status field is latched: it remains low after a temporary
1650 * link failure until it's read. We need the current link status,
1651 * thus read twice.
1652 */
1653 mdio_read(dev, MII_BMSR);
1654 bmsr = mdio_read(dev, MII_BMSR);
1655
1656 if (!(bmsr & BMSR_LSTATUS)) {
1657 if (netif_carrier_ok(dev)) {
1658 if (netif_msg_link(np))
1659 printk(KERN_NOTICE "%s: link down.\n",
1660 dev->name);
1661 netif_carrier_off(dev);
1662 undo_cable_magic(dev);
1663 }
1664 return;
1665 }
1666 if (!netif_carrier_ok(dev)) {
1667 if (netif_msg_link(np))
1668 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1669 netif_carrier_on(dev);
1670 do_cable_magic(dev);
1671 }
1672
1673 duplex = np->full_duplex;
1674 if (!duplex) {
1675 if (bmsr & BMSR_ANEGCOMPLETE) {
1676 int tmp = mii_nway_result(
1677 np->advertising & mdio_read(dev, MII_LPA));
1678 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1679 duplex = 1;
1680 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1681 duplex = 1;
1682 }
1683
1684 /* if duplex is set then bit 28 must be set, too */
1685 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1686 if (netif_msg_link(np))
1687 printk(KERN_INFO
1688 "%s: Setting %s-duplex based on negotiated "
1689 "link capability.\n", dev->name,
1690 duplex ? "full" : "half");
1691 if (duplex) {
1692 np->rx_config |= RxAcceptTx;
1693 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1694 } else {
1695 np->rx_config &= ~RxAcceptTx;
1696 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1697 }
1698 writel(np->tx_config, ioaddr + TxConfig);
1699 writel(np->rx_config, ioaddr + RxConfig);
1700 }
1701}
1702
1703static void init_registers(struct net_device *dev)
1704{
1705 struct netdev_private *np = netdev_priv(dev);
1706 void __iomem * ioaddr = ns_ioaddr(dev);
1707
1708 init_phy_fixup(dev);
1709
1710 /* clear any interrupts that are pending, such as wake events */
1711 readl(ioaddr + IntrStatus);
1712
1713 writel(np->ring_dma, ioaddr + RxRingPtr);
1714 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1715 ioaddr + TxRingPtr);
1716
1717 /* Initialize other registers.
1718 * Configure the PCI bus bursts and FIFO thresholds.
1719 * Configure for standard, in-spec Ethernet.
1720 * Start with half-duplex. check_link will update
1721 * to the correct settings.
1722 */
1723
1724 /* DRTH: 2: start tx if 64 bytes are in the fifo
1725 * FLTH: 0x10: refill with next packet if 512 bytes are free
1726 * MXDMA: 0: up to 256 byte bursts.
1727 * MXDMA must be <= FLTH
1728 * ECRETRY=1
1729 * ATP=1
1730 */
1731 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1732 TX_FLTH_VAL | TX_DRTH_VAL_START;
1733 writel(np->tx_config, ioaddr + TxConfig);
1734
1735 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1736 * MXDMA 0: up to 256 byte bursts
1737 */
1738 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1739 /* if receive ring now has bigger buffers than normal, enable jumbo */
1740 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1741 np->rx_config |= RxAcceptLong;
1742
1743 writel(np->rx_config, ioaddr + RxConfig);
1744
1745 /* Disable PME:
1746 * The PME bit is initialized from the EEPROM contents.
1747 * PCI cards probably have PME disabled, but motherboard
1748 * implementations may have PME set to enable WakeOnLan.
1749 * With PME set the chip will scan incoming packets but
1750 * nothing will be written to memory. */
1751 np->SavedClkRun = readl(ioaddr + ClkRun);
1752 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1753 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1754 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1755 dev->name, readl(ioaddr + WOLCmd));
1756 }
1757
1758 check_link(dev);
1759 __set_rx_mode(dev);
1760
1761 /* Enable interrupts by setting the interrupt mask. */
1762 writel(DEFAULT_INTR, ioaddr + IntrMask);
1763 writel(1, ioaddr + IntrEnable);
1764
1765 writel(RxOn | TxOn, ioaddr + ChipCmd);
1766 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1767}
1768
1769/*
1770 * netdev_timer:
1771 * Purpose:
1772 * 1) check for link changes. Usually they are handled by the MII interrupt
1773 * but it doesn't hurt to check twice.
1774 * 2) check for sudden death of the NIC:
1775 * It seems that a reference set for this chip went out with incorrect info,
1776 * and there exist boards that aren't quite right. An unexpected voltage
1777 * drop can cause the PHY to get itself in a weird state (basically reset).
1778 * NOTE: this only seems to affect revC chips.
1779 * 3) check of death of the RX path due to OOM
1780 */
1781static void netdev_timer(unsigned long data)
1782{
1783 struct net_device *dev = (struct net_device *)data;
1784 struct netdev_private *np = netdev_priv(dev);
1785 void __iomem * ioaddr = ns_ioaddr(dev);
1786 int next_tick = 5*HZ;
1787
1788 if (netif_msg_timer(np)) {
1789 /* DO NOT read the IntrStatus register,
1790 * a read clears any pending interrupts.
1791 */
1792 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1793 dev->name);
1794 }
1795
1796 if (dev->if_port == PORT_TP) {
1797 u16 dspcfg;
1798
1799 spin_lock_irq(&np->lock);
1800 /* check for a nasty random phy-reset - use dspcfg as a flag */
1801 writew(1, ioaddr+PGSEL);
1802 dspcfg = readw(ioaddr+DSPCFG);
1803 writew(0, ioaddr+PGSEL);
1804 if (dspcfg != np->dspcfg) {
1805 if (!netif_queue_stopped(dev)) {
1806 spin_unlock_irq(&np->lock);
1807 if (netif_msg_hw(np))
1808 printk(KERN_NOTICE "%s: possible phy reset: "
1809 "re-initializing\n", dev->name);
1810 disable_irq(dev->irq);
1811 spin_lock_irq(&np->lock);
1812 natsemi_stop_rxtx(dev);
1813 dump_ring(dev);
1814 reinit_ring(dev);
1815 init_registers(dev);
1816 spin_unlock_irq(&np->lock);
1817 enable_irq(dev->irq);
1818 } else {
1819 /* hurry back */
1820 next_tick = HZ;
1821 spin_unlock_irq(&np->lock);
1822 }
1823 } else {
1824 /* init_registers() calls check_link() for the above case */
1825 check_link(dev);
1826 spin_unlock_irq(&np->lock);
1827 }
1828 } else {
1829 spin_lock_irq(&np->lock);
1830 check_link(dev);
1831 spin_unlock_irq(&np->lock);
1832 }
1833 if (np->oom) {
1834 disable_irq(dev->irq);
1835 np->oom = 0;
1836 refill_rx(dev);
1837 enable_irq(dev->irq);
1838 if (!np->oom) {
1839 writel(RxOn, ioaddr + ChipCmd);
1840 } else {
1841 next_tick = 1;
1842 }
1843 }
1844 mod_timer(&np->timer, jiffies + next_tick);
1845}
1846
1847static void dump_ring(struct net_device *dev)
1848{
1849 struct netdev_private *np = netdev_priv(dev);
1850
1851 if (netif_msg_pktdata(np)) {
1852 int i;
1853 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1854 for (i = 0; i < TX_RING_SIZE; i++) {
1855 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1856 i, np->tx_ring[i].next_desc,
1857 np->tx_ring[i].cmd_status,
1858 np->tx_ring[i].addr);
1859 }
1860 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1861 for (i = 0; i < RX_RING_SIZE; i++) {
1862 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1863 i, np->rx_ring[i].next_desc,
1864 np->rx_ring[i].cmd_status,
1865 np->rx_ring[i].addr);
1866 }
1867 }
1868}
1869
1870static void tx_timeout(struct net_device *dev)
1871{
1872 struct netdev_private *np = netdev_priv(dev);
1873 void __iomem * ioaddr = ns_ioaddr(dev);
1874
1875 disable_irq(dev->irq);
1876 spin_lock_irq(&np->lock);
1877 if (!np->hands_off) {
1878 if (netif_msg_tx_err(np))
1879 printk(KERN_WARNING
1880 "%s: Transmit timed out, status %#08x,"
1881 " resetting...\n",
1882 dev->name, readl(ioaddr + IntrStatus));
1883 dump_ring(dev);
1884
1885 natsemi_reset(dev);
1886 reinit_ring(dev);
1887 init_registers(dev);
1888 } else {
1889 printk(KERN_WARNING
1890 "%s: tx_timeout while in hands_off state?\n",
1891 dev->name);
1892 }
1893 spin_unlock_irq(&np->lock);
1894 enable_irq(dev->irq);
1895
1896 dev->trans_start = jiffies;
1897 np->stats.tx_errors++;
1898 netif_wake_queue(dev);
1899}
1900
1901static int alloc_ring(struct net_device *dev)
1902{
1903 struct netdev_private *np = netdev_priv(dev);
1904 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1905 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1906 &np->ring_dma);
1907 if (!np->rx_ring)
1908 return -ENOMEM;
1909 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1910 return 0;
1911}
1912
1913static void refill_rx(struct net_device *dev)
1914{
1915 struct netdev_private *np = netdev_priv(dev);
1916
1917 /* Refill the Rx ring buffers. */
1918 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1919 struct sk_buff *skb;
1920 int entry = np->dirty_rx % RX_RING_SIZE;
1921 if (np->rx_skbuff[entry] == NULL) {
1922 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1923 skb = dev_alloc_skb(buflen);
1924 np->rx_skbuff[entry] = skb;
1925 if (skb == NULL)
1926 break; /* Better luck next round. */
1927 skb->dev = dev; /* Mark as being used by this device. */
1928 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1929 skb->tail, buflen, PCI_DMA_FROMDEVICE);
1930 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1931 }
1932 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1933 }
1934 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1935 if (netif_msg_rx_err(np))
1936 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1937 np->oom = 1;
1938 }
1939}
1940
1941static void set_bufsize(struct net_device *dev)
1942{
1943 struct netdev_private *np = netdev_priv(dev);
1944 if (dev->mtu <= ETH_DATA_LEN)
1945 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1946 else
1947 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1948}
1949
1950/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1951static void init_ring(struct net_device *dev)
1952{
1953 struct netdev_private *np = netdev_priv(dev);
1954 int i;
1955
1956 /* 1) TX ring */
1957 np->dirty_tx = np->cur_tx = 0;
1958 for (i = 0; i < TX_RING_SIZE; i++) {
1959 np->tx_skbuff[i] = NULL;
1960 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1961 +sizeof(struct netdev_desc)
1962 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1963 np->tx_ring[i].cmd_status = 0;
1964 }
1965
1966 /* 2) RX ring */
1967 np->dirty_rx = 0;
1968 np->cur_rx = RX_RING_SIZE;
1969 np->oom = 0;
1970 set_bufsize(dev);
1971
1972 np->rx_head_desc = &np->rx_ring[0];
1973
1974 /* Please be carefull before changing this loop - at least gcc-2.95.1
1975 * miscompiles it otherwise.
1976 */
1977 /* Initialize all Rx descriptors. */
1978 for (i = 0; i < RX_RING_SIZE; i++) {
1979 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1980 +sizeof(struct netdev_desc)
1981 *((i+1)%RX_RING_SIZE));
1982 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1983 np->rx_skbuff[i] = NULL;
1984 }
1985 refill_rx(dev);
1986 dump_ring(dev);
1987}
1988
1989static void drain_tx(struct net_device *dev)
1990{
1991 struct netdev_private *np = netdev_priv(dev);
1992 int i;
1993
1994 for (i = 0; i < TX_RING_SIZE; i++) {
1995 if (np->tx_skbuff[i]) {
1996 pci_unmap_single(np->pci_dev,
1997 np->tx_dma[i], np->tx_skbuff[i]->len,
1998 PCI_DMA_TODEVICE);
1999 dev_kfree_skb(np->tx_skbuff[i]);
2000 np->stats.tx_dropped++;
2001 }
2002 np->tx_skbuff[i] = NULL;
2003 }
2004}
2005
2006static void drain_rx(struct net_device *dev)
2007{
2008 struct netdev_private *np = netdev_priv(dev);
2009 unsigned int buflen = np->rx_buf_sz;
2010 int i;
2011
2012 /* Free all the skbuffs in the Rx queue. */
2013 for (i = 0; i < RX_RING_SIZE; i++) {
2014 np->rx_ring[i].cmd_status = 0;
2015 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2016 if (np->rx_skbuff[i]) {
2017 pci_unmap_single(np->pci_dev,
2018 np->rx_dma[i], buflen,
2019 PCI_DMA_FROMDEVICE);
2020 dev_kfree_skb(np->rx_skbuff[i]);
2021 }
2022 np->rx_skbuff[i] = NULL;
2023 }
2024}
2025
2026static void drain_ring(struct net_device *dev)
2027{
2028 drain_rx(dev);
2029 drain_tx(dev);
2030}
2031
2032static void free_ring(struct net_device *dev)
2033{
2034 struct netdev_private *np = netdev_priv(dev);
2035 pci_free_consistent(np->pci_dev,
2036 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2037 np->rx_ring, np->ring_dma);
2038}
2039
2040static void reinit_rx(struct net_device *dev)
2041{
2042 struct netdev_private *np = netdev_priv(dev);
2043 int i;
2044
2045 /* RX Ring */
2046 np->dirty_rx = 0;
2047 np->cur_rx = RX_RING_SIZE;
2048 np->rx_head_desc = &np->rx_ring[0];
2049 /* Initialize all Rx descriptors. */
2050 for (i = 0; i < RX_RING_SIZE; i++)
2051 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2052
2053 refill_rx(dev);
2054}
2055
2056static void reinit_ring(struct net_device *dev)
2057{
2058 struct netdev_private *np = netdev_priv(dev);
2059 int i;
2060
2061 /* drain TX ring */
2062 drain_tx(dev);
2063 np->dirty_tx = np->cur_tx = 0;
2064 for (i=0;i<TX_RING_SIZE;i++)
2065 np->tx_ring[i].cmd_status = 0;
2066
2067 reinit_rx(dev);
2068}
2069
2070static int start_tx(struct sk_buff *skb, struct net_device *dev)
2071{
2072 struct netdev_private *np = netdev_priv(dev);
2073 void __iomem * ioaddr = ns_ioaddr(dev);
2074 unsigned entry;
2075
2076 /* Note: Ordering is important here, set the field with the
2077 "ownership" bit last, and only then increment cur_tx. */
2078
2079 /* Calculate the next Tx descriptor entry. */
2080 entry = np->cur_tx % TX_RING_SIZE;
2081
2082 np->tx_skbuff[entry] = skb;
2083 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2084 skb->data,skb->len, PCI_DMA_TODEVICE);
2085
2086 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2087
2088 spin_lock_irq(&np->lock);
2089
2090 if (!np->hands_off) {
2091 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2092 /* StrongARM: Explicitly cache flush np->tx_ring and
2093 * skb->data,skb->len. */
2094 wmb();
2095 np->cur_tx++;
2096 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2097 netdev_tx_done(dev);
2098 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2099 netif_stop_queue(dev);
2100 }
2101 /* Wake the potentially-idle transmit channel. */
2102 writel(TxOn, ioaddr + ChipCmd);
2103 } else {
2104 dev_kfree_skb_irq(skb);
2105 np->stats.tx_dropped++;
2106 }
2107 spin_unlock_irq(&np->lock);
2108
2109 dev->trans_start = jiffies;
2110
2111 if (netif_msg_tx_queued(np)) {
2112 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2113 dev->name, np->cur_tx, entry);
2114 }
2115 return 0;
2116}
2117
2118static void netdev_tx_done(struct net_device *dev)
2119{
2120 struct netdev_private *np = netdev_priv(dev);
2121
2122 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2123 int entry = np->dirty_tx % TX_RING_SIZE;
2124 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2125 break;
2126 if (netif_msg_tx_done(np))
2127 printk(KERN_DEBUG
2128 "%s: tx frame #%d finished, status %#08x.\n",
2129 dev->name, np->dirty_tx,
2130 le32_to_cpu(np->tx_ring[entry].cmd_status));
2131 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2132 np->stats.tx_packets++;
2133 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2134 } else { /* Various Tx errors */
2135 int tx_status =
2136 le32_to_cpu(np->tx_ring[entry].cmd_status);
2137 if (tx_status & (DescTxAbort|DescTxExcColl))
2138 np->stats.tx_aborted_errors++;
2139 if (tx_status & DescTxFIFO)
2140 np->stats.tx_fifo_errors++;
2141 if (tx_status & DescTxCarrier)
2142 np->stats.tx_carrier_errors++;
2143 if (tx_status & DescTxOOWCol)
2144 np->stats.tx_window_errors++;
2145 np->stats.tx_errors++;
2146 }
2147 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2148 np->tx_skbuff[entry]->len,
2149 PCI_DMA_TODEVICE);
2150 /* Free the original skb. */
2151 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2152 np->tx_skbuff[entry] = NULL;
2153 }
2154 if (netif_queue_stopped(dev)
2155 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2156 /* The ring is no longer full, wake queue. */
2157 netif_wake_queue(dev);
2158 }
2159}
2160
2161/* The interrupt handler does all of the Rx thread work and cleans up
2162 after the Tx thread. */
2163static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
2164{
2165 struct net_device *dev = dev_instance;
2166 struct netdev_private *np = netdev_priv(dev);
2167 void __iomem * ioaddr = ns_ioaddr(dev);
2168 int boguscnt = max_interrupt_work;
2169 unsigned int handled = 0;
2170
2171 if (np->hands_off)
2172 return IRQ_NONE;
2173 do {
2174 /* Reading automatically acknowledges all int sources. */
2175 u32 intr_status = readl(ioaddr + IntrStatus);
2176
2177 if (netif_msg_intr(np))
2178 printk(KERN_DEBUG
2179 "%s: Interrupt, status %#08x, mask %#08x.\n",
2180 dev->name, intr_status,
2181 readl(ioaddr + IntrMask));
2182
2183 if (intr_status == 0)
2184 break;
2185 handled = 1;
2186
2187 if (intr_status &
2188 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2189 IntrRxErr | IntrRxOverrun)) {
2190 netdev_rx(dev);
2191 }
2192
2193 if (intr_status &
2194 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2195 spin_lock(&np->lock);
2196 netdev_tx_done(dev);
2197 spin_unlock(&np->lock);
2198 }
2199
2200 /* Abnormal error summary/uncommon events handlers. */
2201 if (intr_status & IntrAbnormalSummary)
2202 netdev_error(dev, intr_status);
2203
2204 if (--boguscnt < 0) {
2205 if (netif_msg_intr(np))
2206 printk(KERN_WARNING
2207 "%s: Too much work at interrupt, "
2208 "status=%#08x.\n",
2209 dev->name, intr_status);
2210 break;
2211 }
2212 } while (1);
2213
2214 if (netif_msg_intr(np))
2215 printk(KERN_DEBUG "%s: exiting interrupt.\n", dev->name);
2216
2217 return IRQ_RETVAL(handled);
2218}
2219
2220/* This routine is logically part of the interrupt handler, but separated
2221 for clarity and better register allocation. */
2222static void netdev_rx(struct net_device *dev)
2223{
2224 struct netdev_private *np = netdev_priv(dev);
2225 int entry = np->cur_rx % RX_RING_SIZE;
2226 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2227 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2228 unsigned int buflen = np->rx_buf_sz;
2229 void __iomem * ioaddr = ns_ioaddr(dev);
2230
2231 /* If the driver owns the next entry it's a new packet. Send it up. */
2232 while (desc_status < 0) { /* e.g. & DescOwn */
2233 int pkt_len;
2234 if (netif_msg_rx_status(np))
2235 printk(KERN_DEBUG
2236 " netdev_rx() entry %d status was %#08x.\n",
2237 entry, desc_status);
2238 if (--boguscnt < 0)
2239 break;
2240 pkt_len = (desc_status & DescSizeMask) - 4;
2241 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2242 if (desc_status & DescMore) {
2243 if (netif_msg_rx_err(np))
2244 printk(KERN_WARNING
2245 "%s: Oversized(?) Ethernet "
2246 "frame spanned multiple "
2247 "buffers, entry %#08x "
2248 "status %#08x.\n", dev->name,
2249 np->cur_rx, desc_status);
2250 np->stats.rx_length_errors++;
2251 } else {
2252 /* There was an error. */
2253 np->stats.rx_errors++;
2254 if (desc_status & (DescRxAbort|DescRxOver))
2255 np->stats.rx_over_errors++;
2256 if (desc_status & (DescRxLong|DescRxRunt))
2257 np->stats.rx_length_errors++;
2258 if (desc_status & (DescRxInvalid|DescRxAlign))
2259 np->stats.rx_frame_errors++;
2260 if (desc_status & DescRxCRC)
2261 np->stats.rx_crc_errors++;
2262 }
2263 } else if (pkt_len > np->rx_buf_sz) {
2264 /* if this is the tail of a double buffer
2265 * packet, we've already counted the error
2266 * on the first part. Ignore the second half.
2267 */
2268 } else {
2269 struct sk_buff *skb;
2270 /* Omit CRC size. */
2271 /* Check if the packet is long enough to accept
2272 * without copying to a minimally-sized skbuff. */
2273 if (pkt_len < rx_copybreak
2274 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2275 skb->dev = dev;
2276 /* 16 byte align the IP header */
2277 skb_reserve(skb, RX_OFFSET);
2278 pci_dma_sync_single_for_cpu(np->pci_dev,
2279 np->rx_dma[entry],
2280 buflen,
2281 PCI_DMA_FROMDEVICE);
2282 eth_copy_and_sum(skb,
2283 np->rx_skbuff[entry]->tail, pkt_len, 0);
2284 skb_put(skb, pkt_len);
2285 pci_dma_sync_single_for_device(np->pci_dev,
2286 np->rx_dma[entry],
2287 buflen,
2288 PCI_DMA_FROMDEVICE);
2289 } else {
2290 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2291 buflen, PCI_DMA_FROMDEVICE);
2292 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2293 np->rx_skbuff[entry] = NULL;
2294 }
2295 skb->protocol = eth_type_trans(skb, dev);
2296 netif_rx(skb);
2297 dev->last_rx = jiffies;
2298 np->stats.rx_packets++;
2299 np->stats.rx_bytes += pkt_len;
2300 }
2301 entry = (++np->cur_rx) % RX_RING_SIZE;
2302 np->rx_head_desc = &np->rx_ring[entry];
2303 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2304 }
2305 refill_rx(dev);
2306
2307 /* Restart Rx engine if stopped. */
2308 if (np->oom)
2309 mod_timer(&np->timer, jiffies + 1);
2310 else
2311 writel(RxOn, ioaddr + ChipCmd);
2312}
2313
2314static void netdev_error(struct net_device *dev, int intr_status)
2315{
2316 struct netdev_private *np = netdev_priv(dev);
2317 void __iomem * ioaddr = ns_ioaddr(dev);
2318
2319 spin_lock(&np->lock);
2320 if (intr_status & LinkChange) {
2321 u16 lpa = mdio_read(dev, MII_LPA);
2322 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2323 && netif_msg_link(np)) {
2324 printk(KERN_INFO
2325 "%s: Autonegotiation advertising"
2326 " %#04x partner %#04x.\n", dev->name,
2327 np->advertising, lpa);
2328 }
2329
2330 /* read MII int status to clear the flag */
2331 readw(ioaddr + MIntrStatus);
2332 check_link(dev);
2333 }
2334 if (intr_status & StatsMax) {
2335 __get_stats(dev);
2336 }
2337 if (intr_status & IntrTxUnderrun) {
2338 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2339 np->tx_config += TX_DRTH_VAL_INC;
2340 if (netif_msg_tx_err(np))
2341 printk(KERN_NOTICE
2342 "%s: increased tx threshold, txcfg %#08x.\n",
2343 dev->name, np->tx_config);
2344 } else {
2345 if (netif_msg_tx_err(np))
2346 printk(KERN_NOTICE
2347 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2348 dev->name, np->tx_config);
2349 }
2350 writel(np->tx_config, ioaddr + TxConfig);
2351 }
2352 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2353 int wol_status = readl(ioaddr + WOLCmd);
2354 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2355 dev->name, wol_status);
2356 }
2357 if (intr_status & RxStatusFIFOOver) {
2358 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2359 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2360 dev->name);
2361 }
2362 np->stats.rx_fifo_errors++;
2363 }
2364 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2365 if (intr_status & IntrPCIErr) {
2366 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2367 intr_status & IntrPCIErr);
2368 np->stats.tx_fifo_errors++;
2369 np->stats.rx_fifo_errors++;
2370 }
2371 spin_unlock(&np->lock);
2372}
2373
2374static void __get_stats(struct net_device *dev)
2375{
2376 void __iomem * ioaddr = ns_ioaddr(dev);
2377 struct netdev_private *np = netdev_priv(dev);
2378
2379 /* The chip only need report frame silently dropped. */
2380 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2381 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2382}
2383
2384static struct net_device_stats *get_stats(struct net_device *dev)
2385{
2386 struct netdev_private *np = netdev_priv(dev);
2387
2388 /* The chip only need report frame silently dropped. */
2389 spin_lock_irq(&np->lock);
2390 if (netif_running(dev) && !np->hands_off)
2391 __get_stats(dev);
2392 spin_unlock_irq(&np->lock);
2393
2394 return &np->stats;
2395}
2396
2397#ifdef CONFIG_NET_POLL_CONTROLLER
2398static void natsemi_poll_controller(struct net_device *dev)
2399{
2400 disable_irq(dev->irq);
2401 intr_handler(dev->irq, dev, NULL);
2402 enable_irq(dev->irq);
2403}
2404#endif
2405
2406#define HASH_TABLE 0x200
2407static void __set_rx_mode(struct net_device *dev)
2408{
2409 void __iomem * ioaddr = ns_ioaddr(dev);
2410 struct netdev_private *np = netdev_priv(dev);
2411 u8 mc_filter[64]; /* Multicast hash filter */
2412 u32 rx_mode;
2413
2414 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2415 /* Unconditionally log net taps. */
2416 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2417 dev->name);
2418 rx_mode = RxFilterEnable | AcceptBroadcast
2419 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2420 } else if ((dev->mc_count > multicast_filter_limit)
2421 || (dev->flags & IFF_ALLMULTI)) {
2422 rx_mode = RxFilterEnable | AcceptBroadcast
2423 | AcceptAllMulticast | AcceptMyPhys;
2424 } else {
2425 struct dev_mc_list *mclist;
2426 int i;
2427 memset(mc_filter, 0, sizeof(mc_filter));
2428 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2429 i++, mclist = mclist->next) {
2430 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2431 mc_filter[i/8] |= (1 << (i & 0x07));
2432 }
2433 rx_mode = RxFilterEnable | AcceptBroadcast
2434 | AcceptMulticast | AcceptMyPhys;
2435 for (i = 0; i < 64; i += 2) {
2436 writew(HASH_TABLE + i, ioaddr + RxFilterAddr);
2437 writew((mc_filter[i+1]<<8) + mc_filter[i],
2438 ioaddr + RxFilterData);
2439 }
2440 }
2441 writel(rx_mode, ioaddr + RxFilterAddr);
2442 np->cur_rx_mode = rx_mode;
2443}
2444
2445static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2446{
2447 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2448 return -EINVAL;
2449
2450 dev->mtu = new_mtu;
2451
2452 /* synchronized against open : rtnl_lock() held by caller */
2453 if (netif_running(dev)) {
2454 struct netdev_private *np = netdev_priv(dev);
2455 void __iomem * ioaddr = ns_ioaddr(dev);
2456
2457 disable_irq(dev->irq);
2458 spin_lock(&np->lock);
2459 /* stop engines */
2460 natsemi_stop_rxtx(dev);
2461 /* drain rx queue */
2462 drain_rx(dev);
2463 /* change buffers */
2464 set_bufsize(dev);
2465 reinit_rx(dev);
2466 writel(np->ring_dma, ioaddr + RxRingPtr);
2467 /* restart engines */
2468 writel(RxOn | TxOn, ioaddr + ChipCmd);
2469 spin_unlock(&np->lock);
2470 enable_irq(dev->irq);
2471 }
2472 return 0;
2473}
2474
2475static void set_rx_mode(struct net_device *dev)
2476{
2477 struct netdev_private *np = netdev_priv(dev);
2478 spin_lock_irq(&np->lock);
2479 if (!np->hands_off)
2480 __set_rx_mode(dev);
2481 spin_unlock_irq(&np->lock);
2482}
2483
2484static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2485{
2486 struct netdev_private *np = netdev_priv(dev);
2487 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2488 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2489 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2490}
2491
2492static int get_regs_len(struct net_device *dev)
2493{
2494 return NATSEMI_REGS_SIZE;
2495}
2496
2497static int get_eeprom_len(struct net_device *dev)
2498{
2499 return NATSEMI_EEPROM_SIZE;
2500}
2501
2502static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2503{
2504 struct netdev_private *np = netdev_priv(dev);
2505 spin_lock_irq(&np->lock);
2506 netdev_get_ecmd(dev, ecmd);
2507 spin_unlock_irq(&np->lock);
2508 return 0;
2509}
2510
2511static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2512{
2513 struct netdev_private *np = netdev_priv(dev);
2514 int res;
2515 spin_lock_irq(&np->lock);
2516 res = netdev_set_ecmd(dev, ecmd);
2517 spin_unlock_irq(&np->lock);
2518 return res;
2519}
2520
2521static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2522{
2523 struct netdev_private *np = netdev_priv(dev);
2524 spin_lock_irq(&np->lock);
2525 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2526 netdev_get_sopass(dev, wol->sopass);
2527 spin_unlock_irq(&np->lock);
2528}
2529
2530static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2531{
2532 struct netdev_private *np = netdev_priv(dev);
2533 int res;
2534 spin_lock_irq(&np->lock);
2535 netdev_set_wol(dev, wol->wolopts);
2536 res = netdev_set_sopass(dev, wol->sopass);
2537 spin_unlock_irq(&np->lock);
2538 return res;
2539}
2540
2541static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2542{
2543 struct netdev_private *np = netdev_priv(dev);
2544 regs->version = NATSEMI_REGS_VER;
2545 spin_lock_irq(&np->lock);
2546 netdev_get_regs(dev, buf);
2547 spin_unlock_irq(&np->lock);
2548}
2549
2550static u32 get_msglevel(struct net_device *dev)
2551{
2552 struct netdev_private *np = netdev_priv(dev);
2553 return np->msg_enable;
2554}
2555
2556static void set_msglevel(struct net_device *dev, u32 val)
2557{
2558 struct netdev_private *np = netdev_priv(dev);
2559 np->msg_enable = val;
2560}
2561
2562static int nway_reset(struct net_device *dev)
2563{
2564 int tmp;
2565 int r = -EINVAL;
2566 /* if autoneg is off, it's an error */
2567 tmp = mdio_read(dev, MII_BMCR);
2568 if (tmp & BMCR_ANENABLE) {
2569 tmp |= (BMCR_ANRESTART);
2570 mdio_write(dev, MII_BMCR, tmp);
2571 r = 0;
2572 }
2573 return r;
2574}
2575
2576static u32 get_link(struct net_device *dev)
2577{
2578 /* LSTATUS is latched low until a read - so read twice */
2579 mdio_read(dev, MII_BMSR);
2580 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2581}
2582
2583static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2584{
2585 struct netdev_private *np = netdev_priv(dev);
2586 u8 eebuf[NATSEMI_EEPROM_SIZE];
2587 int res;
2588
2589 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2590 spin_lock_irq(&np->lock);
2591 res = netdev_get_eeprom(dev, eebuf);
2592 spin_unlock_irq(&np->lock);
2593 if (!res)
2594 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2595 return res;
2596}
2597
2598static struct ethtool_ops ethtool_ops = {
2599 .get_drvinfo = get_drvinfo,
2600 .get_regs_len = get_regs_len,
2601 .get_eeprom_len = get_eeprom_len,
2602 .get_settings = get_settings,
2603 .set_settings = set_settings,
2604 .get_wol = get_wol,
2605 .set_wol = set_wol,
2606 .get_regs = get_regs,
2607 .get_msglevel = get_msglevel,
2608 .set_msglevel = set_msglevel,
2609 .nway_reset = nway_reset,
2610 .get_link = get_link,
2611 .get_eeprom = get_eeprom,
2612};
2613
2614static int netdev_set_wol(struct net_device *dev, u32 newval)
2615{
2616 struct netdev_private *np = netdev_priv(dev);
2617 void __iomem * ioaddr = ns_ioaddr(dev);
2618 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2619
2620 /* translate to bitmasks this chip understands */
2621 if (newval & WAKE_PHY)
2622 data |= WakePhy;
2623 if (newval & WAKE_UCAST)
2624 data |= WakeUnicast;
2625 if (newval & WAKE_MCAST)
2626 data |= WakeMulticast;
2627 if (newval & WAKE_BCAST)
2628 data |= WakeBroadcast;
2629 if (newval & WAKE_ARP)
2630 data |= WakeArp;
2631 if (newval & WAKE_MAGIC)
2632 data |= WakeMagic;
2633 if (np->srr >= SRR_DP83815_D) {
2634 if (newval & WAKE_MAGICSECURE) {
2635 data |= WakeMagicSecure;
2636 }
2637 }
2638
2639 writel(data, ioaddr + WOLCmd);
2640
2641 return 0;
2642}
2643
2644static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2645{
2646 struct netdev_private *np = netdev_priv(dev);
2647 void __iomem * ioaddr = ns_ioaddr(dev);
2648 u32 regval = readl(ioaddr + WOLCmd);
2649
2650 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2651 | WAKE_ARP | WAKE_MAGIC);
2652
2653 if (np->srr >= SRR_DP83815_D) {
2654 /* SOPASS works on revD and higher */
2655 *supported |= WAKE_MAGICSECURE;
2656 }
2657 *cur = 0;
2658
2659 /* translate from chip bitmasks */
2660 if (regval & WakePhy)
2661 *cur |= WAKE_PHY;
2662 if (regval & WakeUnicast)
2663 *cur |= WAKE_UCAST;
2664 if (regval & WakeMulticast)
2665 *cur |= WAKE_MCAST;
2666 if (regval & WakeBroadcast)
2667 *cur |= WAKE_BCAST;
2668 if (regval & WakeArp)
2669 *cur |= WAKE_ARP;
2670 if (regval & WakeMagic)
2671 *cur |= WAKE_MAGIC;
2672 if (regval & WakeMagicSecure) {
2673 /* this can be on in revC, but it's broken */
2674 *cur |= WAKE_MAGICSECURE;
2675 }
2676
2677 return 0;
2678}
2679
2680static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2681{
2682 struct netdev_private *np = netdev_priv(dev);
2683 void __iomem * ioaddr = ns_ioaddr(dev);
2684 u16 *sval = (u16 *)newval;
2685 u32 addr;
2686
2687 if (np->srr < SRR_DP83815_D) {
2688 return 0;
2689 }
2690
2691 /* enable writing to these registers by disabling the RX filter */
2692 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2693 addr &= ~RxFilterEnable;
2694 writel(addr, ioaddr + RxFilterAddr);
2695
2696 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2697 writel(addr | 0xa, ioaddr + RxFilterAddr);
2698 writew(sval[0], ioaddr + RxFilterData);
2699
2700 writel(addr | 0xc, ioaddr + RxFilterAddr);
2701 writew(sval[1], ioaddr + RxFilterData);
2702
2703 writel(addr | 0xe, ioaddr + RxFilterAddr);
2704 writew(sval[2], ioaddr + RxFilterData);
2705
2706 /* re-enable the RX filter */
2707 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2708
2709 return 0;
2710}
2711
2712static int netdev_get_sopass(struct net_device *dev, u8 *data)
2713{
2714 struct netdev_private *np = netdev_priv(dev);
2715 void __iomem * ioaddr = ns_ioaddr(dev);
2716 u16 *sval = (u16 *)data;
2717 u32 addr;
2718
2719 if (np->srr < SRR_DP83815_D) {
2720 sval[0] = sval[1] = sval[2] = 0;
2721 return 0;
2722 }
2723
2724 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2725 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2726
2727 writel(addr | 0xa, ioaddr + RxFilterAddr);
2728 sval[0] = readw(ioaddr + RxFilterData);
2729
2730 writel(addr | 0xc, ioaddr + RxFilterAddr);
2731 sval[1] = readw(ioaddr + RxFilterData);
2732
2733 writel(addr | 0xe, ioaddr + RxFilterAddr);
2734 sval[2] = readw(ioaddr + RxFilterData);
2735
2736 writel(addr, ioaddr + RxFilterAddr);
2737
2738 return 0;
2739}
2740
2741static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2742{
2743 struct netdev_private *np = netdev_priv(dev);
2744 u32 tmp;
2745
2746 ecmd->port = dev->if_port;
2747 ecmd->speed = np->speed;
2748 ecmd->duplex = np->duplex;
2749 ecmd->autoneg = np->autoneg;
2750 ecmd->advertising = 0;
2751 if (np->advertising & ADVERTISE_10HALF)
2752 ecmd->advertising |= ADVERTISED_10baseT_Half;
2753 if (np->advertising & ADVERTISE_10FULL)
2754 ecmd->advertising |= ADVERTISED_10baseT_Full;
2755 if (np->advertising & ADVERTISE_100HALF)
2756 ecmd->advertising |= ADVERTISED_100baseT_Half;
2757 if (np->advertising & ADVERTISE_100FULL)
2758 ecmd->advertising |= ADVERTISED_100baseT_Full;
2759 ecmd->supported = (SUPPORTED_Autoneg |
2760 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2761 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2762 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2763 ecmd->phy_address = np->phy_addr_external;
2764 /*
2765 * We intentionally report the phy address of the external
2766 * phy, even if the internal phy is used. This is necessary
2767 * to work around a deficiency of the ethtool interface:
2768 * It's only possible to query the settings of the active
2769 * port. Therefore
2770 * # ethtool -s ethX port mii
2771 * actually sends an ioctl to switch to port mii with the
2772 * settings that are used for the current active port.
2773 * If we would report a different phy address in this
2774 * command, then
2775 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2776 * would unintentionally change the phy address.
2777 *
2778 * Fortunately the phy address doesn't matter with the
2779 * internal phy...
2780 */
2781
2782 /* set information based on active port type */
2783 switch (ecmd->port) {
2784 default:
2785 case PORT_TP:
2786 ecmd->advertising |= ADVERTISED_TP;
2787 ecmd->transceiver = XCVR_INTERNAL;
2788 break;
2789 case PORT_MII:
2790 ecmd->advertising |= ADVERTISED_MII;
2791 ecmd->transceiver = XCVR_EXTERNAL;
2792 break;
2793 case PORT_FIBRE:
2794 ecmd->advertising |= ADVERTISED_FIBRE;
2795 ecmd->transceiver = XCVR_EXTERNAL;
2796 break;
2797 }
2798
2799 /* if autonegotiation is on, try to return the active speed/duplex */
2800 if (ecmd->autoneg == AUTONEG_ENABLE) {
2801 ecmd->advertising |= ADVERTISED_Autoneg;
2802 tmp = mii_nway_result(
2803 np->advertising & mdio_read(dev, MII_LPA));
2804 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2805 ecmd->speed = SPEED_100;
2806 else
2807 ecmd->speed = SPEED_10;
2808 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2809 ecmd->duplex = DUPLEX_FULL;
2810 else
2811 ecmd->duplex = DUPLEX_HALF;
2812 }
2813
2814 /* ignore maxtxpkt, maxrxpkt for now */
2815
2816 return 0;
2817}
2818
2819static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2820{
2821 struct netdev_private *np = netdev_priv(dev);
2822
2823 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2824 return -EINVAL;
2825 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2826 return -EINVAL;
2827 if (ecmd->autoneg == AUTONEG_ENABLE) {
2828 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2829 ADVERTISED_10baseT_Full |
2830 ADVERTISED_100baseT_Half |
2831 ADVERTISED_100baseT_Full)) == 0) {
2832 return -EINVAL;
2833 }
2834 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2835 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2836 return -EINVAL;
2837 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2838 return -EINVAL;
2839 } else {
2840 return -EINVAL;
2841 }
2842
2843 /*
2844 * maxtxpkt, maxrxpkt: ignored for now.
2845 *
2846 * transceiver:
2847 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2848 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2849 * selects based on ecmd->port.
2850 *
2851 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2852 * phys that are connected to the mii bus. It's used to apply fibre
2853 * specific updates.
2854 */
2855
2856 /* WHEW! now lets bang some bits */
2857
2858 /* save the parms */
2859 dev->if_port = ecmd->port;
2860 np->autoneg = ecmd->autoneg;
2861 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2862 if (np->autoneg == AUTONEG_ENABLE) {
2863 /* advertise only what has been requested */
2864 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2865 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2866 np->advertising |= ADVERTISE_10HALF;
2867 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2868 np->advertising |= ADVERTISE_10FULL;
2869 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2870 np->advertising |= ADVERTISE_100HALF;
2871 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2872 np->advertising |= ADVERTISE_100FULL;
2873 } else {
2874 np->speed = ecmd->speed;
2875 np->duplex = ecmd->duplex;
2876 /* user overriding the initial full duplex parm? */
2877 if (np->duplex == DUPLEX_HALF)
2878 np->full_duplex = 0;
2879 }
2880
2881 /* get the right phy enabled */
2882 if (ecmd->port == PORT_TP)
2883 switch_port_internal(dev);
2884 else
2885 switch_port_external(dev);
2886
2887 /* set parms and see how this affected our link status */
2888 init_phy_fixup(dev);
2889 check_link(dev);
2890 return 0;
2891}
2892
2893static int netdev_get_regs(struct net_device *dev, u8 *buf)
2894{
2895 int i;
2896 int j;
2897 u32 rfcr;
2898 u32 *rbuf = (u32 *)buf;
2899 void __iomem * ioaddr = ns_ioaddr(dev);
2900
2901 /* read non-mii page 0 of registers */
2902 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2903 rbuf[i] = readl(ioaddr + i*4);
2904 }
2905
2906 /* read current mii registers */
2907 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2908 rbuf[i] = mdio_read(dev, i & 0x1f);
2909
2910 /* read only the 'magic' registers from page 1 */
2911 writew(1, ioaddr + PGSEL);
2912 rbuf[i++] = readw(ioaddr + PMDCSR);
2913 rbuf[i++] = readw(ioaddr + TSTDAT);
2914 rbuf[i++] = readw(ioaddr + DSPCFG);
2915 rbuf[i++] = readw(ioaddr + SDCFG);
2916 writew(0, ioaddr + PGSEL);
2917
2918 /* read RFCR indexed registers */
2919 rfcr = readl(ioaddr + RxFilterAddr);
2920 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
2921 writel(j*2, ioaddr + RxFilterAddr);
2922 rbuf[i++] = readw(ioaddr + RxFilterData);
2923 }
2924 writel(rfcr, ioaddr + RxFilterAddr);
2925
2926 /* the interrupt status is clear-on-read - see if we missed any */
2927 if (rbuf[4] & rbuf[5]) {
2928 printk(KERN_WARNING
2929 "%s: shoot, we dropped an interrupt (%#08x)\n",
2930 dev->name, rbuf[4] & rbuf[5]);
2931 }
2932
2933 return 0;
2934}
2935
2936#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
2937 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
2938 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
2939 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
2940 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
2941 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
2942 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
2943 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
2944
2945static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
2946{
2947 int i;
2948 u16 *ebuf = (u16 *)buf;
2949 void __iomem * ioaddr = ns_ioaddr(dev);
2950
2951 /* eeprom_read reads 16 bits, and indexes by 16 bits */
2952 for (i = 0; i < NATSEMI_EEPROM_SIZE/2; i++) {
2953 ebuf[i] = eeprom_read(ioaddr, i);
2954 /* The EEPROM itself stores data bit-swapped, but eeprom_read
2955 * reads it back "sanely". So we swap it back here in order to
2956 * present it to userland as it is stored. */
2957 ebuf[i] = SWAP_BITS(ebuf[i]);
2958 }
2959 return 0;
2960}
2961
2962static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2963{
2964 struct mii_ioctl_data *data = if_mii(rq);
2965 struct netdev_private *np = netdev_priv(dev);
2966
2967 switch(cmd) {
2968 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2969 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
2970 data->phy_id = np->phy_addr_external;
2971 /* Fall Through */
2972
2973 case SIOCGMIIREG: /* Read MII PHY register. */
2974 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
2975 /* The phy_id is not enough to uniquely identify
2976 * the intended target. Therefore the command is sent to
2977 * the given mii on the current port.
2978 */
2979 if (dev->if_port == PORT_TP) {
2980 if ((data->phy_id & 0x1f) == np->phy_addr_external)
2981 data->val_out = mdio_read(dev,
2982 data->reg_num & 0x1f);
2983 else
2984 data->val_out = 0;
2985 } else {
2986 move_int_phy(dev, data->phy_id & 0x1f);
2987 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
2988 data->reg_num & 0x1f);
2989 }
2990 return 0;
2991
2992 case SIOCSMIIREG: /* Write MII PHY register. */
2993 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
2994 if (!capable(CAP_NET_ADMIN))
2995 return -EPERM;
2996 if (dev->if_port == PORT_TP) {
2997 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
2998 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
2999 np->advertising = data->val_in;
3000 mdio_write(dev, data->reg_num & 0x1f,
3001 data->val_in);
3002 }
3003 } else {
3004 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3005 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3006 np->advertising = data->val_in;
3007 }
3008 move_int_phy(dev, data->phy_id & 0x1f);
3009 miiport_write(dev, data->phy_id & 0x1f,
3010 data->reg_num & 0x1f,
3011 data->val_in);
3012 }
3013 return 0;
3014 default:
3015 return -EOPNOTSUPP;
3016 }
3017}
3018
3019static void enable_wol_mode(struct net_device *dev, int enable_intr)
3020{
3021 void __iomem * ioaddr = ns_ioaddr(dev);
3022 struct netdev_private *np = netdev_priv(dev);
3023
3024 if (netif_msg_wol(np))
3025 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3026 dev->name);
3027
3028 /* For WOL we must restart the rx process in silent mode.
3029 * Write NULL to the RxRingPtr. Only possible if
3030 * rx process is stopped
3031 */
3032 writel(0, ioaddr + RxRingPtr);
3033
3034 /* read WoL status to clear */
3035 readl(ioaddr + WOLCmd);
3036
3037 /* PME on, clear status */
3038 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3039
3040 /* and restart the rx process */
3041 writel(RxOn, ioaddr + ChipCmd);
3042
3043 if (enable_intr) {
3044 /* enable the WOL interrupt.
3045 * Could be used to send a netlink message.
3046 */
3047 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3048 writel(1, ioaddr + IntrEnable);
3049 }
3050}
3051
3052static int netdev_close(struct net_device *dev)
3053{
3054 void __iomem * ioaddr = ns_ioaddr(dev);
3055 struct netdev_private *np = netdev_priv(dev);
3056
3057 if (netif_msg_ifdown(np))
3058 printk(KERN_DEBUG
3059 "%s: Shutting down ethercard, status was %#04x.\n",
3060 dev->name, (int)readl(ioaddr + ChipCmd));
3061 if (netif_msg_pktdata(np))
3062 printk(KERN_DEBUG
3063 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3064 dev->name, np->cur_tx, np->dirty_tx,
3065 np->cur_rx, np->dirty_rx);
3066
3067 /*
3068 * FIXME: what if someone tries to close a device
3069 * that is suspended?
3070 * Should we reenable the nic to switch to
3071 * the final WOL settings?
3072 */
3073
3074 del_timer_sync(&np->timer);
3075 disable_irq(dev->irq);
3076 spin_lock_irq(&np->lock);
3077 /* Disable interrupts, and flush posted writes */
3078 writel(0, ioaddr + IntrEnable);
3079 readl(ioaddr + IntrEnable);
3080 np->hands_off = 1;
3081 spin_unlock_irq(&np->lock);
3082 enable_irq(dev->irq);
3083
3084 free_irq(dev->irq, dev);
3085
3086 /* Interrupt disabled, interrupt handler released,
3087 * queue stopped, timer deleted, rtnl_lock held
3088 * All async codepaths that access the driver are disabled.
3089 */
3090 spin_lock_irq(&np->lock);
3091 np->hands_off = 0;
3092 readl(ioaddr + IntrMask);
3093 readw(ioaddr + MIntrStatus);
3094
3095 /* Freeze Stats */
3096 writel(StatsFreeze, ioaddr + StatsCtrl);
3097
3098 /* Stop the chip's Tx and Rx processes. */
3099 natsemi_stop_rxtx(dev);
3100
3101 __get_stats(dev);
3102 spin_unlock_irq(&np->lock);
3103
3104 /* clear the carrier last - an interrupt could reenable it otherwise */
3105 netif_carrier_off(dev);
3106 netif_stop_queue(dev);
3107
3108 dump_ring(dev);
3109 drain_ring(dev);
3110 free_ring(dev);
3111
3112 {
3113 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3114 if (wol) {
3115 /* restart the NIC in WOL mode.
3116 * The nic must be stopped for this.
3117 */
3118 enable_wol_mode(dev, 0);
3119 } else {
3120 /* Restore PME enable bit unmolested */
3121 writel(np->SavedClkRun, ioaddr + ClkRun);
3122 }
3123 }
3124 return 0;
3125}
3126
3127
3128static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3129{
3130 struct net_device *dev = pci_get_drvdata(pdev);
3131 void __iomem * ioaddr = ns_ioaddr(dev);
3132
3133 unregister_netdev (dev);
3134 pci_release_regions (pdev);
3135 iounmap(ioaddr);
3136 free_netdev (dev);
3137 pci_set_drvdata(pdev, NULL);
3138}
3139
3140#ifdef CONFIG_PM
3141
3142/*
3143 * The ns83815 chip doesn't have explicit RxStop bits.
3144 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3145 * of the nic, thus this function must be very careful:
3146 *
3147 * suspend/resume synchronization:
3148 * entry points:
3149 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3150 * start_tx, tx_timeout
3151 *
3152 * No function accesses the hardware without checking np->hands_off.
3153 * the check occurs under spin_lock_irq(&np->lock);
3154 * exceptions:
3155 * * netdev_ioctl: noncritical access.
3156 * * netdev_open: cannot happen due to the device_detach
3157 * * netdev_close: doesn't hurt.
3158 * * netdev_timer: timer stopped by natsemi_suspend.
3159 * * intr_handler: doesn't acquire the spinlock. suspend calls
3160 * disable_irq() to enforce synchronization.
3161 *
3162 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3163 */
3164
3165static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3166{
3167 struct net_device *dev = pci_get_drvdata (pdev);
3168 struct netdev_private *np = netdev_priv(dev);
3169 void __iomem * ioaddr = ns_ioaddr(dev);
3170
3171 rtnl_lock();
3172 if (netif_running (dev)) {
3173 del_timer_sync(&np->timer);
3174
3175 disable_irq(dev->irq);
3176 spin_lock_irq(&np->lock);
3177
3178 writel(0, ioaddr + IntrEnable);
3179 np->hands_off = 1;
3180 natsemi_stop_rxtx(dev);
3181 netif_stop_queue(dev);
3182
3183 spin_unlock_irq(&np->lock);
3184 enable_irq(dev->irq);
3185
3186 /* Update the error counts. */
3187 __get_stats(dev);
3188
3189 /* pci_power_off(pdev, -1); */
3190 drain_ring(dev);
3191 {
3192 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3193 /* Restore PME enable bit */
3194 if (wol) {
3195 /* restart the NIC in WOL mode.
3196 * The nic must be stopped for this.
3197 * FIXME: use the WOL interrupt
3198 */
3199 enable_wol_mode(dev, 0);
3200 } else {
3201 /* Restore PME enable bit unmolested */
3202 writel(np->SavedClkRun, ioaddr + ClkRun);
3203 }
3204 }
3205 }
3206 netif_device_detach(dev);
3207 rtnl_unlock();
3208 return 0;
3209}
3210
3211
3212static int natsemi_resume (struct pci_dev *pdev)
3213{
3214 struct net_device *dev = pci_get_drvdata (pdev);
3215 struct netdev_private *np = netdev_priv(dev);
3216
3217 rtnl_lock();
3218 if (netif_device_present(dev))
3219 goto out;
3220 if (netif_running(dev)) {
3221 BUG_ON(!np->hands_off);
3222 pci_enable_device(pdev);
3223 /* pci_power_on(pdev); */
3224
3225 natsemi_reset(dev);
3226 init_ring(dev);
3227 disable_irq(dev->irq);
3228 spin_lock_irq(&np->lock);
3229 np->hands_off = 0;
3230 init_registers(dev);
3231 netif_device_attach(dev);
3232 spin_unlock_irq(&np->lock);
3233 enable_irq(dev->irq);
3234
3235 mod_timer(&np->timer, jiffies + 1*HZ);
3236 }
3237 netif_device_attach(dev);
3238out:
3239 rtnl_unlock();
3240 return 0;
3241}
3242
3243#endif /* CONFIG_PM */
3244
3245static struct pci_driver natsemi_driver = {
3246 .name = DRV_NAME,
3247 .id_table = natsemi_pci_tbl,
3248 .probe = natsemi_probe1,
3249 .remove = __devexit_p(natsemi_remove1),
3250#ifdef CONFIG_PM
3251 .suspend = natsemi_suspend,
3252 .resume = natsemi_resume,
3253#endif
3254};
3255
3256static int __init natsemi_init_mod (void)
3257{
3258/* when a module, this is printed whether or not devices are found in probe */
3259#ifdef MODULE
3260 printk(version);
3261#endif
3262
3263 return pci_module_init (&natsemi_driver);
3264}
3265
3266static void __exit natsemi_exit_mod (void)
3267{
3268 pci_unregister_driver (&natsemi_driver);
3269}
3270
3271module_init(natsemi_init_mod);
3272module_exit(natsemi_exit_mod);
3273
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 12:39:59 -0500