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-rw-r--r--drivers/net/myri10ge/Makefile5
-rw-r--r--drivers/net/myri10ge/myri10ge.c2851
-rw-r--r--drivers/net/myri10ge/myri10ge_mcp.h205
-rw-r--r--drivers/net/myri10ge/myri10ge_mcp_gen_header.h58
4 files changed, 3119 insertions, 0 deletions
diff --git a/drivers/net/myri10ge/Makefile b/drivers/net/myri10ge/Makefile
new file mode 100644
index 000000000000..5df891647aee
--- /dev/null
+++ b/drivers/net/myri10ge/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Myricom Myri-10G ethernet driver
3#
4
5obj-$(CONFIG_MYRI10GE) += myri10ge.o
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
new file mode 100644
index 000000000000..87933cba7e22
--- /dev/null
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -0,0 +1,2851 @@
1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
47#include <linux/etherdevice.h>
48#include <linux/if_ether.h>
49#include <linux/if_vlan.h>
50#include <linux/ip.h>
51#include <linux/inet.h>
52#include <linux/in.h>
53#include <linux/ethtool.h>
54#include <linux/firmware.h>
55#include <linux/delay.h>
56#include <linux/version.h>
57#include <linux/timer.h>
58#include <linux/vmalloc.h>
59#include <linux/crc32.h>
60#include <linux/moduleparam.h>
61#include <linux/io.h>
62#include <net/checksum.h>
63#include <asm/byteorder.h>
64#include <asm/io.h>
65#include <asm/pci.h>
66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
74#define MYRI10GE_VERSION_STR "0.9.0"
75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92#define MYRI10GE_NO_CONFIRM_DATA 0xffffffff
93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95struct myri10ge_rx_buffer_state {
96 struct sk_buff *skb;
97 DECLARE_PCI_UNMAP_ADDR(bus)
98 DECLARE_PCI_UNMAP_LEN(len)
99};
100
101struct myri10ge_tx_buffer_state {
102 struct sk_buff *skb;
103 int last;
104 DECLARE_PCI_UNMAP_ADDR(bus)
105 DECLARE_PCI_UNMAP_LEN(len)
106};
107
108struct myri10ge_cmd {
109 u32 data0;
110 u32 data1;
111 u32 data2;
112};
113
114struct myri10ge_rx_buf {
115 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
116 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
117 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
118 struct myri10ge_rx_buffer_state *info;
119 int cnt;
120 int alloc_fail;
121 int mask; /* number of rx slots -1 */
122};
123
124struct myri10ge_tx_buf {
125 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
126 u8 __iomem *wc_fifo; /* w/c send fifo address */
127 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
128 char *req_bytes;
129 struct myri10ge_tx_buffer_state *info;
130 int mask; /* number of transmit slots -1 */
131 int boundary; /* boundary transmits cannot cross */
132 int req ____cacheline_aligned; /* transmit slots submitted */
133 int pkt_start; /* packets started */
134 int done ____cacheline_aligned; /* transmit slots completed */
135 int pkt_done; /* packets completed */
136};
137
138struct myri10ge_rx_done {
139 struct mcp_slot *entry;
140 dma_addr_t bus;
141 int cnt;
142 int idx;
143};
144
145struct myri10ge_priv {
146 int running; /* running? */
147 int csum_flag; /* rx_csums? */
148 struct myri10ge_tx_buf tx; /* transmit ring */
149 struct myri10ge_rx_buf rx_small;
150 struct myri10ge_rx_buf rx_big;
151 struct myri10ge_rx_done rx_done;
152 int small_bytes;
153 struct net_device *dev;
154 struct net_device_stats stats;
155 u8 __iomem *sram;
156 int sram_size;
157 unsigned long board_span;
158 unsigned long iomem_base;
159 u32 __iomem *irq_claim;
160 u32 __iomem *irq_deassert;
161 char *mac_addr_string;
162 struct mcp_cmd_response *cmd;
163 dma_addr_t cmd_bus;
164 struct mcp_irq_data *fw_stats;
165 dma_addr_t fw_stats_bus;
166 struct pci_dev *pdev;
167 int msi_enabled;
168 unsigned int link_state;
169 unsigned int rdma_tags_available;
170 int intr_coal_delay;
171 u32 __iomem *intr_coal_delay_ptr;
172 int mtrr;
173 int wake_queue;
174 int stop_queue;
175 int down_cnt;
176 wait_queue_head_t down_wq;
177 struct work_struct watchdog_work;
178 struct timer_list watchdog_timer;
179 int watchdog_tx_done;
180 int watchdog_resets;
181 int tx_linearized;
182 int pause;
183 char *fw_name;
184 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
185 char fw_version[128];
186 u8 mac_addr[6]; /* eeprom mac address */
187 unsigned long serial_number;
188 int vendor_specific_offset;
189 u32 devctl;
190 u16 msi_flags;
191 u32 pm_state[16];
192 u32 read_dma;
193 u32 write_dma;
194 u32 read_write_dma;
195};
196
197static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
198static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
199
200static char *myri10ge_fw_name = NULL;
201module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
202MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
203
204static int myri10ge_ecrc_enable = 1;
205module_param(myri10ge_ecrc_enable, int, S_IRUGO);
206MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
207
208static int myri10ge_max_intr_slots = 1024;
209module_param(myri10ge_max_intr_slots, int, S_IRUGO);
210MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
211
212static int myri10ge_small_bytes = -1; /* -1 == auto */
213module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
214MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
215
216static int myri10ge_msi = 1; /* enable msi by default */
217module_param(myri10ge_msi, int, S_IRUGO);
218MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
219
220static int myri10ge_intr_coal_delay = 25;
221module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
222MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
223
224static int myri10ge_flow_control = 1;
225module_param(myri10ge_flow_control, int, S_IRUGO);
226MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
227
228static int myri10ge_deassert_wait = 1;
229module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
230MODULE_PARM_DESC(myri10ge_deassert_wait,
231 "Wait when deasserting legacy interrupts\n");
232
233static int myri10ge_force_firmware = 0;
234module_param(myri10ge_force_firmware, int, S_IRUGO);
235MODULE_PARM_DESC(myri10ge_force_firmware,
236 "Force firmware to assume aligned completions\n");
237
238static int myri10ge_skb_cross_4k = 0;
239module_param(myri10ge_skb_cross_4k, int, S_IRUGO | S_IWUSR);
240MODULE_PARM_DESC(myri10ge_skb_cross_4k,
241 "Can a small skb cross a 4KB boundary?\n");
242
243static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
244module_param(myri10ge_initial_mtu, int, S_IRUGO);
245MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
246
247static int myri10ge_napi_weight = 64;
248module_param(myri10ge_napi_weight, int, S_IRUGO);
249MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
250
251static int myri10ge_watchdog_timeout = 1;
252module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
253MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
254
255static int myri10ge_max_irq_loops = 1048576;
256module_param(myri10ge_max_irq_loops, int, S_IRUGO);
257MODULE_PARM_DESC(myri10ge_max_irq_loops,
258 "Set stuck legacy IRQ detection threshold\n");
259
260#define MYRI10GE_FW_OFFSET 1024*1024
261#define MYRI10GE_HIGHPART_TO_U32(X) \
262(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
263#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
264
265#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
266
267static int
268myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
269 struct myri10ge_cmd *data, int atomic)
270{
271 struct mcp_cmd *buf;
272 char buf_bytes[sizeof(*buf) + 8];
273 struct mcp_cmd_response *response = mgp->cmd;
274 char __iomem *cmd_addr = mgp->sram + MXGEFW_CMD_OFFSET;
275 u32 dma_low, dma_high, result, value;
276 int sleep_total = 0;
277
278 /* ensure buf is aligned to 8 bytes */
279 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
280
281 buf->data0 = htonl(data->data0);
282 buf->data1 = htonl(data->data1);
283 buf->data2 = htonl(data->data2);
284 buf->cmd = htonl(cmd);
285 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
286 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
287
288 buf->response_addr.low = htonl(dma_low);
289 buf->response_addr.high = htonl(dma_high);
290 response->result = MYRI10GE_NO_RESPONSE_RESULT;
291 mb();
292 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
293
294 /* wait up to 15ms. Longest command is the DMA benchmark,
295 * which is capped at 5ms, but runs from a timeout handler
296 * that runs every 7.8ms. So a 15ms timeout leaves us with
297 * a 2.2ms margin
298 */
299 if (atomic) {
300 /* if atomic is set, do not sleep,
301 * and try to get the completion quickly
302 * (1ms will be enough for those commands) */
303 for (sleep_total = 0;
304 sleep_total < 1000
305 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
306 sleep_total += 10)
307 udelay(10);
308 } else {
309 /* use msleep for most command */
310 for (sleep_total = 0;
311 sleep_total < 15
312 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
313 sleep_total++)
314 msleep(1);
315 }
316
317 result = ntohl(response->result);
318 value = ntohl(response->data);
319 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
320 if (result == 0) {
321 data->data0 = value;
322 return 0;
323 } else {
324 dev_err(&mgp->pdev->dev,
325 "command %d failed, result = %d\n",
326 cmd, result);
327 return -ENXIO;
328 }
329 }
330
331 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
332 cmd, result);
333 return -EAGAIN;
334}
335
336/*
337 * The eeprom strings on the lanaiX have the format
338 * SN=x\0
339 * MAC=x:x:x:x:x:x\0
340 * PT:ddd mmm xx xx:xx:xx xx\0
341 * PV:ddd mmm xx xx:xx:xx xx\0
342 */
343static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
344{
345 char *ptr, *limit;
346 int i;
347
348 ptr = mgp->eeprom_strings;
349 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
350
351 while (*ptr != '\0' && ptr < limit) {
352 if (memcmp(ptr, "MAC=", 4) == 0) {
353 ptr += 4;
354 mgp->mac_addr_string = ptr;
355 for (i = 0; i < 6; i++) {
356 if ((ptr + 2) > limit)
357 goto abort;
358 mgp->mac_addr[i] =
359 simple_strtoul(ptr, &ptr, 16);
360 ptr += 1;
361 }
362 }
363 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
364 ptr += 3;
365 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
366 }
367 while (ptr < limit && *ptr++) ;
368 }
369
370 return 0;
371
372abort:
373 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
374 return -ENXIO;
375}
376
377/*
378 * Enable or disable periodic RDMAs from the host to make certain
379 * chipsets resend dropped PCIe messages
380 */
381
382static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
383{
384 char __iomem *submit;
385 u32 buf[16];
386 u32 dma_low, dma_high;
387 int i;
388
389 /* clear confirmation addr */
390 mgp->cmd->data = 0;
391 mb();
392
393 /* send a rdma command to the PCIe engine, and wait for the
394 * response in the confirmation address. The firmware should
395 * write a -1 there to indicate it is alive and well
396 */
397 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
398 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
399
400 buf[0] = htonl(dma_high); /* confirm addr MSW */
401 buf[1] = htonl(dma_low); /* confirm addr LSW */
402 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
403 buf[3] = htonl(dma_high); /* dummy addr MSW */
404 buf[4] = htonl(dma_low); /* dummy addr LSW */
405 buf[5] = htonl(enable); /* enable? */
406
407 submit = mgp->sram + 0xfc01c0;
408
409 myri10ge_pio_copy(submit, &buf, sizeof(buf));
410 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
411 msleep(1);
412 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
413 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
414 (enable ? "enable" : "disable"));
415}
416
417static int
418myri10ge_validate_firmware(struct myri10ge_priv *mgp,
419 struct mcp_gen_header *hdr)
420{
421 struct device *dev = &mgp->pdev->dev;
422 int major, minor;
423
424 /* check firmware type */
425 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
426 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
427 return -EINVAL;
428 }
429
430 /* save firmware version for ethtool */
431 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
432
433 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
434
435 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
436 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
437 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
438 MXGEFW_VERSION_MINOR);
439 return -EINVAL;
440 }
441 return 0;
442}
443
444static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
445{
446 unsigned crc, reread_crc;
447 const struct firmware *fw;
448 struct device *dev = &mgp->pdev->dev;
449 struct mcp_gen_header *hdr;
450 size_t hdr_offset;
451 int status;
452
453 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
454 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
455 mgp->fw_name);
456 status = -EINVAL;
457 goto abort_with_nothing;
458 }
459
460 /* check size */
461
462 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
463 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
464 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
465 status = -EINVAL;
466 goto abort_with_fw;
467 }
468
469 /* check id */
470 hdr_offset = ntohl(*(u32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
471 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
472 dev_err(dev, "Bad firmware file\n");
473 status = -EINVAL;
474 goto abort_with_fw;
475 }
476 hdr = (void *)(fw->data + hdr_offset);
477
478 status = myri10ge_validate_firmware(mgp, hdr);
479 if (status != 0)
480 goto abort_with_fw;
481
482 crc = crc32(~0, fw->data, fw->size);
483 memcpy_toio(mgp->sram + MYRI10GE_FW_OFFSET, fw->data, fw->size);
484 /* corruption checking is good for parity recovery and buggy chipset */
485 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
486 reread_crc = crc32(~0, fw->data, fw->size);
487 if (crc != reread_crc) {
488 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
489 (unsigned)fw->size, reread_crc, crc);
490 status = -EIO;
491 goto abort_with_fw;
492 }
493 *size = (u32) fw->size;
494
495abort_with_fw:
496 release_firmware(fw);
497
498abort_with_nothing:
499 return status;
500}
501
502static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
503{
504 struct mcp_gen_header *hdr;
505 struct device *dev = &mgp->pdev->dev;
506 const size_t bytes = sizeof(struct mcp_gen_header);
507 size_t hdr_offset;
508 int status;
509
510 /* find running firmware header */
511 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
512
513 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
514 dev_err(dev, "Running firmware has bad header offset (%d)\n",
515 (int)hdr_offset);
516 return -EIO;
517 }
518
519 /* copy header of running firmware from SRAM to host memory to
520 * validate firmware */
521 hdr = kmalloc(bytes, GFP_KERNEL);
522 if (hdr == NULL) {
523 dev_err(dev, "could not malloc firmware hdr\n");
524 return -ENOMEM;
525 }
526 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
527 status = myri10ge_validate_firmware(mgp, hdr);
528 kfree(hdr);
529 return status;
530}
531
532static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
533{
534 char __iomem *submit;
535 u32 buf[16];
536 u32 dma_low, dma_high, size;
537 int status, i;
538
539 status = myri10ge_load_hotplug_firmware(mgp, &size);
540 if (status) {
541 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
542
543 /* Do not attempt to adopt firmware if there
544 * was a bad crc */
545 if (status == -EIO)
546 return status;
547
548 status = myri10ge_adopt_running_firmware(mgp);
549 if (status != 0) {
550 dev_err(&mgp->pdev->dev,
551 "failed to adopt running firmware\n");
552 return status;
553 }
554 dev_info(&mgp->pdev->dev,
555 "Successfully adopted running firmware\n");
556 if (mgp->tx.boundary == 4096) {
557 dev_warn(&mgp->pdev->dev,
558 "Using firmware currently running on NIC"
559 ". For optimal\n");
560 dev_warn(&mgp->pdev->dev,
561 "performance consider loading optimized "
562 "firmware\n");
563 dev_warn(&mgp->pdev->dev, "via hotplug\n");
564 }
565
566 mgp->fw_name = "adopted";
567 mgp->tx.boundary = 2048;
568 return status;
569 }
570
571 /* clear confirmation addr */
572 mgp->cmd->data = 0;
573 mb();
574
575 /* send a reload command to the bootstrap MCP, and wait for the
576 * response in the confirmation address. The firmware should
577 * write a -1 there to indicate it is alive and well
578 */
579 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
580 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
581
582 buf[0] = htonl(dma_high); /* confirm addr MSW */
583 buf[1] = htonl(dma_low); /* confirm addr LSW */
584 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
585
586 /* FIX: All newest firmware should un-protect the bottom of
587 * the sram before handoff. However, the very first interfaces
588 * do not. Therefore the handoff copy must skip the first 8 bytes
589 */
590 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
591 buf[4] = htonl(size - 8); /* length of code */
592 buf[5] = htonl(8); /* where to copy to */
593 buf[6] = htonl(0); /* where to jump to */
594
595 submit = mgp->sram + 0xfc0000;
596
597 myri10ge_pio_copy(submit, &buf, sizeof(buf));
598 mb();
599 msleep(1);
600 mb();
601 i = 0;
602 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
603 msleep(1);
604 i++;
605 }
606 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
607 dev_err(&mgp->pdev->dev, "handoff failed\n");
608 return -ENXIO;
609 }
610 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
611 myri10ge_dummy_rdma(mgp, mgp->tx.boundary != 4096);
612
613 return 0;
614}
615
616static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
617{
618 struct myri10ge_cmd cmd;
619 int status;
620
621 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
622 | (addr[2] << 8) | addr[3]);
623
624 cmd.data1 = ((addr[4] << 8) | (addr[5]));
625
626 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
627 return status;
628}
629
630static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
631{
632 struct myri10ge_cmd cmd;
633 int status, ctl;
634
635 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
636 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
637
638 if (status) {
639 printk(KERN_ERR
640 "myri10ge: %s: Failed to set flow control mode\n",
641 mgp->dev->name);
642 return status;
643 }
644 mgp->pause = pause;
645 return 0;
646}
647
648static void
649myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
650{
651 struct myri10ge_cmd cmd;
652 int status, ctl;
653
654 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
655 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
656 if (status)
657 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
658 mgp->dev->name);
659}
660
661static int myri10ge_reset(struct myri10ge_priv *mgp)
662{
663 struct myri10ge_cmd cmd;
664 int status;
665 size_t bytes;
666 u32 len;
667
668 /* try to send a reset command to the card to see if it
669 * is alive */
670 memset(&cmd, 0, sizeof(cmd));
671 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
672 if (status != 0) {
673 dev_err(&mgp->pdev->dev, "failed reset\n");
674 return -ENXIO;
675 }
676
677 /* Now exchange information about interrupts */
678
679 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
680 memset(mgp->rx_done.entry, 0, bytes);
681 cmd.data0 = (u32) bytes;
682 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
683 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
684 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
685 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
686
687 status |=
688 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
689 mgp->irq_claim = (__iomem u32 *) (mgp->sram + cmd.data0);
690 if (!mgp->msi_enabled) {
691 status |= myri10ge_send_cmd
692 (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0);
693 mgp->irq_deassert = (__iomem u32 *) (mgp->sram + cmd.data0);
694
695 }
696 status |= myri10ge_send_cmd
697 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
698 mgp->intr_coal_delay_ptr = (__iomem u32 *) (mgp->sram + cmd.data0);
699 if (status != 0) {
700 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
701 return status;
702 }
703 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
704
705 /* Run a small DMA test.
706 * The magic multipliers to the length tell the firmware
707 * to do DMA read, write, or read+write tests. The
708 * results are returned in cmd.data0. The upper 16
709 * bits or the return is the number of transfers completed.
710 * The lower 16 bits is the time in 0.5us ticks that the
711 * transfers took to complete.
712 */
713
714 len = mgp->tx.boundary;
715
716 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
717 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
718 cmd.data2 = len * 0x10000;
719 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
720 if (status == 0)
721 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
722 (cmd.data0 & 0xffff);
723 else
724 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
725 status);
726 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
727 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
728 cmd.data2 = len * 0x1;
729 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
730 if (status == 0)
731 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
732 (cmd.data0 & 0xffff);
733 else
734 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
735 status);
736
737 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
738 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
739 cmd.data2 = len * 0x10001;
740 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
741 if (status == 0)
742 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
743 (cmd.data0 & 0xffff);
744 else
745 dev_warn(&mgp->pdev->dev,
746 "DMA read/write benchmark failed: %d\n", status);
747
748 memset(mgp->rx_done.entry, 0, bytes);
749
750 /* reset mcp/driver shared state back to 0 */
751 mgp->tx.req = 0;
752 mgp->tx.done = 0;
753 mgp->tx.pkt_start = 0;
754 mgp->tx.pkt_done = 0;
755 mgp->rx_big.cnt = 0;
756 mgp->rx_small.cnt = 0;
757 mgp->rx_done.idx = 0;
758 mgp->rx_done.cnt = 0;
759 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
760 myri10ge_change_promisc(mgp, 0, 0);
761 myri10ge_change_pause(mgp, mgp->pause);
762 return status;
763}
764
765static inline void
766myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
767 struct mcp_kreq_ether_recv *src)
768{
769 u32 low;
770
771 low = src->addr_low;
772 src->addr_low = DMA_32BIT_MASK;
773 myri10ge_pio_copy(dst, src, 8 * sizeof(*src));
774 mb();
775 src->addr_low = low;
776 __raw_writel(low, &dst->addr_low);
777 mb();
778}
779
780/*
781 * Set of routunes to get a new receive buffer. Any buffer which
782 * crosses a 4KB boundary must start on a 4KB boundary due to PCIe
783 * wdma restrictions. We also try to align any smaller allocation to
784 * at least a 16 byte boundary for efficiency. We assume the linux
785 * memory allocator works by powers of 2, and will not return memory
786 * smaller than 2KB which crosses a 4KB boundary. If it does, we fall
787 * back to allocating 2x as much space as required.
788 *
789 * We intend to replace large (>4KB) skb allocations by using
790 * pages directly and building a fraglist in the near future.
791 */
792
793static inline struct sk_buff *myri10ge_alloc_big(int bytes)
794{
795 struct sk_buff *skb;
796 unsigned long data, roundup;
797
798 skb = dev_alloc_skb(bytes + 4096 + MXGEFW_PAD);
799 if (skb == NULL)
800 return NULL;
801
802 /* Correct skb->truesize so that socket buffer
803 * accounting is not confused the rounding we must
804 * do to satisfy alignment constraints.
805 */
806 skb->truesize -= 4096;
807
808 data = (unsigned long)(skb->data);
809 roundup = (-data) & (4095);
810 skb_reserve(skb, roundup);
811 return skb;
812}
813
814/* Allocate 2x as much space as required and use whichever portion
815 * does not cross a 4KB boundary */
816static inline struct sk_buff *myri10ge_alloc_small_safe(unsigned int bytes)
817{
818 struct sk_buff *skb;
819 unsigned long data, boundary;
820
821 skb = dev_alloc_skb(2 * (bytes + MXGEFW_PAD) - 1);
822 if (unlikely(skb == NULL))
823 return NULL;
824
825 /* Correct skb->truesize so that socket buffer
826 * accounting is not confused the rounding we must
827 * do to satisfy alignment constraints.
828 */
829 skb->truesize -= bytes + MXGEFW_PAD;
830
831 data = (unsigned long)(skb->data);
832 boundary = (data + 4095UL) & ~4095UL;
833 if ((boundary - data) >= (bytes + MXGEFW_PAD))
834 return skb;
835
836 skb_reserve(skb, boundary - data);
837 return skb;
838}
839
840/* Allocate just enough space, and verify that the allocated
841 * space does not cross a 4KB boundary */
842static inline struct sk_buff *myri10ge_alloc_small(int bytes)
843{
844 struct sk_buff *skb;
845 unsigned long roundup, data, end;
846
847 skb = dev_alloc_skb(bytes + 16 + MXGEFW_PAD);
848 if (unlikely(skb == NULL))
849 return NULL;
850
851 /* Round allocated buffer to 16 byte boundary */
852 data = (unsigned long)(skb->data);
853 roundup = (-data) & 15UL;
854 skb_reserve(skb, roundup);
855 /* Verify that the data buffer does not cross a page boundary */
856 data = (unsigned long)(skb->data);
857 end = data + bytes + MXGEFW_PAD - 1;
858 if (unlikely(((end >> 12) != (data >> 12)) && (data & 4095UL))) {
859 printk(KERN_NOTICE
860 "myri10ge_alloc_small: small skb crossed 4KB boundary\n");
861 myri10ge_skb_cross_4k = 1;
862 dev_kfree_skb_any(skb);
863 skb = myri10ge_alloc_small_safe(bytes);
864 }
865 return skb;
866}
867
868static inline int
869myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct pci_dev *pdev, int bytes,
870 int idx)
871{
872 struct sk_buff *skb;
873 dma_addr_t bus;
874 int len, retval = 0;
875
876 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */
877
878 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ )
879 skb = myri10ge_alloc_big(bytes);
880 else if (myri10ge_skb_cross_4k)
881 skb = myri10ge_alloc_small_safe(bytes);
882 else
883 skb = myri10ge_alloc_small(bytes);
884
885 if (unlikely(skb == NULL)) {
886 rx->alloc_fail++;
887 retval = -ENOBUFS;
888 goto done;
889 }
890
891 /* set len so that it only covers the area we
892 * need mapped for DMA */
893 len = bytes + MXGEFW_PAD;
894
895 bus = pci_map_single(pdev, skb->data, len, PCI_DMA_FROMDEVICE);
896 rx->info[idx].skb = skb;
897 pci_unmap_addr_set(&rx->info[idx], bus, bus);
898 pci_unmap_len_set(&rx->info[idx], len, len);
899 rx->shadow[idx].addr_low = htonl(MYRI10GE_LOWPART_TO_U32(bus));
900 rx->shadow[idx].addr_high = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
901
902done:
903 /* copy 8 descriptors (64-bytes) to the mcp at a time */
904 if ((idx & 7) == 7) {
905 if (rx->wc_fifo == NULL)
906 myri10ge_submit_8rx(&rx->lanai[idx - 7],
907 &rx->shadow[idx - 7]);
908 else {
909 mb();
910 myri10ge_pio_copy(rx->wc_fifo,
911 &rx->shadow[idx - 7], 64);
912 }
913 }
914 return retval;
915}
916
917static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum)
918{
919 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
920
921 if ((skb->protocol == ntohs(ETH_P_8021Q)) &&
922 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
923 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
924 skb->csum = hw_csum;
925 skb->ip_summed = CHECKSUM_HW;
926 }
927}
928
929static inline unsigned long
930myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
931 int bytes, int len, int csum)
932{
933 dma_addr_t bus;
934 struct sk_buff *skb;
935 int idx, unmap_len;
936
937 idx = rx->cnt & rx->mask;
938 rx->cnt++;
939
940 /* save a pointer to the received skb */
941 skb = rx->info[idx].skb;
942 bus = pci_unmap_addr(&rx->info[idx], bus);
943 unmap_len = pci_unmap_len(&rx->info[idx], len);
944
945 /* try to replace the received skb */
946 if (myri10ge_getbuf(rx, mgp->pdev, bytes, idx)) {
947 /* drop the frame -- the old skbuf is re-cycled */
948 mgp->stats.rx_dropped += 1;
949 return 0;
950 }
951
952 /* unmap the recvd skb */
953 pci_unmap_single(mgp->pdev, bus, unmap_len, PCI_DMA_FROMDEVICE);
954
955 /* mcp implicitly skips 1st bytes so that packet is properly
956 * aligned */
957 skb_reserve(skb, MXGEFW_PAD);
958
959 /* set the length of the frame */
960 skb_put(skb, len);
961
962 skb->protocol = eth_type_trans(skb, mgp->dev);
963 skb->dev = mgp->dev;
964 if (mgp->csum_flag) {
965 if ((skb->protocol == ntohs(ETH_P_IP)) ||
966 (skb->protocol == ntohs(ETH_P_IPV6))) {
967 skb->csum = ntohs((u16) csum);
968 skb->ip_summed = CHECKSUM_HW;
969 } else
970 myri10ge_vlan_ip_csum(skb, ntohs((u16) csum));
971 }
972
973 netif_receive_skb(skb);
974 mgp->dev->last_rx = jiffies;
975 return 1;
976}
977
978static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
979{
980 struct pci_dev *pdev = mgp->pdev;
981 struct myri10ge_tx_buf *tx = &mgp->tx;
982 struct sk_buff *skb;
983 int idx, len;
984 int limit = 0;
985
986 while (tx->pkt_done != mcp_index) {
987 idx = tx->done & tx->mask;
988 skb = tx->info[idx].skb;
989
990 /* Mark as free */
991 tx->info[idx].skb = NULL;
992 if (tx->info[idx].last) {
993 tx->pkt_done++;
994 tx->info[idx].last = 0;
995 }
996 tx->done++;
997 len = pci_unmap_len(&tx->info[idx], len);
998 pci_unmap_len_set(&tx->info[idx], len, 0);
999 if (skb) {
1000 mgp->stats.tx_bytes += skb->len;
1001 mgp->stats.tx_packets++;
1002 dev_kfree_skb_irq(skb);
1003 if (len)
1004 pci_unmap_single(pdev,
1005 pci_unmap_addr(&tx->info[idx],
1006 bus), len,
1007 PCI_DMA_TODEVICE);
1008 } else {
1009 if (len)
1010 pci_unmap_page(pdev,
1011 pci_unmap_addr(&tx->info[idx],
1012 bus), len,
1013 PCI_DMA_TODEVICE);
1014 }
1015
1016 /* limit potential for livelock by only handling
1017 * 2 full tx rings per call */
1018 if (unlikely(++limit > 2 * tx->mask))
1019 break;
1020 }
1021 /* start the queue if we've stopped it */
1022 if (netif_queue_stopped(mgp->dev)
1023 && tx->req - tx->done < (tx->mask >> 1)) {
1024 mgp->wake_queue++;
1025 netif_wake_queue(mgp->dev);
1026 }
1027}
1028
1029static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1030{
1031 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1032 unsigned long rx_bytes = 0;
1033 unsigned long rx_packets = 0;
1034 unsigned long rx_ok;
1035
1036 int idx = rx_done->idx;
1037 int cnt = rx_done->cnt;
1038 u16 length;
1039 u16 checksum;
1040
1041 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1042 length = ntohs(rx_done->entry[idx].length);
1043 rx_done->entry[idx].length = 0;
1044 checksum = ntohs(rx_done->entry[idx].checksum);
1045 if (length <= mgp->small_bytes)
1046 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1047 mgp->small_bytes,
1048 length, checksum);
1049 else
1050 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1051 mgp->dev->mtu + ETH_HLEN,
1052 length, checksum);
1053 rx_packets += rx_ok;
1054 rx_bytes += rx_ok * (unsigned long)length;
1055 cnt++;
1056 idx = cnt & (myri10ge_max_intr_slots - 1);
1057
1058 /* limit potential for livelock by only handling a
1059 * limited number of frames. */
1060 (*limit)--;
1061 }
1062 rx_done->idx = idx;
1063 rx_done->cnt = cnt;
1064 mgp->stats.rx_packets += rx_packets;
1065 mgp->stats.rx_bytes += rx_bytes;
1066}
1067
1068static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1069{
1070 struct mcp_irq_data *stats = mgp->fw_stats;
1071
1072 if (unlikely(stats->stats_updated)) {
1073 if (mgp->link_state != stats->link_up) {
1074 mgp->link_state = stats->link_up;
1075 if (mgp->link_state) {
1076 printk(KERN_INFO "myri10ge: %s: link up\n",
1077 mgp->dev->name);
1078 netif_carrier_on(mgp->dev);
1079 } else {
1080 printk(KERN_INFO "myri10ge: %s: link down\n",
1081 mgp->dev->name);
1082 netif_carrier_off(mgp->dev);
1083 }
1084 }
1085 if (mgp->rdma_tags_available !=
1086 ntohl(mgp->fw_stats->rdma_tags_available)) {
1087 mgp->rdma_tags_available =
1088 ntohl(mgp->fw_stats->rdma_tags_available);
1089 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1090 "%d tags left\n", mgp->dev->name,
1091 mgp->rdma_tags_available);
1092 }
1093 mgp->down_cnt += stats->link_down;
1094 if (stats->link_down)
1095 wake_up(&mgp->down_wq);
1096 }
1097}
1098
1099static int myri10ge_poll(struct net_device *netdev, int *budget)
1100{
1101 struct myri10ge_priv *mgp = netdev_priv(netdev);
1102 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1103 int limit, orig_limit, work_done;
1104
1105 /* process as many rx events as NAPI will allow */
1106 limit = min(*budget, netdev->quota);
1107 orig_limit = limit;
1108 myri10ge_clean_rx_done(mgp, &limit);
1109 work_done = orig_limit - limit;
1110 *budget -= work_done;
1111 netdev->quota -= work_done;
1112
1113 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1114 netif_rx_complete(netdev);
1115 __raw_writel(htonl(3), mgp->irq_claim);
1116 return 0;
1117 }
1118 return 1;
1119}
1120
1121static irqreturn_t myri10ge_intr(int irq, void *arg, struct pt_regs *regs)
1122{
1123 struct myri10ge_priv *mgp = arg;
1124 struct mcp_irq_data *stats = mgp->fw_stats;
1125 struct myri10ge_tx_buf *tx = &mgp->tx;
1126 u32 send_done_count;
1127 int i;
1128
1129 /* make sure it is our IRQ, and that the DMA has finished */
1130 if (unlikely(!stats->valid))
1131 return (IRQ_NONE);
1132
1133 /* low bit indicates receives are present, so schedule
1134 * napi poll handler */
1135 if (stats->valid & 1)
1136 netif_rx_schedule(mgp->dev);
1137
1138 if (!mgp->msi_enabled) {
1139 __raw_writel(0, mgp->irq_deassert);
1140 if (!myri10ge_deassert_wait)
1141 stats->valid = 0;
1142 mb();
1143 } else
1144 stats->valid = 0;
1145
1146 /* Wait for IRQ line to go low, if using INTx */
1147 i = 0;
1148 while (1) {
1149 i++;
1150 /* check for transmit completes and receives */
1151 send_done_count = ntohl(stats->send_done_count);
1152 if (send_done_count != tx->pkt_done)
1153 myri10ge_tx_done(mgp, (int)send_done_count);
1154 if (unlikely(i > myri10ge_max_irq_loops)) {
1155 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1156 mgp->dev->name);
1157 stats->valid = 0;
1158 schedule_work(&mgp->watchdog_work);
1159 }
1160 if (likely(stats->valid == 0))
1161 break;
1162 cpu_relax();
1163 barrier();
1164 }
1165
1166 myri10ge_check_statblock(mgp);
1167
1168 __raw_writel(htonl(3), mgp->irq_claim + 1);
1169 return (IRQ_HANDLED);
1170}
1171
1172static int
1173myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1174{
1175 cmd->autoneg = AUTONEG_DISABLE;
1176 cmd->speed = SPEED_10000;
1177 cmd->duplex = DUPLEX_FULL;
1178 return 0;
1179}
1180
1181static void
1182myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1183{
1184 struct myri10ge_priv *mgp = netdev_priv(netdev);
1185
1186 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1187 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1188 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1189 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1190}
1191
1192static int
1193myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1194{
1195 struct myri10ge_priv *mgp = netdev_priv(netdev);
1196 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1197 return 0;
1198}
1199
1200static int
1201myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1202{
1203 struct myri10ge_priv *mgp = netdev_priv(netdev);
1204
1205 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1206 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1207 return 0;
1208}
1209
1210static void
1211myri10ge_get_pauseparam(struct net_device *netdev,
1212 struct ethtool_pauseparam *pause)
1213{
1214 struct myri10ge_priv *mgp = netdev_priv(netdev);
1215
1216 pause->autoneg = 0;
1217 pause->rx_pause = mgp->pause;
1218 pause->tx_pause = mgp->pause;
1219}
1220
1221static int
1222myri10ge_set_pauseparam(struct net_device *netdev,
1223 struct ethtool_pauseparam *pause)
1224{
1225 struct myri10ge_priv *mgp = netdev_priv(netdev);
1226
1227 if (pause->tx_pause != mgp->pause)
1228 return myri10ge_change_pause(mgp, pause->tx_pause);
1229 if (pause->rx_pause != mgp->pause)
1230 return myri10ge_change_pause(mgp, pause->tx_pause);
1231 if (pause->autoneg != 0)
1232 return -EINVAL;
1233 return 0;
1234}
1235
1236static void
1237myri10ge_get_ringparam(struct net_device *netdev,
1238 struct ethtool_ringparam *ring)
1239{
1240 struct myri10ge_priv *mgp = netdev_priv(netdev);
1241
1242 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1243 ring->rx_max_pending = mgp->rx_big.mask + 1;
1244 ring->rx_jumbo_max_pending = 0;
1245 ring->tx_max_pending = mgp->rx_small.mask + 1;
1246 ring->rx_mini_pending = ring->rx_mini_max_pending;
1247 ring->rx_pending = ring->rx_max_pending;
1248 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1249 ring->tx_pending = ring->tx_max_pending;
1250}
1251
1252static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1253{
1254 struct myri10ge_priv *mgp = netdev_priv(netdev);
1255 if (mgp->csum_flag)
1256 return 1;
1257 else
1258 return 0;
1259}
1260
1261static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1262{
1263 struct myri10ge_priv *mgp = netdev_priv(netdev);
1264 if (csum_enabled)
1265 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1266 else
1267 mgp->csum_flag = 0;
1268 return 0;
1269}
1270
1271static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1272 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1273 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1274 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1275 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1276 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1277 "tx_heartbeat_errors", "tx_window_errors",
1278 /* device-specific stats */
1279 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1280 "serial_number", "tx_pkt_start", "tx_pkt_done",
1281 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1282 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1283 "link_up", "dropped_link_overflow", "dropped_link_error_or_filtered",
1284 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1285 "dropped_no_big_buffer"
1286};
1287
1288#define MYRI10GE_NET_STATS_LEN 21
1289#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1290
1291static void
1292myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1293{
1294 switch (stringset) {
1295 case ETH_SS_STATS:
1296 memcpy(data, *myri10ge_gstrings_stats,
1297 sizeof(myri10ge_gstrings_stats));
1298 break;
1299 }
1300}
1301
1302static int myri10ge_get_stats_count(struct net_device *netdev)
1303{
1304 return MYRI10GE_STATS_LEN;
1305}
1306
1307static void
1308myri10ge_get_ethtool_stats(struct net_device *netdev,
1309 struct ethtool_stats *stats, u64 * data)
1310{
1311 struct myri10ge_priv *mgp = netdev_priv(netdev);
1312 int i;
1313
1314 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1315 data[i] = ((unsigned long *)&mgp->stats)[i];
1316
1317 data[i++] = (unsigned int)mgp->read_dma;
1318 data[i++] = (unsigned int)mgp->write_dma;
1319 data[i++] = (unsigned int)mgp->read_write_dma;
1320 data[i++] = (unsigned int)mgp->serial_number;
1321 data[i++] = (unsigned int)mgp->tx.pkt_start;
1322 data[i++] = (unsigned int)mgp->tx.pkt_done;
1323 data[i++] = (unsigned int)mgp->tx.req;
1324 data[i++] = (unsigned int)mgp->tx.done;
1325 data[i++] = (unsigned int)mgp->rx_small.cnt;
1326 data[i++] = (unsigned int)mgp->rx_big.cnt;
1327 data[i++] = (unsigned int)mgp->wake_queue;
1328 data[i++] = (unsigned int)mgp->stop_queue;
1329 data[i++] = (unsigned int)mgp->watchdog_resets;
1330 data[i++] = (unsigned int)mgp->tx_linearized;
1331 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1332 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1333 data[i++] =
1334 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1335 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1336 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1337 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1338 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1339}
1340
1341static struct ethtool_ops myri10ge_ethtool_ops = {
1342 .get_settings = myri10ge_get_settings,
1343 .get_drvinfo = myri10ge_get_drvinfo,
1344 .get_coalesce = myri10ge_get_coalesce,
1345 .set_coalesce = myri10ge_set_coalesce,
1346 .get_pauseparam = myri10ge_get_pauseparam,
1347 .set_pauseparam = myri10ge_set_pauseparam,
1348 .get_ringparam = myri10ge_get_ringparam,
1349 .get_rx_csum = myri10ge_get_rx_csum,
1350 .set_rx_csum = myri10ge_set_rx_csum,
1351 .get_tx_csum = ethtool_op_get_tx_csum,
1352 .set_tx_csum = ethtool_op_set_tx_csum,
1353 .get_sg = ethtool_op_get_sg,
1354 .set_sg = ethtool_op_set_sg,
1355#ifdef NETIF_F_TSO
1356 .get_tso = ethtool_op_get_tso,
1357 .set_tso = ethtool_op_set_tso,
1358#endif
1359 .get_strings = myri10ge_get_strings,
1360 .get_stats_count = myri10ge_get_stats_count,
1361 .get_ethtool_stats = myri10ge_get_ethtool_stats
1362};
1363
1364static int myri10ge_allocate_rings(struct net_device *dev)
1365{
1366 struct myri10ge_priv *mgp;
1367 struct myri10ge_cmd cmd;
1368 int tx_ring_size, rx_ring_size;
1369 int tx_ring_entries, rx_ring_entries;
1370 int i, status;
1371 size_t bytes;
1372
1373 mgp = netdev_priv(dev);
1374
1375 /* get ring sizes */
1376
1377 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1378 tx_ring_size = cmd.data0;
1379 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1380 rx_ring_size = cmd.data0;
1381
1382 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1383 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1384 mgp->tx.mask = tx_ring_entries - 1;
1385 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1386
1387 /* allocate the host shadow rings */
1388
1389 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1390 * sizeof(*mgp->tx.req_list);
1391 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1392 if (mgp->tx.req_bytes == NULL)
1393 goto abort_with_nothing;
1394
1395 /* ensure req_list entries are aligned to 8 bytes */
1396 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1397 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1398
1399 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1400 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1401 if (mgp->rx_small.shadow == NULL)
1402 goto abort_with_tx_req_bytes;
1403
1404 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1405 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1406 if (mgp->rx_big.shadow == NULL)
1407 goto abort_with_rx_small_shadow;
1408
1409 /* allocate the host info rings */
1410
1411 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1412 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1413 if (mgp->tx.info == NULL)
1414 goto abort_with_rx_big_shadow;
1415
1416 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1417 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1418 if (mgp->rx_small.info == NULL)
1419 goto abort_with_tx_info;
1420
1421 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1422 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1423 if (mgp->rx_big.info == NULL)
1424 goto abort_with_rx_small_info;
1425
1426 /* Fill the receive rings */
1427
1428 for (i = 0; i <= mgp->rx_small.mask; i++) {
1429 status = myri10ge_getbuf(&mgp->rx_small, mgp->pdev,
1430 mgp->small_bytes, i);
1431 if (status) {
1432 printk(KERN_ERR
1433 "myri10ge: %s: alloced only %d small bufs\n",
1434 dev->name, i);
1435 goto abort_with_rx_small_ring;
1436 }
1437 }
1438
1439 for (i = 0; i <= mgp->rx_big.mask; i++) {
1440 status =
1441 myri10ge_getbuf(&mgp->rx_big, mgp->pdev,
1442 dev->mtu + ETH_HLEN, i);
1443 if (status) {
1444 printk(KERN_ERR
1445 "myri10ge: %s: alloced only %d big bufs\n",
1446 dev->name, i);
1447 goto abort_with_rx_big_ring;
1448 }
1449 }
1450
1451 return 0;
1452
1453abort_with_rx_big_ring:
1454 for (i = 0; i <= mgp->rx_big.mask; i++) {
1455 if (mgp->rx_big.info[i].skb != NULL)
1456 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1457 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1458 pci_unmap_single(mgp->pdev,
1459 pci_unmap_addr(&mgp->rx_big.info[i],
1460 bus),
1461 pci_unmap_len(&mgp->rx_big.info[i],
1462 len),
1463 PCI_DMA_FROMDEVICE);
1464 }
1465
1466abort_with_rx_small_ring:
1467 for (i = 0; i <= mgp->rx_small.mask; i++) {
1468 if (mgp->rx_small.info[i].skb != NULL)
1469 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1470 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1471 pci_unmap_single(mgp->pdev,
1472 pci_unmap_addr(&mgp->rx_small.info[i],
1473 bus),
1474 pci_unmap_len(&mgp->rx_small.info[i],
1475 len),
1476 PCI_DMA_FROMDEVICE);
1477 }
1478 kfree(mgp->rx_big.info);
1479
1480abort_with_rx_small_info:
1481 kfree(mgp->rx_small.info);
1482
1483abort_with_tx_info:
1484 kfree(mgp->tx.info);
1485
1486abort_with_rx_big_shadow:
1487 kfree(mgp->rx_big.shadow);
1488
1489abort_with_rx_small_shadow:
1490 kfree(mgp->rx_small.shadow);
1491
1492abort_with_tx_req_bytes:
1493 kfree(mgp->tx.req_bytes);
1494 mgp->tx.req_bytes = NULL;
1495 mgp->tx.req_list = NULL;
1496
1497abort_with_nothing:
1498 return status;
1499}
1500
1501static void myri10ge_free_rings(struct net_device *dev)
1502{
1503 struct myri10ge_priv *mgp;
1504 struct sk_buff *skb;
1505 struct myri10ge_tx_buf *tx;
1506 int i, len, idx;
1507
1508 mgp = netdev_priv(dev);
1509
1510 for (i = 0; i <= mgp->rx_big.mask; i++) {
1511 if (mgp->rx_big.info[i].skb != NULL)
1512 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1513 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1514 pci_unmap_single(mgp->pdev,
1515 pci_unmap_addr(&mgp->rx_big.info[i],
1516 bus),
1517 pci_unmap_len(&mgp->rx_big.info[i],
1518 len),
1519 PCI_DMA_FROMDEVICE);
1520 }
1521
1522 for (i = 0; i <= mgp->rx_small.mask; i++) {
1523 if (mgp->rx_small.info[i].skb != NULL)
1524 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1525 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1526 pci_unmap_single(mgp->pdev,
1527 pci_unmap_addr(&mgp->rx_small.info[i],
1528 bus),
1529 pci_unmap_len(&mgp->rx_small.info[i],
1530 len),
1531 PCI_DMA_FROMDEVICE);
1532 }
1533
1534 tx = &mgp->tx;
1535 while (tx->done != tx->req) {
1536 idx = tx->done & tx->mask;
1537 skb = tx->info[idx].skb;
1538
1539 /* Mark as free */
1540 tx->info[idx].skb = NULL;
1541 tx->done++;
1542 len = pci_unmap_len(&tx->info[idx], len);
1543 pci_unmap_len_set(&tx->info[idx], len, 0);
1544 if (skb) {
1545 mgp->stats.tx_dropped++;
1546 dev_kfree_skb_any(skb);
1547 if (len)
1548 pci_unmap_single(mgp->pdev,
1549 pci_unmap_addr(&tx->info[idx],
1550 bus), len,
1551 PCI_DMA_TODEVICE);
1552 } else {
1553 if (len)
1554 pci_unmap_page(mgp->pdev,
1555 pci_unmap_addr(&tx->info[idx],
1556 bus), len,
1557 PCI_DMA_TODEVICE);
1558 }
1559 }
1560 kfree(mgp->rx_big.info);
1561
1562 kfree(mgp->rx_small.info);
1563
1564 kfree(mgp->tx.info);
1565
1566 kfree(mgp->rx_big.shadow);
1567
1568 kfree(mgp->rx_small.shadow);
1569
1570 kfree(mgp->tx.req_bytes);
1571 mgp->tx.req_bytes = NULL;
1572 mgp->tx.req_list = NULL;
1573}
1574
1575static int myri10ge_open(struct net_device *dev)
1576{
1577 struct myri10ge_priv *mgp;
1578 struct myri10ge_cmd cmd;
1579 int status, big_pow2;
1580
1581 mgp = netdev_priv(dev);
1582
1583 if (mgp->running != MYRI10GE_ETH_STOPPED)
1584 return -EBUSY;
1585
1586 mgp->running = MYRI10GE_ETH_STARTING;
1587 status = myri10ge_reset(mgp);
1588 if (status != 0) {
1589 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1590 mgp->running = MYRI10GE_ETH_STOPPED;
1591 return -ENXIO;
1592 }
1593
1594 /* decide what small buffer size to use. For good TCP rx
1595 * performance, it is important to not receive 1514 byte
1596 * frames into jumbo buffers, as it confuses the socket buffer
1597 * accounting code, leading to drops and erratic performance.
1598 */
1599
1600 if (dev->mtu <= ETH_DATA_LEN)
1601 mgp->small_bytes = 128; /* enough for a TCP header */
1602 else
1603 mgp->small_bytes = ETH_FRAME_LEN; /* enough for an ETH_DATA_LEN frame */
1604
1605 /* Override the small buffer size? */
1606 if (myri10ge_small_bytes > 0)
1607 mgp->small_bytes = myri10ge_small_bytes;
1608
1609 /* If the user sets an obscenely small MTU, adjust the small
1610 * bytes down to nearly nothing */
1611 if (mgp->small_bytes >= (dev->mtu + ETH_HLEN))
1612 mgp->small_bytes = 64;
1613
1614 /* get the lanai pointers to the send and receive rings */
1615
1616 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1617 mgp->tx.lanai =
1618 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1619
1620 status |=
1621 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1622 mgp->rx_small.lanai =
1623 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1624
1625 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1626 mgp->rx_big.lanai =
1627 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1628
1629 if (status != 0) {
1630 printk(KERN_ERR
1631 "myri10ge: %s: failed to get ring sizes or locations\n",
1632 dev->name);
1633 mgp->running = MYRI10GE_ETH_STOPPED;
1634 return -ENXIO;
1635 }
1636
1637 if (mgp->mtrr >= 0) {
1638 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + 0x200000;
1639 mgp->rx_small.wc_fifo = (u8 __iomem *) mgp->sram + 0x300000;
1640 mgp->rx_big.wc_fifo = (u8 __iomem *) mgp->sram + 0x340000;
1641 } else {
1642 mgp->tx.wc_fifo = NULL;
1643 mgp->rx_small.wc_fifo = NULL;
1644 mgp->rx_big.wc_fifo = NULL;
1645 }
1646
1647 status = myri10ge_allocate_rings(dev);
1648 if (status != 0)
1649 goto abort_with_nothing;
1650
1651 /* Firmware needs the big buff size as a power of 2. Lie and
1652 * tell him the buffer is larger, because we only use 1
1653 * buffer/pkt, and the mtu will prevent overruns.
1654 */
1655 big_pow2 = dev->mtu + ETH_HLEN + MXGEFW_PAD;
1656 while ((big_pow2 & (big_pow2 - 1)) != 0)
1657 big_pow2++;
1658
1659 /* now give firmware buffers sizes, and MTU */
1660 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1661 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1662 cmd.data0 = mgp->small_bytes;
1663 status |=
1664 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1665 cmd.data0 = big_pow2;
1666 status |=
1667 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1668 if (status) {
1669 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1670 dev->name);
1671 goto abort_with_rings;
1672 }
1673
1674 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1675 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1676 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA, &cmd, 0);
1677 if (status) {
1678 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1679 dev->name);
1680 goto abort_with_rings;
1681 }
1682
1683 mgp->link_state = -1;
1684 mgp->rdma_tags_available = 15;
1685
1686 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1687
1688 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1689 if (status) {
1690 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1691 dev->name);
1692 goto abort_with_rings;
1693 }
1694
1695 mgp->wake_queue = 0;
1696 mgp->stop_queue = 0;
1697 mgp->running = MYRI10GE_ETH_RUNNING;
1698 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1699 add_timer(&mgp->watchdog_timer);
1700 netif_wake_queue(dev);
1701 return 0;
1702
1703abort_with_rings:
1704 myri10ge_free_rings(dev);
1705
1706abort_with_nothing:
1707 mgp->running = MYRI10GE_ETH_STOPPED;
1708 return -ENOMEM;
1709}
1710
1711static int myri10ge_close(struct net_device *dev)
1712{
1713 struct myri10ge_priv *mgp;
1714 struct myri10ge_cmd cmd;
1715 int status, old_down_cnt;
1716
1717 mgp = netdev_priv(dev);
1718
1719 if (mgp->running != MYRI10GE_ETH_RUNNING)
1720 return 0;
1721
1722 if (mgp->tx.req_bytes == NULL)
1723 return 0;
1724
1725 del_timer_sync(&mgp->watchdog_timer);
1726 mgp->running = MYRI10GE_ETH_STOPPING;
1727 netif_poll_disable(mgp->dev);
1728 netif_carrier_off(dev);
1729 netif_stop_queue(dev);
1730 old_down_cnt = mgp->down_cnt;
1731 mb();
1732 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1733 if (status)
1734 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1735 dev->name);
1736
1737 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1738 if (old_down_cnt == mgp->down_cnt)
1739 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1740
1741 netif_tx_disable(dev);
1742
1743 myri10ge_free_rings(dev);
1744
1745 mgp->running = MYRI10GE_ETH_STOPPED;
1746 return 0;
1747}
1748
1749/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1750 * backwards one at a time and handle ring wraps */
1751
1752static inline void
1753myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1754 struct mcp_kreq_ether_send *src, int cnt)
1755{
1756 int idx, starting_slot;
1757 starting_slot = tx->req;
1758 while (cnt > 1) {
1759 cnt--;
1760 idx = (starting_slot + cnt) & tx->mask;
1761 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1762 mb();
1763 }
1764}
1765
1766/*
1767 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1768 * at most 32 bytes at a time, so as to avoid involving the software
1769 * pio handler in the nic. We re-write the first segment's flags
1770 * to mark them valid only after writing the entire chain.
1771 */
1772
1773static inline void
1774myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1775 int cnt)
1776{
1777 int idx, i;
1778 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1779 struct mcp_kreq_ether_send *srcp;
1780 u8 last_flags;
1781
1782 idx = tx->req & tx->mask;
1783
1784 last_flags = src->flags;
1785 src->flags = 0;
1786 mb();
1787 dst = dstp = &tx->lanai[idx];
1788 srcp = src;
1789
1790 if ((idx + cnt) < tx->mask) {
1791 for (i = 0; i < (cnt - 1); i += 2) {
1792 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1793 mb(); /* force write every 32 bytes */
1794 srcp += 2;
1795 dstp += 2;
1796 }
1797 } else {
1798 /* submit all but the first request, and ensure
1799 * that it is submitted below */
1800 myri10ge_submit_req_backwards(tx, src, cnt);
1801 i = 0;
1802 }
1803 if (i < cnt) {
1804 /* submit the first request */
1805 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1806 mb(); /* barrier before setting valid flag */
1807 }
1808
1809 /* re-write the last 32-bits with the valid flags */
1810 src->flags = last_flags;
1811 __raw_writel(*((u32 *) src + 3), (u32 __iomem *) dst + 3);
1812 tx->req += cnt;
1813 mb();
1814}
1815
1816static inline void
1817myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1818 struct mcp_kreq_ether_send *src, int cnt)
1819{
1820 tx->req += cnt;
1821 mb();
1822 while (cnt >= 4) {
1823 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1824 mb();
1825 src += 4;
1826 cnt -= 4;
1827 }
1828 if (cnt > 0) {
1829 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1830 * needs to be so that we don't overrun it */
1831 myri10ge_pio_copy(tx->wc_fifo + (cnt << 18), src, 64);
1832 mb();
1833 }
1834}
1835
1836/*
1837 * Transmit a packet. We need to split the packet so that a single
1838 * segment does not cross myri10ge->tx.boundary, so this makes segment
1839 * counting tricky. So rather than try to count segments up front, we
1840 * just give up if there are too few segments to hold a reasonably
1841 * fragmented packet currently available. If we run
1842 * out of segments while preparing a packet for DMA, we just linearize
1843 * it and try again.
1844 */
1845
1846static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1847{
1848 struct myri10ge_priv *mgp = netdev_priv(dev);
1849 struct mcp_kreq_ether_send *req;
1850 struct myri10ge_tx_buf *tx = &mgp->tx;
1851 struct skb_frag_struct *frag;
1852 dma_addr_t bus;
1853 u32 low, high_swapped;
1854 unsigned int len;
1855 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1856 u16 pseudo_hdr_offset, cksum_offset;
1857 int cum_len, seglen, boundary, rdma_count;
1858 u8 flags, odd_flag;
1859
1860again:
1861 req = tx->req_list;
1862 avail = tx->mask - 1 - (tx->req - tx->done);
1863
1864 mss = 0;
1865 max_segments = MXGEFW_MAX_SEND_DESC;
1866
1867#ifdef NETIF_F_TSO
1868 if (skb->len > (dev->mtu + ETH_HLEN)) {
1869 mss = skb_shinfo(skb)->tso_size;
1870 if (mss != 0)
1871 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1872 }
1873#endif /*NETIF_F_TSO */
1874
1875 if ((unlikely(avail < max_segments))) {
1876 /* we are out of transmit resources */
1877 mgp->stop_queue++;
1878 netif_stop_queue(dev);
1879 return 1;
1880 }
1881
1882 /* Setup checksum offloading, if needed */
1883 cksum_offset = 0;
1884 pseudo_hdr_offset = 0;
1885 odd_flag = 0;
1886 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1887 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1888 cksum_offset = (skb->h.raw - skb->data);
1889 pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data;
1890 /* If the headers are excessively large, then we must
1891 * fall back to a software checksum */
1892 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
1893 if (skb_checksum_help(skb, 0))
1894 goto drop;
1895 cksum_offset = 0;
1896 pseudo_hdr_offset = 0;
1897 } else {
1898 pseudo_hdr_offset = htons(pseudo_hdr_offset);
1899 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
1900 flags |= MXGEFW_FLAGS_CKSUM;
1901 }
1902 }
1903
1904 cum_len = 0;
1905
1906#ifdef NETIF_F_TSO
1907 if (mss) { /* TSO */
1908 /* this removes any CKSUM flag from before */
1909 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
1910
1911 /* negative cum_len signifies to the
1912 * send loop that we are still in the
1913 * header portion of the TSO packet.
1914 * TSO header must be at most 134 bytes long */
1915 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1916
1917 /* for TSO, pseudo_hdr_offset holds mss.
1918 * The firmware figures out where to put
1919 * the checksum by parsing the header. */
1920 pseudo_hdr_offset = htons(mss);
1921 } else
1922#endif /*NETIF_F_TSO */
1923 /* Mark small packets, and pad out tiny packets */
1924 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
1925 flags |= MXGEFW_FLAGS_SMALL;
1926
1927 /* pad frames to at least ETH_ZLEN bytes */
1928 if (unlikely(skb->len < ETH_ZLEN)) {
1929 skb = skb_padto(skb, ETH_ZLEN);
1930 if (skb == NULL) {
1931 /* The packet is gone, so we must
1932 * return 0 */
1933 mgp->stats.tx_dropped += 1;
1934 return 0;
1935 }
1936 /* adjust the len to account for the zero pad
1937 * so that the nic can know how long it is */
1938 skb->len = ETH_ZLEN;
1939 }
1940 }
1941
1942 /* map the skb for DMA */
1943 len = skb->len - skb->data_len;
1944 idx = tx->req & tx->mask;
1945 tx->info[idx].skb = skb;
1946 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
1947 pci_unmap_addr_set(&tx->info[idx], bus, bus);
1948 pci_unmap_len_set(&tx->info[idx], len, len);
1949
1950 frag_cnt = skb_shinfo(skb)->nr_frags;
1951 frag_idx = 0;
1952 count = 0;
1953 rdma_count = 0;
1954
1955 /* "rdma_count" is the number of RDMAs belonging to the
1956 * current packet BEFORE the current send request. For
1957 * non-TSO packets, this is equal to "count".
1958 * For TSO packets, rdma_count needs to be reset
1959 * to 0 after a segment cut.
1960 *
1961 * The rdma_count field of the send request is
1962 * the number of RDMAs of the packet starting at
1963 * that request. For TSO send requests with one ore more cuts
1964 * in the middle, this is the number of RDMAs starting
1965 * after the last cut in the request. All previous
1966 * segments before the last cut implicitly have 1 RDMA.
1967 *
1968 * Since the number of RDMAs is not known beforehand,
1969 * it must be filled-in retroactively - after each
1970 * segmentation cut or at the end of the entire packet.
1971 */
1972
1973 while (1) {
1974 /* Break the SKB or Fragment up into pieces which
1975 * do not cross mgp->tx.boundary */
1976 low = MYRI10GE_LOWPART_TO_U32(bus);
1977 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
1978 while (len) {
1979 u8 flags_next;
1980 int cum_len_next;
1981
1982 if (unlikely(count == max_segments))
1983 goto abort_linearize;
1984
1985 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
1986 seglen = boundary - low;
1987 if (seglen > len)
1988 seglen = len;
1989 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
1990 cum_len_next = cum_len + seglen;
1991#ifdef NETIF_F_TSO
1992 if (mss) { /* TSO */
1993 (req - rdma_count)->rdma_count = rdma_count + 1;
1994
1995 if (likely(cum_len >= 0)) { /* payload */
1996 int next_is_first, chop;
1997
1998 chop = (cum_len_next > mss);
1999 cum_len_next = cum_len_next % mss;
2000 next_is_first = (cum_len_next == 0);
2001 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2002 flags_next |= next_is_first *
2003 MXGEFW_FLAGS_FIRST;
2004 rdma_count |= -(chop | next_is_first);
2005 rdma_count += chop & !next_is_first;
2006 } else if (likely(cum_len_next >= 0)) { /* header ends */
2007 int small;
2008
2009 rdma_count = -1;
2010 cum_len_next = 0;
2011 seglen = -cum_len;
2012 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2013 flags_next = MXGEFW_FLAGS_TSO_PLD |
2014 MXGEFW_FLAGS_FIRST |
2015 (small * MXGEFW_FLAGS_SMALL);
2016 }
2017 }
2018#endif /* NETIF_F_TSO */
2019 req->addr_high = high_swapped;
2020 req->addr_low = htonl(low);
2021 req->pseudo_hdr_offset = pseudo_hdr_offset;
2022 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2023 req->rdma_count = 1;
2024 req->length = htons(seglen);
2025 req->cksum_offset = cksum_offset;
2026 req->flags = flags | ((cum_len & 1) * odd_flag);
2027
2028 low += seglen;
2029 len -= seglen;
2030 cum_len = cum_len_next;
2031 flags = flags_next;
2032 req++;
2033 count++;
2034 rdma_count++;
2035 if (unlikely(cksum_offset > seglen))
2036 cksum_offset -= seglen;
2037 else
2038 cksum_offset = 0;
2039 }
2040 if (frag_idx == frag_cnt)
2041 break;
2042
2043 /* map next fragment for DMA */
2044 idx = (count + tx->req) & tx->mask;
2045 frag = &skb_shinfo(skb)->frags[frag_idx];
2046 frag_idx++;
2047 len = frag->size;
2048 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2049 len, PCI_DMA_TODEVICE);
2050 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2051 pci_unmap_len_set(&tx->info[idx], len, len);
2052 }
2053
2054 (req - rdma_count)->rdma_count = rdma_count;
2055#ifdef NETIF_F_TSO
2056 if (mss)
2057 do {
2058 req--;
2059 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2060 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2061 MXGEFW_FLAGS_FIRST)));
2062#endif
2063 idx = ((count - 1) + tx->req) & tx->mask;
2064 tx->info[idx].last = 1;
2065 if (tx->wc_fifo == NULL)
2066 myri10ge_submit_req(tx, tx->req_list, count);
2067 else
2068 myri10ge_submit_req_wc(tx, tx->req_list, count);
2069 tx->pkt_start++;
2070 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2071 mgp->stop_queue++;
2072 netif_stop_queue(dev);
2073 }
2074 dev->trans_start = jiffies;
2075 return 0;
2076
2077abort_linearize:
2078 /* Free any DMA resources we've alloced and clear out the skb
2079 * slot so as to not trip up assertions, and to avoid a
2080 * double-free if linearizing fails */
2081
2082 last_idx = (idx + 1) & tx->mask;
2083 idx = tx->req & tx->mask;
2084 tx->info[idx].skb = NULL;
2085 do {
2086 len = pci_unmap_len(&tx->info[idx], len);
2087 if (len) {
2088 if (tx->info[idx].skb != NULL)
2089 pci_unmap_single(mgp->pdev,
2090 pci_unmap_addr(&tx->info[idx],
2091 bus), len,
2092 PCI_DMA_TODEVICE);
2093 else
2094 pci_unmap_page(mgp->pdev,
2095 pci_unmap_addr(&tx->info[idx],
2096 bus), len,
2097 PCI_DMA_TODEVICE);
2098 pci_unmap_len_set(&tx->info[idx], len, 0);
2099 tx->info[idx].skb = NULL;
2100 }
2101 idx = (idx + 1) & tx->mask;
2102 } while (idx != last_idx);
2103 if (skb_shinfo(skb)->tso_size) {
2104 printk(KERN_ERR
2105 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2106 mgp->dev->name);
2107 goto drop;
2108 }
2109
2110 if (skb_linearize(skb, GFP_ATOMIC))
2111 goto drop;
2112
2113 mgp->tx_linearized++;
2114 goto again;
2115
2116drop:
2117 dev_kfree_skb_any(skb);
2118 mgp->stats.tx_dropped += 1;
2119 return 0;
2120
2121}
2122
2123static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2124{
2125 struct myri10ge_priv *mgp = netdev_priv(dev);
2126 return &mgp->stats;
2127}
2128
2129static void myri10ge_set_multicast_list(struct net_device *dev)
2130{
2131 /* can be called from atomic contexts,
2132 * pass 1 to force atomicity in myri10ge_send_cmd() */
2133 myri10ge_change_promisc(netdev_priv(dev), dev->flags & IFF_PROMISC, 1);
2134}
2135
2136static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2137{
2138 struct sockaddr *sa = addr;
2139 struct myri10ge_priv *mgp = netdev_priv(dev);
2140 int status;
2141
2142 if (!is_valid_ether_addr(sa->sa_data))
2143 return -EADDRNOTAVAIL;
2144
2145 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2146 if (status != 0) {
2147 printk(KERN_ERR
2148 "myri10ge: %s: changing mac address failed with %d\n",
2149 dev->name, status);
2150 return status;
2151 }
2152
2153 /* change the dev structure */
2154 memcpy(dev->dev_addr, sa->sa_data, 6);
2155 return 0;
2156}
2157
2158static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2159{
2160 struct myri10ge_priv *mgp = netdev_priv(dev);
2161 int error = 0;
2162
2163 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2164 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2165 dev->name, new_mtu);
2166 return -EINVAL;
2167 }
2168 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2169 dev->name, dev->mtu, new_mtu);
2170 if (mgp->running) {
2171 /* if we change the mtu on an active device, we must
2172 * reset the device so the firmware sees the change */
2173 myri10ge_close(dev);
2174 dev->mtu = new_mtu;
2175 myri10ge_open(dev);
2176 } else
2177 dev->mtu = new_mtu;
2178
2179 return error;
2180}
2181
2182/*
2183 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2184 * Only do it if the bridge is a root port since we don't want to disturb
2185 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2186 */
2187
2188#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_PCIE 0x005d
2189
2190static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2191{
2192 struct pci_dev *bridge = mgp->pdev->bus->self;
2193 struct device *dev = &mgp->pdev->dev;
2194 unsigned cap;
2195 unsigned err_cap;
2196 u16 val;
2197 u8 ext_type;
2198 int ret;
2199
2200 if (!myri10ge_ecrc_enable || !bridge)
2201 return;
2202
2203 /* check that the bridge is a root port */
2204 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2205 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2206 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2207 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2208 if (myri10ge_ecrc_enable > 1) {
2209 struct pci_dev *old_bridge = bridge;
2210
2211 /* Walk the hierarchy up to the root port
2212 * where ECRC has to be enabled */
2213 do {
2214 bridge = bridge->bus->self;
2215 if (!bridge) {
2216 dev_err(dev,
2217 "Failed to find root port"
2218 " to force ECRC\n");
2219 return;
2220 }
2221 cap =
2222 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2223 pci_read_config_word(bridge,
2224 cap + PCI_CAP_FLAGS, &val);
2225 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2226 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2227
2228 dev_info(dev,
2229 "Forcing ECRC on non-root port %s"
2230 " (enabling on root port %s)\n",
2231 pci_name(old_bridge), pci_name(bridge));
2232 } else {
2233 dev_err(dev,
2234 "Not enabling ECRC on non-root port %s\n",
2235 pci_name(bridge));
2236 return;
2237 }
2238 }
2239
2240 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2241 /* nvidia ext cap is not always linked in ext cap chain */
2242 if (!cap
2243 && bridge->vendor == PCI_VENDOR_ID_NVIDIA
2244 && bridge->device == PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_PCIE)
2245 cap = 0x160;
2246
2247 if (!cap)
2248 return;
2249
2250 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2251 if (ret) {
2252 dev_err(dev, "failed reading ext-conf-space of %s\n",
2253 pci_name(bridge));
2254 dev_err(dev, "\t pci=nommconf in use? "
2255 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2256 return;
2257 }
2258 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2259 return;
2260
2261 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2262 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2263 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2264 mgp->tx.boundary = 4096;
2265 mgp->fw_name = myri10ge_fw_aligned;
2266}
2267
2268/*
2269 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2270 * when the PCI-E Completion packets are aligned on an 8-byte
2271 * boundary. Some PCI-E chip sets always align Completion packets; on
2272 * the ones that do not, the alignment can be enforced by enabling
2273 * ECRC generation (if supported).
2274 *
2275 * When PCI-E Completion packets are not aligned, it is actually more
2276 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2277 *
2278 * If the driver can neither enable ECRC nor verify that it has
2279 * already been enabled, then it must use a firmware image which works
2280 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2281 * should also ensure that it never gives the device a Read-DMA which is
2282 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2283 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2284 * firmware image, and set tx.boundary to 4KB.
2285 */
2286
2287#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
2288
2289static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2290{
2291 struct pci_dev *bridge = mgp->pdev->bus->self;
2292
2293 mgp->tx.boundary = 2048;
2294 mgp->fw_name = myri10ge_fw_unaligned;
2295
2296 if (myri10ge_force_firmware == 0) {
2297 myri10ge_enable_ecrc(mgp);
2298
2299 /* Check to see if the upstream bridge is known to
2300 * provide aligned completions */
2301 if (bridge
2302 /* ServerWorks HT2000/HT1000 */
2303 && bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2304 && bridge->device ==
2305 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) {
2306 dev_info(&mgp->pdev->dev,
2307 "Assuming aligned completions (0x%x:0x%x)\n",
2308 bridge->vendor, bridge->device);
2309 mgp->tx.boundary = 4096;
2310 mgp->fw_name = myri10ge_fw_aligned;
2311 }
2312 } else {
2313 if (myri10ge_force_firmware == 1) {
2314 dev_info(&mgp->pdev->dev,
2315 "Assuming aligned completions (forced)\n");
2316 mgp->tx.boundary = 4096;
2317 mgp->fw_name = myri10ge_fw_aligned;
2318 } else {
2319 dev_info(&mgp->pdev->dev,
2320 "Assuming unaligned completions (forced)\n");
2321 mgp->tx.boundary = 2048;
2322 mgp->fw_name = myri10ge_fw_unaligned;
2323 }
2324 }
2325 if (myri10ge_fw_name != NULL) {
2326 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2327 myri10ge_fw_name);
2328 mgp->fw_name = myri10ge_fw_name;
2329 }
2330}
2331
2332static void myri10ge_save_state(struct myri10ge_priv *mgp)
2333{
2334 struct pci_dev *pdev = mgp->pdev;
2335 int cap;
2336
2337 pci_save_state(pdev);
2338 /* now save PCIe and MSI state that Linux will not
2339 * save for us */
2340 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2341 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl);
2342 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2343 pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags);
2344}
2345
2346static void myri10ge_restore_state(struct myri10ge_priv *mgp)
2347{
2348 struct pci_dev *pdev = mgp->pdev;
2349 int cap;
2350
2351 /* restore PCIe and MSI state that linux will not */
2352 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2353 pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl);
2354 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2355 pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags);
2356
2357 pci_restore_state(pdev);
2358}
2359
2360#ifdef CONFIG_PM
2361
2362static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2363{
2364 struct myri10ge_priv *mgp;
2365 struct net_device *netdev;
2366
2367 mgp = pci_get_drvdata(pdev);
2368 if (mgp == NULL)
2369 return -EINVAL;
2370 netdev = mgp->dev;
2371
2372 netif_device_detach(netdev);
2373 if (netif_running(netdev)) {
2374 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2375 rtnl_lock();
2376 myri10ge_close(netdev);
2377 rtnl_unlock();
2378 }
2379 myri10ge_dummy_rdma(mgp, 0);
2380 free_irq(pdev->irq, mgp);
2381 myri10ge_save_state(mgp);
2382 pci_disable_device(pdev);
2383 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2384 return 0;
2385}
2386
2387static int myri10ge_resume(struct pci_dev *pdev)
2388{
2389 struct myri10ge_priv *mgp;
2390 struct net_device *netdev;
2391 int status;
2392 u16 vendor;
2393
2394 mgp = pci_get_drvdata(pdev);
2395 if (mgp == NULL)
2396 return -EINVAL;
2397 netdev = mgp->dev;
2398 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2399 msleep(5); /* give card time to respond */
2400 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2401 if (vendor == 0xffff) {
2402 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2403 mgp->dev->name);
2404 return -EIO;
2405 }
2406 myri10ge_restore_state(mgp);
2407 pci_enable_device(pdev);
2408 pci_set_master(pdev);
2409
2410 status = request_irq(pdev->irq, myri10ge_intr, SA_SHIRQ,
2411 netdev->name, mgp);
2412 if (status != 0) {
2413 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2414 goto abort_with_msi;
2415 }
2416
2417 myri10ge_reset(mgp);
2418 myri10ge_dummy_rdma(mgp, mgp->tx.boundary != 4096);
2419
2420 /* Save configuration space to be restored if the
2421 * nic resets due to a parity error */
2422 myri10ge_save_state(mgp);
2423
2424 if (netif_running(netdev)) {
2425 rtnl_lock();
2426 myri10ge_open(netdev);
2427 rtnl_unlock();
2428 }
2429 netif_device_attach(netdev);
2430
2431 return 0;
2432
2433abort_with_msi:
2434 return -EIO;
2435
2436}
2437
2438#endif /* CONFIG_PM */
2439
2440static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2441{
2442 struct pci_dev *pdev = mgp->pdev;
2443 int vs = mgp->vendor_specific_offset;
2444 u32 reboot;
2445
2446 /*enter read32 mode */
2447 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2448
2449 /*read REBOOT_STATUS (0xfffffff0) */
2450 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2451 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2452 return reboot;
2453}
2454
2455/*
2456 * This watchdog is used to check whether the board has suffered
2457 * from a parity error and needs to be recovered.
2458 */
2459static void myri10ge_watchdog(void *arg)
2460{
2461 struct myri10ge_priv *mgp = arg;
2462 u32 reboot;
2463 int status;
2464 u16 cmd, vendor;
2465
2466 mgp->watchdog_resets++;
2467 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2468 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2469 /* Bus master DMA disabled? Check to see
2470 * if the card rebooted due to a parity error
2471 * For now, just report it */
2472 reboot = myri10ge_read_reboot(mgp);
2473 printk(KERN_ERR
2474 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2475 mgp->dev->name, reboot);
2476 /*
2477 * A rebooted nic will come back with config space as
2478 * it was after power was applied to PCIe bus.
2479 * Attempt to restore config space which was saved
2480 * when the driver was loaded, or the last time the
2481 * nic was resumed from power saving mode.
2482 */
2483 myri10ge_restore_state(mgp);
2484 } else {
2485 /* if we get back -1's from our slot, perhaps somebody
2486 * powered off our card. Don't try to reset it in
2487 * this case */
2488 if (cmd == 0xffff) {
2489 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2490 if (vendor == 0xffff) {
2491 printk(KERN_ERR
2492 "myri10ge: %s: device disappeared!\n",
2493 mgp->dev->name);
2494 return;
2495 }
2496 }
2497 /* Perhaps it is a software error. Try to reset */
2498
2499 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2500 mgp->dev->name);
2501 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2502 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2503 mgp->tx.pkt_start, mgp->tx.pkt_done,
2504 (int)ntohl(mgp->fw_stats->send_done_count));
2505 msleep(2000);
2506 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2507 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2508 mgp->tx.pkt_start, mgp->tx.pkt_done,
2509 (int)ntohl(mgp->fw_stats->send_done_count));
2510 }
2511 rtnl_lock();
2512 myri10ge_close(mgp->dev);
2513 status = myri10ge_load_firmware(mgp);
2514 if (status != 0)
2515 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2516 mgp->dev->name);
2517 else
2518 myri10ge_open(mgp->dev);
2519 rtnl_unlock();
2520}
2521
2522/*
2523 * We use our own timer routine rather than relying upon
2524 * netdev->tx_timeout because we have a very large hardware transmit
2525 * queue. Due to the large queue, the netdev->tx_timeout function
2526 * cannot detect a NIC with a parity error in a timely fashion if the
2527 * NIC is lightly loaded.
2528 */
2529static void myri10ge_watchdog_timer(unsigned long arg)
2530{
2531 struct myri10ge_priv *mgp;
2532
2533 mgp = (struct myri10ge_priv *)arg;
2534 if (mgp->tx.req != mgp->tx.done &&
2535 mgp->tx.done == mgp->watchdog_tx_done)
2536 /* nic seems like it might be stuck.. */
2537 schedule_work(&mgp->watchdog_work);
2538 else
2539 /* rearm timer */
2540 mod_timer(&mgp->watchdog_timer,
2541 jiffies + myri10ge_watchdog_timeout * HZ);
2542
2543 mgp->watchdog_tx_done = mgp->tx.done;
2544}
2545
2546static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2547{
2548 struct net_device *netdev;
2549 struct myri10ge_priv *mgp;
2550 struct device *dev = &pdev->dev;
2551 size_t bytes;
2552 int i;
2553 int status = -ENXIO;
2554 int cap;
2555 int dac_enabled;
2556 u16 val;
2557
2558 netdev = alloc_etherdev(sizeof(*mgp));
2559 if (netdev == NULL) {
2560 dev_err(dev, "Could not allocate ethernet device\n");
2561 return -ENOMEM;
2562 }
2563
2564 mgp = netdev_priv(netdev);
2565 memset(mgp, 0, sizeof(*mgp));
2566 mgp->dev = netdev;
2567 mgp->pdev = pdev;
2568 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2569 mgp->pause = myri10ge_flow_control;
2570 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2571 init_waitqueue_head(&mgp->down_wq);
2572
2573 if (pci_enable_device(pdev)) {
2574 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2575 status = -ENODEV;
2576 goto abort_with_netdev;
2577 }
2578 myri10ge_select_firmware(mgp);
2579
2580 /* Find the vendor-specific cap so we can check
2581 * the reboot register later on */
2582 mgp->vendor_specific_offset
2583 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2584
2585 /* Set our max read request to 4KB */
2586 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2587 if (cap < 64) {
2588 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2589 goto abort_with_netdev;
2590 }
2591 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2592 if (status != 0) {
2593 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2594 status);
2595 goto abort_with_netdev;
2596 }
2597 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2598 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2599 if (status != 0) {
2600 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2601 status);
2602 goto abort_with_netdev;
2603 }
2604
2605 pci_set_master(pdev);
2606 dac_enabled = 1;
2607 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2608 if (status != 0) {
2609 dac_enabled = 0;
2610 dev_err(&pdev->dev,
2611 "64-bit pci address mask was refused, trying 32-bit");
2612 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2613 }
2614 if (status != 0) {
2615 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2616 goto abort_with_netdev;
2617 }
2618 mgp->cmd = pci_alloc_consistent(pdev, sizeof(*mgp->cmd), &mgp->cmd_bus);
2619 if (mgp->cmd == NULL)
2620 goto abort_with_netdev;
2621
2622 mgp->fw_stats = pci_alloc_consistent(pdev, sizeof(*mgp->fw_stats),
2623 &mgp->fw_stats_bus);
2624 if (mgp->fw_stats == NULL)
2625 goto abort_with_cmd;
2626
2627 mgp->board_span = pci_resource_len(pdev, 0);
2628 mgp->iomem_base = pci_resource_start(pdev, 0);
2629 mgp->mtrr = -1;
2630#ifdef CONFIG_MTRR
2631 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2632 MTRR_TYPE_WRCOMB, 1);
2633#endif
2634 /* Hack. need to get rid of these magic numbers */
2635 mgp->sram_size =
2636 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2637 if (mgp->sram_size > mgp->board_span) {
2638 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2639 mgp->board_span);
2640 goto abort_with_wc;
2641 }
2642 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2643 if (mgp->sram == NULL) {
2644 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2645 mgp->board_span, mgp->iomem_base);
2646 status = -ENXIO;
2647 goto abort_with_wc;
2648 }
2649 memcpy_fromio(mgp->eeprom_strings,
2650 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2651 MYRI10GE_EEPROM_STRINGS_SIZE);
2652 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2653 status = myri10ge_read_mac_addr(mgp);
2654 if (status)
2655 goto abort_with_ioremap;
2656
2657 for (i = 0; i < ETH_ALEN; i++)
2658 netdev->dev_addr[i] = mgp->mac_addr[i];
2659
2660 /* allocate rx done ring */
2661 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2662 mgp->rx_done.entry =
2663 pci_alloc_consistent(pdev, bytes, &mgp->rx_done.bus);
2664 if (mgp->rx_done.entry == NULL)
2665 goto abort_with_ioremap;
2666 memset(mgp->rx_done.entry, 0, bytes);
2667
2668 status = myri10ge_load_firmware(mgp);
2669 if (status != 0) {
2670 dev_err(&pdev->dev, "failed to load firmware\n");
2671 goto abort_with_rx_done;
2672 }
2673
2674 status = myri10ge_reset(mgp);
2675 if (status != 0) {
2676 dev_err(&pdev->dev, "failed reset\n");
2677 goto abort_with_firmware;
2678 }
2679
2680 if (myri10ge_msi) {
2681 status = pci_enable_msi(pdev);
2682 if (status != 0)
2683 dev_err(&pdev->dev,
2684 "Error %d setting up MSI; falling back to xPIC\n",
2685 status);
2686 else
2687 mgp->msi_enabled = 1;
2688 }
2689
2690 status = request_irq(pdev->irq, myri10ge_intr, SA_SHIRQ,
2691 netdev->name, mgp);
2692 if (status != 0) {
2693 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2694 goto abort_with_firmware;
2695 }
2696
2697 pci_set_drvdata(pdev, mgp);
2698 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2699 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2700 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2701 myri10ge_initial_mtu = 68;
2702 netdev->mtu = myri10ge_initial_mtu;
2703 netdev->open = myri10ge_open;
2704 netdev->stop = myri10ge_close;
2705 netdev->hard_start_xmit = myri10ge_xmit;
2706 netdev->get_stats = myri10ge_get_stats;
2707 netdev->base_addr = mgp->iomem_base;
2708 netdev->irq = pdev->irq;
2709 netdev->change_mtu = myri10ge_change_mtu;
2710 netdev->set_multicast_list = myri10ge_set_multicast_list;
2711 netdev->set_mac_address = myri10ge_set_mac_address;
2712 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2713 if (dac_enabled)
2714 netdev->features |= NETIF_F_HIGHDMA;
2715 netdev->poll = myri10ge_poll;
2716 netdev->weight = myri10ge_napi_weight;
2717
2718 /* Save configuration space to be restored if the
2719 * nic resets due to a parity error */
2720 myri10ge_save_state(mgp);
2721 /* Restore state immediately since pci_save_msi_state disables MSI */
2722 myri10ge_restore_state(mgp);
2723
2724 /* Setup the watchdog timer */
2725 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2726 (unsigned long)mgp);
2727
2728 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2729 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog, mgp);
2730 status = register_netdev(netdev);
2731 if (status != 0) {
2732 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2733 goto abort_with_irq;
2734 }
2735
2736 printk(KERN_INFO "myri10ge: %s: %s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2737 netdev->name, (mgp->msi_enabled ? "MSI" : "xPIC"),
2738 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2739 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2740
2741 return 0;
2742
2743abort_with_irq:
2744 free_irq(pdev->irq, mgp);
2745 if (mgp->msi_enabled)
2746 pci_disable_msi(pdev);
2747
2748abort_with_firmware:
2749 myri10ge_dummy_rdma(mgp, 0);
2750
2751abort_with_rx_done:
2752 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2753 pci_free_consistent(pdev, bytes, mgp->rx_done.entry, mgp->rx_done.bus);
2754
2755abort_with_ioremap:
2756 iounmap(mgp->sram);
2757
2758abort_with_wc:
2759#ifdef CONFIG_MTRR
2760 if (mgp->mtrr >= 0)
2761 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2762#endif
2763 pci_free_consistent(pdev, sizeof(*mgp->fw_stats),
2764 mgp->fw_stats, mgp->fw_stats_bus);
2765
2766abort_with_cmd:
2767 pci_free_consistent(pdev, sizeof(*mgp->cmd), mgp->cmd, mgp->cmd_bus);
2768
2769abort_with_netdev:
2770
2771 free_netdev(netdev);
2772 return status;
2773}
2774
2775/*
2776 * myri10ge_remove
2777 *
2778 * Does what is necessary to shutdown one Myrinet device. Called
2779 * once for each Myrinet card by the kernel when a module is
2780 * unloaded.
2781 */
2782static void myri10ge_remove(struct pci_dev *pdev)
2783{
2784 struct myri10ge_priv *mgp;
2785 struct net_device *netdev;
2786 size_t bytes;
2787
2788 mgp = pci_get_drvdata(pdev);
2789 if (mgp == NULL)
2790 return;
2791
2792 flush_scheduled_work();
2793 netdev = mgp->dev;
2794 unregister_netdev(netdev);
2795 free_irq(pdev->irq, mgp);
2796 if (mgp->msi_enabled)
2797 pci_disable_msi(pdev);
2798
2799 myri10ge_dummy_rdma(mgp, 0);
2800
2801 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2802 pci_free_consistent(pdev, bytes, mgp->rx_done.entry, mgp->rx_done.bus);
2803
2804 iounmap(mgp->sram);
2805
2806#ifdef CONFIG_MTRR
2807 if (mgp->mtrr >= 0)
2808 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2809#endif
2810 pci_free_consistent(pdev, sizeof(*mgp->fw_stats),
2811 mgp->fw_stats, mgp->fw_stats_bus);
2812
2813 pci_free_consistent(pdev, sizeof(*mgp->cmd), mgp->cmd, mgp->cmd_bus);
2814
2815 free_netdev(netdev);
2816 pci_set_drvdata(pdev, NULL);
2817}
2818
2819#define PCI_DEVICE_ID_MYIRCOM_MYRI10GE_Z8E 0x0008
2820
2821static struct pci_device_id myri10ge_pci_tbl[] = {
2822 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYIRCOM_MYRI10GE_Z8E)},
2823 {0},
2824};
2825
2826static struct pci_driver myri10ge_driver = {
2827 .name = "myri10ge",
2828 .probe = myri10ge_probe,
2829 .remove = myri10ge_remove,
2830 .id_table = myri10ge_pci_tbl,
2831#ifdef CONFIG_PM
2832 .suspend = myri10ge_suspend,
2833 .resume = myri10ge_resume,
2834#endif
2835};
2836
2837static __init int myri10ge_init_module(void)
2838{
2839 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
2840 MYRI10GE_VERSION_STR);
2841 return pci_register_driver(&myri10ge_driver);
2842}
2843
2844module_init(myri10ge_init_module);
2845
2846static __exit void myri10ge_cleanup_module(void)
2847{
2848 pci_unregister_driver(&myri10ge_driver);
2849}
2850
2851module_exit(myri10ge_cleanup_module);
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h
new file mode 100644
index 000000000000..ac23e18db63d
--- /dev/null
+++ b/drivers/net/myri10ge/myri10ge_mcp.h
@@ -0,0 +1,205 @@
1#ifndef __MYRI10GE_MCP_H__
2#define __MYRI10GE_MCP_H__
3
4#define MXGEFW_VERSION_MAJOR 1
5#define MXGEFW_VERSION_MINOR 4
6
7/* 8 Bytes */
8struct mcp_dma_addr {
9 u32 high;
10 u32 low;
11};
12
13/* 4 Bytes */
14struct mcp_slot {
15 u16 checksum;
16 u16 length;
17};
18
19/* 64 Bytes */
20struct mcp_cmd {
21 u32 cmd;
22 u32 data0; /* will be low portion if data > 32 bits */
23 /* 8 */
24 u32 data1; /* will be high portion if data > 32 bits */
25 u32 data2; /* currently unused.. */
26 /* 16 */
27 struct mcp_dma_addr response_addr;
28 /* 24 */
29 u8 pad[40];
30};
31
32/* 8 Bytes */
33struct mcp_cmd_response {
34 u32 data;
35 u32 result;
36};
37
38/*
39 * flags used in mcp_kreq_ether_send_t:
40 *
41 * The SMALL flag is only needed in the first segment. It is raised
42 * for packets that are total less or equal 512 bytes.
43 *
44 * The CKSUM flag must be set in all segments.
45 *
46 * The PADDED flags is set if the packet needs to be padded, and it
47 * must be set for all segments.
48 *
49 * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
50 * length of all previous segments was odd.
51 */
52
53#define MXGEFW_FLAGS_SMALL 0x1
54#define MXGEFW_FLAGS_TSO_HDR 0x1
55#define MXGEFW_FLAGS_FIRST 0x2
56#define MXGEFW_FLAGS_ALIGN_ODD 0x4
57#define MXGEFW_FLAGS_CKSUM 0x8
58#define MXGEFW_FLAGS_TSO_LAST 0x8
59#define MXGEFW_FLAGS_NO_TSO 0x10
60#define MXGEFW_FLAGS_TSO_CHOP 0x10
61#define MXGEFW_FLAGS_TSO_PLD 0x20
62
63#define MXGEFW_SEND_SMALL_SIZE 1520
64#define MXGEFW_MAX_MTU 9400
65
66union mcp_pso_or_cumlen {
67 u16 pseudo_hdr_offset;
68 u16 cum_len;
69};
70
71#define MXGEFW_MAX_SEND_DESC 12
72#define MXGEFW_PAD 2
73
74/* 16 Bytes */
75struct mcp_kreq_ether_send {
76 u32 addr_high;
77 u32 addr_low;
78 u16 pseudo_hdr_offset;
79 u16 length;
80 u8 pad;
81 u8 rdma_count;
82 u8 cksum_offset; /* where to start computing cksum */
83 u8 flags; /* as defined above */
84};
85
86/* 8 Bytes */
87struct mcp_kreq_ether_recv {
88 u32 addr_high;
89 u32 addr_low;
90};
91
92/* Commands */
93
94#define MXGEFW_CMD_OFFSET 0xf80000
95
96enum myri10ge_mcp_cmd_type {
97 MXGEFW_CMD_NONE = 0,
98 /* Reset the mcp, it is left in a safe state, waiting
99 * for the driver to set all its parameters */
100 MXGEFW_CMD_RESET,
101
102 /* get the version number of the current firmware..
103 * (may be available in the eeprom strings..? */
104 MXGEFW_GET_MCP_VERSION,
105
106 /* Parameters which must be set by the driver before it can
107 * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
108 * MXGEFW_CMD_RESET is issued */
109
110 MXGEFW_CMD_SET_INTRQ_DMA,
111 MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
112 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */
113
114 /* Parameters which refer to lanai SRAM addresses where the
115 * driver must issue PIO writes for various things */
116
117 MXGEFW_CMD_GET_SEND_OFFSET,
118 MXGEFW_CMD_GET_SMALL_RX_OFFSET,
119 MXGEFW_CMD_GET_BIG_RX_OFFSET,
120 MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
121 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
122
123 /* Parameters which refer to rings stored on the MCP,
124 * and whose size is controlled by the mcp */
125
126 MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */
127 MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */
128
129 /* Parameters which refer to rings stored in the host,
130 * and whose size is controlled by the host. Note that
131 * all must be physically contiguous and must contain
132 * a power of 2 number of entries. */
133
134 MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */
135
136 /* command to bring ethernet interface up. Above parameters
137 * (plus mtu & mac address) must have been exchanged prior
138 * to issuing this command */
139 MXGEFW_CMD_ETHERNET_UP,
140
141 /* command to bring ethernet interface down. No further sends
142 * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
143 * is issued, and all interrupt queues must be flushed prior
144 * to ack'ing this command */
145
146 MXGEFW_CMD_ETHERNET_DOWN,
147
148 /* commands the driver may issue live, without resetting
149 * the nic. Note that increasing the mtu "live" should
150 * only be done if the driver has already supplied buffers
151 * sufficiently large to handle the new mtu. Decreasing
152 * the mtu live is safe */
153
154 MXGEFW_CMD_SET_MTU,
155 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */
156 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */
157 MXGEFW_CMD_SET_STATS_DMA,
158
159 MXGEFW_ENABLE_PROMISC,
160 MXGEFW_DISABLE_PROMISC,
161 MXGEFW_SET_MAC_ADDRESS,
162
163 MXGEFW_ENABLE_FLOW_CONTROL,
164 MXGEFW_DISABLE_FLOW_CONTROL,
165
166 /* do a DMA test
167 * data0,data1 = DMA address
168 * data2 = RDMA length (MSH), WDMA length (LSH)
169 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
170 */
171 MXGEFW_DMA_TEST
172};
173
174enum myri10ge_mcp_cmd_status {
175 MXGEFW_CMD_OK = 0,
176 MXGEFW_CMD_UNKNOWN,
177 MXGEFW_CMD_ERROR_RANGE,
178 MXGEFW_CMD_ERROR_BUSY,
179 MXGEFW_CMD_ERROR_EMPTY,
180 MXGEFW_CMD_ERROR_CLOSED,
181 MXGEFW_CMD_ERROR_HASH_ERROR,
182 MXGEFW_CMD_ERROR_BAD_PORT,
183 MXGEFW_CMD_ERROR_RESOURCES
184};
185
186/* 40 Bytes */
187struct mcp_irq_data {
188 u32 send_done_count;
189
190 u32 link_up;
191 u32 dropped_link_overflow;
192 u32 dropped_link_error_or_filtered;
193 u32 dropped_runt;
194 u32 dropped_overrun;
195 u32 dropped_no_small_buffer;
196 u32 dropped_no_big_buffer;
197 u32 rdma_tags_available;
198
199 u8 tx_stopped;
200 u8 link_down;
201 u8 stats_updated;
202 u8 valid;
203};
204
205#endif /* __MYRI10GE_MCP_H__ */
diff --git a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h
new file mode 100644
index 000000000000..1d3a35f10789
--- /dev/null
+++ b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h
@@ -0,0 +1,58 @@
1#ifndef __MYRI10GE_MCP_GEN_HEADER_H__
2#define __MYRI10GE_MCP_GEN_HEADER_H__
3
4/* this file define a standard header used as a first entry point to
5 * exchange information between firmware/driver and driver. The
6 * header structure can be anywhere in the mcp. It will usually be in
7 * the .data section, because some fields needs to be initialized at
8 * compile time.
9 * The 32bit word at offset MX_HEADER_PTR_OFFSET in the mcp must
10 * contains the location of the header.
11 *
12 * Typically a MCP will start with the following:
13 * .text
14 * .space 52 ! to help catch MEMORY_INT errors
15 * bt start ! jump to real code
16 * nop
17 * .long _gen_mcp_header
18 *
19 * The source will have a definition like:
20 *
21 * mcp_gen_header_t gen_mcp_header = {
22 * .header_length = sizeof(mcp_gen_header_t),
23 * .mcp_type = MCP_TYPE_XXX,
24 * .version = "something $Id: mcp_gen_header.h,v 1.2 2006/05/13 10:04:35 bgoglin Exp $",
25 * .mcp_globals = (unsigned)&Globals
26 * };
27 */
28
29#define MCP_HEADER_PTR_OFFSET 0x3c
30
31#define MCP_TYPE_MX 0x4d582020 /* "MX " */
32#define MCP_TYPE_PCIE 0x70636965 /* "PCIE" pcie-only MCP */
33#define MCP_TYPE_ETH 0x45544820 /* "ETH " */
34#define MCP_TYPE_MCP0 0x4d435030 /* "MCP0" */
35
36struct mcp_gen_header {
37 /* the first 4 fields are filled at compile time */
38 unsigned header_length;
39 unsigned mcp_type;
40 char version[128];
41 unsigned mcp_globals; /* pointer to mcp-type specific structure */
42
43 /* filled by the MCP at run-time */
44 unsigned sram_size;
45 unsigned string_specs; /* either the original STRING_SPECS or a superset */
46 unsigned string_specs_len;
47
48 /* Fields above this comment are guaranteed to be present.
49 *
50 * Fields below this comment are extensions added in later versions
51 * of this struct, drivers should compare the header_length against
52 * offsetof(field) to check wether a given MCP implements them.
53 *
54 * Never remove any field. Keep everything naturally align.
55 */
56};
57
58#endif /* __MYRI10GE_MCP_GEN_HEADER_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 07:44:38 -0500