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-rw-r--r--drivers/net/myri10ge/myri10ge_mcp.h435
1 files changed, 0 insertions, 435 deletions
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h
deleted file mode 100644
index 11be150e4d67..000000000000
--- a/drivers/net/myri10ge/myri10ge_mcp.h
+++ /dev/null
@@ -1,435 +0,0 @@
1#ifndef __MYRI10GE_MCP_H__
2#define __MYRI10GE_MCP_H__
3
4#define MXGEFW_VERSION_MAJOR 1
5#define MXGEFW_VERSION_MINOR 4
6
7/* 8 Bytes */
8struct mcp_dma_addr {
9 __be32 high;
10 __be32 low;
11};
12
13/* 4 Bytes */
14struct mcp_slot {
15 __sum16 checksum;
16 __be16 length;
17};
18
19/* 64 Bytes */
20struct mcp_cmd {
21 __be32 cmd;
22 __be32 data0; /* will be low portion if data > 32 bits */
23 /* 8 */
24 __be32 data1; /* will be high portion if data > 32 bits */
25 __be32 data2; /* currently unused.. */
26 /* 16 */
27 struct mcp_dma_addr response_addr;
28 /* 24 */
29 u8 pad[40];
30};
31
32/* 8 Bytes */
33struct mcp_cmd_response {
34 __be32 data;
35 __be32 result;
36};
37
38/*
39 * flags used in mcp_kreq_ether_send_t:
40 *
41 * The SMALL flag is only needed in the first segment. It is raised
42 * for packets that are total less or equal 512 bytes.
43 *
44 * The CKSUM flag must be set in all segments.
45 *
46 * The PADDED flags is set if the packet needs to be padded, and it
47 * must be set for all segments.
48 *
49 * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
50 * length of all previous segments was odd.
51 */
52
53#define MXGEFW_FLAGS_SMALL 0x1
54#define MXGEFW_FLAGS_TSO_HDR 0x1
55#define MXGEFW_FLAGS_FIRST 0x2
56#define MXGEFW_FLAGS_ALIGN_ODD 0x4
57#define MXGEFW_FLAGS_CKSUM 0x8
58#define MXGEFW_FLAGS_TSO_LAST 0x8
59#define MXGEFW_FLAGS_NO_TSO 0x10
60#define MXGEFW_FLAGS_TSO_CHOP 0x10
61#define MXGEFW_FLAGS_TSO_PLD 0x20
62
63#define MXGEFW_SEND_SMALL_SIZE 1520
64#define MXGEFW_MAX_MTU 9400
65
66union mcp_pso_or_cumlen {
67 u16 pseudo_hdr_offset;
68 u16 cum_len;
69};
70
71#define MXGEFW_MAX_SEND_DESC 12
72#define MXGEFW_PAD 2
73
74/* 16 Bytes */
75struct mcp_kreq_ether_send {
76 __be32 addr_high;
77 __be32 addr_low;
78 __be16 pseudo_hdr_offset;
79 __be16 length;
80 u8 pad;
81 u8 rdma_count;
82 u8 cksum_offset; /* where to start computing cksum */
83 u8 flags; /* as defined above */
84};
85
86/* 8 Bytes */
87struct mcp_kreq_ether_recv {
88 __be32 addr_high;
89 __be32 addr_low;
90};
91
92/* Commands */
93
94#define MXGEFW_BOOT_HANDOFF 0xfc0000
95#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
96
97#define MXGEFW_ETH_CMD 0xf80000
98#define MXGEFW_ETH_SEND_4 0x200000
99#define MXGEFW_ETH_SEND_1 0x240000
100#define MXGEFW_ETH_SEND_2 0x280000
101#define MXGEFW_ETH_SEND_3 0x2c0000
102#define MXGEFW_ETH_RECV_SMALL 0x300000
103#define MXGEFW_ETH_RECV_BIG 0x340000
104#define MXGEFW_ETH_SEND_GO 0x380000
105#define MXGEFW_ETH_SEND_STOP 0x3C0000
106
107#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
108#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
109
110enum myri10ge_mcp_cmd_type {
111 MXGEFW_CMD_NONE = 0,
112 /* Reset the mcp, it is left in a safe state, waiting
113 * for the driver to set all its parameters */
114 MXGEFW_CMD_RESET = 1,
115
116 /* get the version number of the current firmware..
117 * (may be available in the eeprom strings..? */
118 MXGEFW_GET_MCP_VERSION = 2,
119
120 /* Parameters which must be set by the driver before it can
121 * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
122 * MXGEFW_CMD_RESET is issued */
123
124 MXGEFW_CMD_SET_INTRQ_DMA = 3,
125 /* data0 = LSW of the host address
126 * data1 = MSW of the host address
127 * data2 = slice number if multiple slices are used
128 */
129
130 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */
131 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */
132
133 /* Parameters which refer to lanai SRAM addresses where the
134 * driver must issue PIO writes for various things */
135
136 MXGEFW_CMD_GET_SEND_OFFSET = 6,
137 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
138 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
139 /* data0 = slice number if multiple slices are used */
140
141 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
142 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
143
144 /* Parameters which refer to rings stored on the MCP,
145 * and whose size is controlled by the mcp */
146
147 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */
148 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */
149
150 /* Parameters which refer to rings stored in the host,
151 * and whose size is controlled by the host. Note that
152 * all must be physically contiguous and must contain
153 * a power of 2 number of entries. */
154
155 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
156#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31)
157
158 /* command to bring ethernet interface up. Above parameters
159 * (plus mtu & mac address) must have been exchanged prior
160 * to issuing this command */
161 MXGEFW_CMD_ETHERNET_UP = 14,
162
163 /* command to bring ethernet interface down. No further sends
164 * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
165 * is issued, and all interrupt queues must be flushed prior
166 * to ack'ing this command */
167
168 MXGEFW_CMD_ETHERNET_DOWN = 15,
169
170 /* commands the driver may issue live, without resetting
171 * the nic. Note that increasing the mtu "live" should
172 * only be done if the driver has already supplied buffers
173 * sufficiently large to handle the new mtu. Decreasing
174 * the mtu live is safe */
175
176 MXGEFW_CMD_SET_MTU = 16,
177 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */
178 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */
179 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
180
181 MXGEFW_ENABLE_PROMISC = 20,
182 MXGEFW_DISABLE_PROMISC = 21,
183 MXGEFW_SET_MAC_ADDRESS = 22,
184
185 MXGEFW_ENABLE_FLOW_CONTROL = 23,
186 MXGEFW_DISABLE_FLOW_CONTROL = 24,
187
188 /* do a DMA test
189 * data0,data1 = DMA address
190 * data2 = RDMA length (MSH), WDMA length (LSH)
191 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
192 */
193 MXGEFW_DMA_TEST = 25,
194
195 MXGEFW_ENABLE_ALLMULTI = 26,
196 MXGEFW_DISABLE_ALLMULTI = 27,
197
198 /* returns MXGEFW_CMD_ERROR_MULTICAST
199 * if there is no room in the cache
200 * data0,MSH(data1) = multicast group address */
201 MXGEFW_JOIN_MULTICAST_GROUP = 28,
202 /* returns MXGEFW_CMD_ERROR_MULTICAST
203 * if the address is not in the cache,
204 * or is equal to FF-FF-FF-FF-FF-FF
205 * data0,MSH(data1) = multicast group address */
206 MXGEFW_LEAVE_MULTICAST_GROUP = 29,
207 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
208
209 MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
210 /* data0, data1 = bus addr,
211 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
212 * adding new stuff to mcp_irq_data without changing the ABI
213 *
214 * If multiple slices are used, data2 contains both the size of the
215 * structure (in the lower 16 bits) and the slice number
216 * (in the upper 16 bits).
217 */
218
219 MXGEFW_CMD_UNALIGNED_TEST = 32,
220 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
221 * chipset */
222
223 MXGEFW_CMD_UNALIGNED_STATUS = 33,
224 /* return data = boolean, true if the chipset is known to be unaligned */
225
226 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
227 /* data0 = number of big buffers to use. It must be 0 or a power of 2.
228 * 0 indicates that the NIC consumes as many buffers as they are required
229 * for packet. This is the default behavior.
230 * A power of 2 number indicates that the NIC always uses the specified
231 * number of buffers for each big receive packet.
232 * It is up to the driver to ensure that this value is big enough for
233 * the NIC to be able to receive maximum-sized packets.
234 */
235
236 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
237 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
238 /* data0 = number of slices n (0, 1, ..., n-1) to enable
239 * data1 = interrupt mode | use of multiple transmit queues.
240 * 0=share one INTx/MSI.
241 * 1=use one MSI-X per queue.
242 * If all queues share one interrupt, the driver must have set
243 * RSS_SHARED_INTERRUPT_DMA before enabling queues.
244 * 2=enable both receive and send queues.
245 * Without this bit set, only one send queue (slice 0's send queue)
246 * is enabled. The receive queues are always enabled.
247 */
248#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0
249#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1
250#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
251
252 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
253 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
254 /* data0, data1 = bus address lsw, msw */
255 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
256 /* get the offset of the indirection table */
257 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
258 /* set the size of the indirection table */
259 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
260 /* get the offset of the secret key */
261 MXGEFW_CMD_RSS_KEY_UPDATED = 42,
262 /* tell nic that the secret key's been updated */
263 MXGEFW_CMD_SET_RSS_ENABLE = 43,
264 /* data0 = enable/disable rss
265 * 0: disable rss. nic does not distribute receive packets.
266 * 1: enable rss. nic distributes receive packets among queues.
267 * data1 = hash type
268 * 1: IPV4 (required by RSS)
269 * 2: TCP_IPV4 (required by RSS)
270 * 3: IPV4 | TCP_IPV4 (required by RSS)
271 * 4: source port
272 * 5: source port + destination port
273 */
274#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1
275#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2
276#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4
277#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
278#define MXGEFW_RSS_HASH_TYPE_MAX 0x5
279
280 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
281 /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
282 * If the header size of a IPv6 TSO packet is larger than the specified
283 * value, then the driver must not use TSO.
284 * This size restriction only applies to IPv6 TSO.
285 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
286 * always has enough header buffer to store maximum-sized headers.
287 */
288
289 MXGEFW_CMD_SET_TSO_MODE = 45,
290 /* data0 = TSO mode.
291 * 0: Linux/FreeBSD style (NIC default)
292 * 1: NDIS/NetBSD style
293 */
294#define MXGEFW_TSO_MODE_LINUX 0
295#define MXGEFW_TSO_MODE_NDIS 1
296
297 MXGEFW_CMD_MDIO_READ = 46,
298 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
299 MXGEFW_CMD_MDIO_WRITE = 47,
300 /* data0 = dev_addr, data1 = register/addr, data2 = value */
301
302 MXGEFW_CMD_I2C_READ = 48,
303 /* Starts to get a fresh copy of one byte or of the module i2c table, the
304 * obtained data is cached inside the xaui-xfi chip :
305 * data0 : 0 => get one byte, 1=> get 256 bytes
306 * data1 : If data0 == 0: location to refresh
307 * bit 7:0 register location
308 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
309 * bit 23:16 is the i2c bus number (for multi-port NICs)
310 * If data0 == 1: unused
311 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
312 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
313 * will return MXGEFW_CMD_ERROR_BUSY
314 */
315 MXGEFW_CMD_I2C_BYTE = 49,
316 /* Return the last obtained copy of a given byte in the xfp i2c table
317 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
318 * data0 : index of the desired table entry
319 * Return data = the byte stored at the requested index in the table
320 */
321
322 MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
323 /* Return data = NIC memory offset of mcp_vpump_public_global */
324 MXGEFW_CMD_RESET_VPUMP = 51,
325 /* Resets the VPUMP state */
326
327 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
328 /* data0 = mcp_slot type to use.
329 * 0 = the default 4B mcp_slot
330 * 1 = 8B mcp_slot_8
331 */
332#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0
333#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1
334
335 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
336 /* set the throttle factor for ethp_z8e
337 * data0 = throttle_factor
338 * throttle_factor = 256 * pcie-raw-speed / tx_speed
339 * tx_speed = 256 * pcie-raw-speed / throttle_factor
340 *
341 * For PCI-E x8: pcie-raw-speed == 16Gb/s
342 * For PCI-E x4: pcie-raw-speed == 8Gb/s
343 *
344 * ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
345 * ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
346 *
347 * with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
348 * with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
349 */
350
351 MXGEFW_CMD_VPUMP_UP = 54,
352 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
353 MXGEFW_CMD_GET_VPUMP_CLK = 55,
354 /* Get the lanai clock */
355
356 MXGEFW_CMD_GET_DCA_OFFSET = 56,
357 /* offset of dca control for WDMAs */
358
359 /* VMWare NetQueue commands */
360 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
361 MXGEFW_CMD_NETQ_ADD_FILTER = 58,
362 /* data0 = filter_id << 16 | queue << 8 | type */
363 /* data1 = MS4 of MAC Addr */
364 /* data2 = LS2_MAC << 16 | VLAN_tag */
365 MXGEFW_CMD_NETQ_DEL_FILTER = 59,
366 /* data0 = filter_id */
367 MXGEFW_CMD_NETQ_QUERY1 = 60,
368 MXGEFW_CMD_NETQ_QUERY2 = 61,
369 MXGEFW_CMD_NETQ_QUERY3 = 62,
370 MXGEFW_CMD_NETQ_QUERY4 = 63,
371
372 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
373 /* When set, small receive buffers can cross page boundaries.
374 * Both small and big receive buffers may start at any address.
375 * This option has performance implications, so use with caution.
376 */
377};
378
379enum myri10ge_mcp_cmd_status {
380 MXGEFW_CMD_OK = 0,
381 MXGEFW_CMD_UNKNOWN = 1,
382 MXGEFW_CMD_ERROR_RANGE = 2,
383 MXGEFW_CMD_ERROR_BUSY = 3,
384 MXGEFW_CMD_ERROR_EMPTY = 4,
385 MXGEFW_CMD_ERROR_CLOSED = 5,
386 MXGEFW_CMD_ERROR_HASH_ERROR = 6,
387 MXGEFW_CMD_ERROR_BAD_PORT = 7,
388 MXGEFW_CMD_ERROR_RESOURCES = 8,
389 MXGEFW_CMD_ERROR_MULTICAST = 9,
390 MXGEFW_CMD_ERROR_UNALIGNED = 10,
391 MXGEFW_CMD_ERROR_NO_MDIO = 11,
392 MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
393 MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
394 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
395};
396
397#define MXGEFW_OLD_IRQ_DATA_LEN 40
398
399struct mcp_irq_data {
400 /* add new counters at the beginning */
401 __be32 future_use[1];
402 __be32 dropped_pause;
403 __be32 dropped_unicast_filtered;
404 __be32 dropped_bad_crc32;
405 __be32 dropped_bad_phy;
406 __be32 dropped_multicast_filtered;
407 /* 40 Bytes */
408 __be32 send_done_count;
409
410#define MXGEFW_LINK_DOWN 0
411#define MXGEFW_LINK_UP 1
412#define MXGEFW_LINK_MYRINET 2
413#define MXGEFW_LINK_UNKNOWN 3
414 __be32 link_up;
415 __be32 dropped_link_overflow;
416 __be32 dropped_link_error_or_filtered;
417 __be32 dropped_runt;
418 __be32 dropped_overrun;
419 __be32 dropped_no_small_buffer;
420 __be32 dropped_no_big_buffer;
421 __be32 rdma_tags_available;
422
423 u8 tx_stopped;
424 u8 link_down;
425 u8 stats_updated;
426 u8 valid;
427};
428
429/* definitions for NETQ filter type */
430#define MXGEFW_NETQ_FILTERTYPE_NONE 0
431#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
432#define MXGEFW_NETQ_FILTERTYPE_VLAN 2
433#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
434
435#endif /* __MYRI10GE_MCP_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 05:24:35 -0500