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-rw-r--r--drivers/net/mv643xx_eth.h567
1 files changed, 0 insertions, 567 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h
deleted file mode 100644
index 318183e6da87..000000000000
--- a/drivers/net/mv643xx_eth.h
+++ /dev/null
@@ -1,567 +0,0 @@
1#ifndef __MV643XX_ETH_H__
2#define __MV643XX_ETH_H__
3
4#include <linux/module.h>
5#include <linux/kernel.h>
6#include <linux/spinlock.h>
7#include <linux/workqueue.h>
8#include <linux/mii.h>
9
10#include <linux/mv643xx_eth.h>
11
12#include <asm/dma-mapping.h>
13
14/* Checksum offload for Tx works for most packets, but
15 * fails if previous packet sent did not use hw csum
16 */
17#define MV643XX_CHECKSUM_OFFLOAD_TX
18#define MV643XX_NAPI
19#define MV643XX_TX_FAST_REFILL
20#undef MV643XX_COAL
21
22/*
23 * Number of RX / TX descriptors on RX / TX rings.
24 * Note that allocating RX descriptors is done by allocating the RX
25 * ring AND a preallocated RX buffers (skb's) for each descriptor.
26 * The TX descriptors only allocates the TX descriptors ring,
27 * with no pre allocated TX buffers (skb's are allocated by higher layers.
28 */
29
30/* Default TX ring size is 1000 descriptors */
31#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
32
33/* Default RX ring size is 400 descriptors */
34#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
35
36#define MV643XX_TX_COAL 100
37#ifdef MV643XX_COAL
38#define MV643XX_RX_COAL 100
39#endif
40
41#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
42#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
43#else
44#define MAX_DESCS_PER_SKB 1
45#endif
46
47#define ETH_VLAN_HLEN 4
48#define ETH_FCS_LEN 4
49#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
50#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
51 ETH_VLAN_HLEN + ETH_FCS_LEN)
52#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
53 dma_get_cache_alignment())
54
55/*
56 * Registers shared between all ports.
57 */
58#define PHY_ADDR_REG 0x0000
59#define SMI_REG 0x0004
60
61
62/*
63 * Per-port registers.
64 */
65#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
66#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
67#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
68#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
69#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
70#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
71#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
72#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
73#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
74#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
75#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
76#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
77#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
78#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
79#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
80#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
81#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
82#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
83#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
84#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
85#define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
86
87/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
88#define UNICAST_NORMAL_MODE (0 << 0)
89#define UNICAST_PROMISCUOUS_MODE (1 << 0)
90#define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
91#define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
92#define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
93#define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
94#define RECEIVE_BC_IF_IP (0 << 8)
95#define REJECT_BC_IF_IP (1 << 8)
96#define RECEIVE_BC_IF_ARP (0 << 9)
97#define REJECT_BC_IF_ARP (1 << 9)
98#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
99#define CAPTURE_TCP_FRAMES_DIS (0 << 14)
100#define CAPTURE_TCP_FRAMES_EN (1 << 14)
101#define CAPTURE_UDP_FRAMES_DIS (0 << 15)
102#define CAPTURE_UDP_FRAMES_EN (1 << 15)
103#define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
104#define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
105#define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
106
107#define PORT_CONFIG_DEFAULT_VALUE \
108 UNICAST_NORMAL_MODE | \
109 DEFAULT_RX_QUEUE(0) | \
110 DEFAULT_RX_ARP_QUEUE(0) | \
111 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
112 RECEIVE_BC_IF_IP | \
113 RECEIVE_BC_IF_ARP | \
114 CAPTURE_TCP_FRAMES_DIS | \
115 CAPTURE_UDP_FRAMES_DIS | \
116 DEFAULT_RX_TCP_QUEUE(0) | \
117 DEFAULT_RX_UDP_QUEUE(0) | \
118 DEFAULT_RX_BPDU_QUEUE(0)
119
120/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
121#define CLASSIFY_EN (1 << 0)
122#define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
123#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
124#define PARTITION_DISABLE (0 << 2)
125#define PARTITION_ENABLE (1 << 2)
126
127#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
128 SPAN_BPDU_PACKETS_AS_NORMAL | \
129 PARTITION_DISABLE
130
131/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
132#define RIFB (1 << 0)
133#define RX_BURST_SIZE_1_64BIT (0 << 1)
134#define RX_BURST_SIZE_2_64BIT (1 << 1)
135#define RX_BURST_SIZE_4_64BIT (2 << 1)
136#define RX_BURST_SIZE_8_64BIT (3 << 1)
137#define RX_BURST_SIZE_16_64BIT (4 << 1)
138#define BLM_RX_NO_SWAP (1 << 4)
139#define BLM_RX_BYTE_SWAP (0 << 4)
140#define BLM_TX_NO_SWAP (1 << 5)
141#define BLM_TX_BYTE_SWAP (0 << 5)
142#define DESCRIPTORS_BYTE_SWAP (1 << 6)
143#define DESCRIPTORS_NO_SWAP (0 << 6)
144#define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
145#define TX_BURST_SIZE_1_64BIT (0 << 22)
146#define TX_BURST_SIZE_2_64BIT (1 << 22)
147#define TX_BURST_SIZE_4_64BIT (2 << 22)
148#define TX_BURST_SIZE_8_64BIT (3 << 22)
149#define TX_BURST_SIZE_16_64BIT (4 << 22)
150
151#if defined(__BIG_ENDIAN)
152#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
153 RX_BURST_SIZE_4_64BIT | \
154 IPG_INT_RX(0) | \
155 TX_BURST_SIZE_4_64BIT
156#elif defined(__LITTLE_ENDIAN)
157#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
158 RX_BURST_SIZE_4_64BIT | \
159 BLM_RX_NO_SWAP | \
160 BLM_TX_NO_SWAP | \
161 IPG_INT_RX(0) | \
162 TX_BURST_SIZE_4_64BIT
163#else
164#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
165#endif
166
167/* These macros describe Ethernet Port serial control reg (PSCR) bits */
168#define SERIAL_PORT_DISABLE (0 << 0)
169#define SERIAL_PORT_ENABLE (1 << 0)
170#define DO_NOT_FORCE_LINK_PASS (0 << 1)
171#define FORCE_LINK_PASS (1 << 1)
172#define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
173#define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
174#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
175#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
176#define ADV_NO_FLOW_CTRL (0 << 4)
177#define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
178#define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
179#define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
180#define FORCE_BP_MODE_NO_JAM (0 << 7)
181#define FORCE_BP_MODE_JAM_TX (1 << 7)
182#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
183#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
184#define FORCE_LINK_FAIL (0 << 10)
185#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
186#define RETRANSMIT_16_ATTEMPTS (0 << 11)
187#define RETRANSMIT_FOREVER (1 << 11)
188#define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
189#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
190#define DTE_ADV_0 (0 << 14)
191#define DTE_ADV_1 (1 << 14)
192#define DISABLE_AUTO_NEG_BYPASS (0 << 15)
193#define ENABLE_AUTO_NEG_BYPASS (1 << 15)
194#define AUTO_NEG_NO_CHANGE (0 << 16)
195#define RESTART_AUTO_NEG (1 << 16)
196#define MAX_RX_PACKET_1518BYTE (0 << 17)
197#define MAX_RX_PACKET_1522BYTE (1 << 17)
198#define MAX_RX_PACKET_1552BYTE (2 << 17)
199#define MAX_RX_PACKET_9022BYTE (3 << 17)
200#define MAX_RX_PACKET_9192BYTE (4 << 17)
201#define MAX_RX_PACKET_9700BYTE (5 << 17)
202#define MAX_RX_PACKET_MASK (7 << 17)
203#define CLR_EXT_LOOPBACK (0 << 20)
204#define SET_EXT_LOOPBACK (1 << 20)
205#define SET_HALF_DUPLEX_MODE (0 << 21)
206#define SET_FULL_DUPLEX_MODE (1 << 21)
207#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
208#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
209#define SET_GMII_SPEED_TO_10_100 (0 << 23)
210#define SET_GMII_SPEED_TO_1000 (1 << 23)
211#define SET_MII_SPEED_TO_10 (0 << 24)
212#define SET_MII_SPEED_TO_100 (1 << 24)
213
214#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
215 DO_NOT_FORCE_LINK_PASS | \
216 ENABLE_AUTO_NEG_FOR_DUPLX | \
217 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
218 ADV_SYMMETRIC_FLOW_CTRL | \
219 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
220 FORCE_BP_MODE_NO_JAM | \
221 (1 << 9) /* reserved */ | \
222 DO_NOT_FORCE_LINK_FAIL | \
223 RETRANSMIT_16_ATTEMPTS | \
224 ENABLE_AUTO_NEG_SPEED_GMII | \
225 DTE_ADV_0 | \
226 DISABLE_AUTO_NEG_BYPASS | \
227 AUTO_NEG_NO_CHANGE | \
228 MAX_RX_PACKET_9700BYTE | \
229 CLR_EXT_LOOPBACK | \
230 SET_FULL_DUPLEX_MODE | \
231 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
232
233/* These macros describe Ethernet Serial Status reg (PSR) bits */
234#define PORT_STATUS_MODE_10_BIT (1 << 0)
235#define PORT_STATUS_LINK_UP (1 << 1)
236#define PORT_STATUS_FULL_DUPLEX (1 << 2)
237#define PORT_STATUS_FLOW_CONTROL (1 << 3)
238#define PORT_STATUS_GMII_1000 (1 << 4)
239#define PORT_STATUS_MII_100 (1 << 5)
240/* PSR bit 6 is undocumented */
241#define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
242#define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
243#define PORT_STATUS_PARTITION (1 << 9)
244#define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
245/* PSR bits 11-31 are reserved */
246
247#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
248#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
249
250#define DESC_SIZE 64
251
252#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
253#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
254
255#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
256#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
257#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
258#define ETH_INT_CAUSE_EXT 0x00000002
259#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
260
261#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
262#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
263#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
264#define ETH_INT_CAUSE_PHY 0x00010000
265#define ETH_INT_CAUSE_STATE 0x00100000
266#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
267 ETH_INT_CAUSE_STATE)
268
269#define ETH_INT_MASK_ALL 0x00000000
270#define ETH_INT_MASK_ALL_EXT 0x00000000
271
272#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
273#define PHY_WAIT_MICRO_SECONDS 10
274
275/* Buffer offset from buffer pointer */
276#define RX_BUF_OFFSET 0x2
277
278/* Gigabit Ethernet Unit Global Registers */
279
280/* MIB Counters register definitions */
281#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
282#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
283#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
284#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
285#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
286#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
287#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
288#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
289#define ETH_MIB_FRAMES_64_OCTETS 0x20
290#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
291#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
292#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
293#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
294#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
295#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
296#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
297#define ETH_MIB_GOOD_FRAMES_SENT 0x40
298#define ETH_MIB_EXCESSIVE_COLLISION 0x44
299#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
300#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
301#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
302#define ETH_MIB_FC_SENT 0x54
303#define ETH_MIB_GOOD_FC_RECEIVED 0x58
304#define ETH_MIB_BAD_FC_RECEIVED 0x5c
305#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
306#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
307#define ETH_MIB_OVERSIZE_RECEIVED 0x68
308#define ETH_MIB_JABBER_RECEIVED 0x6c
309#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
310#define ETH_MIB_BAD_CRC_EVENT 0x74
311#define ETH_MIB_COLLISION 0x78
312#define ETH_MIB_LATE_COLLISION 0x7c
313
314/* Port serial status reg (PSR) */
315#define ETH_INTERFACE_PCM 0x00000001
316#define ETH_LINK_IS_UP 0x00000002
317#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
318#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
319#define ETH_GMII_SPEED_1000 0x00000010
320#define ETH_MII_SPEED_100 0x00000020
321#define ETH_TX_IN_PROGRESS 0x00000080
322#define ETH_BYPASS_ACTIVE 0x00000100
323#define ETH_PORT_AT_PARTITION_STATE 0x00000200
324#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
325
326/* SMI reg */
327#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
328#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
329#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
330#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
331
332/* Interrupt Cause Register Bit Definitions */
333
334/* SDMA command status fields macros */
335
336/* Tx & Rx descriptors status */
337#define ETH_ERROR_SUMMARY 0x00000001
338
339/* Tx & Rx descriptors command */
340#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
341
342/* Tx descriptors status */
343#define ETH_LC_ERROR 0
344#define ETH_UR_ERROR 0x00000002
345#define ETH_RL_ERROR 0x00000004
346#define ETH_LLC_SNAP_FORMAT 0x00000200
347
348/* Rx descriptors status */
349#define ETH_OVERRUN_ERROR 0x00000002
350#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
351#define ETH_RESOURCE_ERROR 0x00000006
352#define ETH_VLAN_TAGGED 0x00080000
353#define ETH_BPDU_FRAME 0x00100000
354#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
355#define ETH_OTHER_FRAME_TYPE 0x00400000
356#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
357#define ETH_FRAME_TYPE_IP_V_4 0x01000000
358#define ETH_FRAME_HEADER_OK 0x02000000
359#define ETH_RX_LAST_DESC 0x04000000
360#define ETH_RX_FIRST_DESC 0x08000000
361#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
362#define ETH_RX_ENABLE_INTERRUPT 0x20000000
363#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
364
365/* Rx descriptors byte count */
366#define ETH_FRAME_FRAGMENTED 0x00000004
367
368/* Tx descriptors command */
369#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
370#define ETH_FRAME_SET_TO_VLAN 0x00008000
371#define ETH_UDP_FRAME 0x00010000
372#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
373#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
374#define ETH_ZERO_PADDING 0x00080000
375#define ETH_TX_LAST_DESC 0x00100000
376#define ETH_TX_FIRST_DESC 0x00200000
377#define ETH_GEN_CRC 0x00400000
378#define ETH_TX_ENABLE_INTERRUPT 0x00800000
379#define ETH_AUTO_MODE 0x40000000
380
381#define ETH_TX_IHL_SHIFT 11
382
383/* typedefs */
384
385typedef enum _eth_func_ret_status {
386 ETH_OK, /* Returned as expected. */
387 ETH_ERROR, /* Fundamental error. */
388 ETH_RETRY, /* Could not process request. Try later.*/
389 ETH_END_OF_JOB, /* Ring has nothing to process. */
390 ETH_QUEUE_FULL, /* Ring resource error. */
391 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
392} ETH_FUNC_RET_STATUS;
393
394typedef enum _eth_target {
395 ETH_TARGET_DRAM,
396 ETH_TARGET_DEVICE,
397 ETH_TARGET_CBS,
398 ETH_TARGET_PCI0,
399 ETH_TARGET_PCI1
400} ETH_TARGET;
401
402/* These are for big-endian machines. Little endian needs different
403 * definitions.
404 */
405#if defined(__BIG_ENDIAN)
406struct eth_rx_desc {
407 u16 byte_cnt; /* Descriptor buffer byte count */
408 u16 buf_size; /* Buffer size */
409 u32 cmd_sts; /* Descriptor command status */
410 u32 next_desc_ptr; /* Next descriptor pointer */
411 u32 buf_ptr; /* Descriptor buffer pointer */
412};
413
414struct eth_tx_desc {
415 u16 byte_cnt; /* buffer byte count */
416 u16 l4i_chk; /* CPU provided TCP checksum */
417 u32 cmd_sts; /* Command/status field */
418 u32 next_desc_ptr; /* Pointer to next descriptor */
419 u32 buf_ptr; /* pointer to buffer for this descriptor*/
420};
421#elif defined(__LITTLE_ENDIAN)
422struct eth_rx_desc {
423 u32 cmd_sts; /* Descriptor command status */
424 u16 buf_size; /* Buffer size */
425 u16 byte_cnt; /* Descriptor buffer byte count */
426 u32 buf_ptr; /* Descriptor buffer pointer */
427 u32 next_desc_ptr; /* Next descriptor pointer */
428};
429
430struct eth_tx_desc {
431 u32 cmd_sts; /* Command/status field */
432 u16 l4i_chk; /* CPU provided TCP checksum */
433 u16 byte_cnt; /* buffer byte count */
434 u32 buf_ptr; /* pointer to buffer for this descriptor*/
435 u32 next_desc_ptr; /* Pointer to next descriptor */
436};
437#else
438#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
439#endif
440
441/* Unified struct for Rx and Tx operations. The user is not required to */
442/* be familier with neither Tx nor Rx descriptors. */
443struct pkt_info {
444 unsigned short byte_cnt; /* Descriptor buffer byte count */
445 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
446 unsigned int cmd_sts; /* Descriptor command status */
447 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
448 struct sk_buff *return_info; /* User resource return information */
449};
450
451/* Ethernet port specific information */
452struct mv643xx_mib_counters {
453 u64 good_octets_received;
454 u32 bad_octets_received;
455 u32 internal_mac_transmit_err;
456 u32 good_frames_received;
457 u32 bad_frames_received;
458 u32 broadcast_frames_received;
459 u32 multicast_frames_received;
460 u32 frames_64_octets;
461 u32 frames_65_to_127_octets;
462 u32 frames_128_to_255_octets;
463 u32 frames_256_to_511_octets;
464 u32 frames_512_to_1023_octets;
465 u32 frames_1024_to_max_octets;
466 u64 good_octets_sent;
467 u32 good_frames_sent;
468 u32 excessive_collision;
469 u32 multicast_frames_sent;
470 u32 broadcast_frames_sent;
471 u32 unrec_mac_control_received;
472 u32 fc_sent;
473 u32 good_fc_received;
474 u32 bad_fc_received;
475 u32 undersize_received;
476 u32 fragments_received;
477 u32 oversize_received;
478 u32 jabber_received;
479 u32 mac_receive_error;
480 u32 bad_crc_event;
481 u32 collision;
482 u32 late_collision;
483};
484
485struct mv643xx_private {
486 int port_num; /* User Ethernet port number */
487
488 u32 rx_sram_addr; /* Base address of rx sram area */
489 u32 rx_sram_size; /* Size of rx sram area */
490 u32 tx_sram_addr; /* Base address of tx sram area */
491 u32 tx_sram_size; /* Size of tx sram area */
492
493 int rx_resource_err; /* Rx ring resource error flag */
494
495 /* Tx/Rx rings managment indexes fields. For driver use */
496
497 /* Next available and first returning Rx resource */
498 int rx_curr_desc_q, rx_used_desc_q;
499
500 /* Next available and first returning Tx resource */
501 int tx_curr_desc_q, tx_used_desc_q;
502
503#ifdef MV643XX_TX_FAST_REFILL
504 u32 tx_clean_threshold;
505#endif
506
507 struct eth_rx_desc *p_rx_desc_area;
508 dma_addr_t rx_desc_dma;
509 int rx_desc_area_size;
510 struct sk_buff **rx_skb;
511
512 struct eth_tx_desc *p_tx_desc_area;
513 dma_addr_t tx_desc_dma;
514 int tx_desc_area_size;
515 struct sk_buff **tx_skb;
516
517 struct work_struct tx_timeout_task;
518
519 struct net_device *dev;
520 struct napi_struct napi;
521 struct net_device_stats stats;
522 struct mv643xx_mib_counters mib_counters;
523 spinlock_t lock;
524 /* Size of Tx Ring per queue */
525 int tx_ring_size;
526 /* Number of tx descriptors in use */
527 int tx_desc_count;
528 /* Size of Rx Ring per queue */
529 int rx_ring_size;
530 /* Number of rx descriptors in use */
531 int rx_desc_count;
532
533 /*
534 * Used in case RX Ring is empty, which can be caused when
535 * system does not have resources (skb's)
536 */
537 struct timer_list timeout;
538
539 u32 rx_int_coal;
540 u32 tx_int_coal;
541 struct mii_if_info mii;
542};
543
544/* Port operation control routines */
545static void eth_port_init(struct mv643xx_private *mp);
546static void eth_port_reset(unsigned int eth_port_num);
547static void eth_port_start(struct net_device *dev);
548
549/* PHY and MIB routines */
550static void ethernet_phy_reset(unsigned int eth_port_num);
551
552static void eth_port_write_smi_reg(unsigned int eth_port_num,
553 unsigned int phy_reg, unsigned int value);
554
555static void eth_port_read_smi_reg(unsigned int eth_port_num,
556 unsigned int phy_reg, unsigned int *value);
557
558static void eth_clear_mib_counters(unsigned int eth_port_num);
559
560/* Port data flow control routines */
561static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
562 struct pkt_info *p_pkt_info);
563static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
564 struct pkt_info *p_pkt_info);
565
566
567#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 10:22:14 -0500