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-rw-r--r--drivers/net/mv643xx_eth.c4557
1 files changed, 1885 insertions, 2672 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index b7915cdcc6a5..83a877f3a553 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -34,406 +34,145 @@
34 * along with this program; if not, write to the Free Software 34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */ 36 */
37
37#include <linux/init.h> 38#include <linux/init.h>
38#include <linux/dma-mapping.h> 39#include <linux/dma-mapping.h>
39#include <linux/in.h> 40#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/tcp.h> 41#include <linux/tcp.h>
42#include <linux/udp.h> 42#include <linux/udp.h>
43#include <linux/etherdevice.h> 43#include <linux/etherdevice.h>
44
45#include <linux/bitops.h>
46#include <linux/delay.h> 44#include <linux/delay.h>
47#include <linux/ethtool.h> 45#include <linux/ethtool.h>
48#include <linux/platform_device.h> 46#include <linux/platform_device.h>
49
50#include <linux/module.h> 47#include <linux/module.h>
51#include <linux/kernel.h> 48#include <linux/kernel.h>
52#include <linux/spinlock.h> 49#include <linux/spinlock.h>
53#include <linux/workqueue.h> 50#include <linux/workqueue.h>
54#include <linux/mii.h> 51#include <linux/mii.h>
55
56#include <linux/mv643xx_eth.h> 52#include <linux/mv643xx_eth.h>
57
58#include <asm/io.h> 53#include <asm/io.h>
59#include <asm/types.h> 54#include <asm/types.h>
60#include <asm/pgtable.h>
61#include <asm/system.h> 55#include <asm/system.h>
62#include <asm/delay.h>
63#include <asm/dma-mapping.h>
64 56
65#define MV643XX_CHECKSUM_OFFLOAD_TX 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
66#define MV643XX_NAPI 58static char mv643xx_eth_driver_version[] = "1.1";
67#define MV643XX_TX_FAST_REFILL
68#undef MV643XX_COAL
69 59
70#define MV643XX_TX_COAL 100 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71#ifdef MV643XX_COAL 61#define MV643XX_ETH_NAPI
72#define MV643XX_RX_COAL 100 62#define MV643XX_ETH_TX_FAST_REFILL
73#endif
74 63
75#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
76#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
77#else 66#else
78#define MAX_DESCS_PER_SKB 1 67#define MAX_DESCS_PER_SKB 1
79#endif 68#endif
80 69
81#define ETH_VLAN_HLEN 4
82#define ETH_FCS_LEN 4
83#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
84#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
85 ETH_VLAN_HLEN + ETH_FCS_LEN)
86#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
87 dma_get_cache_alignment())
88
89/* 70/*
90 * Registers shared between all ports. 71 * Registers shared between all ports.
91 */ 72 */
92#define PHY_ADDR_REG 0x0000 73#define PHY_ADDR 0x0000
93#define SMI_REG 0x0004 74#define SMI_REG 0x0004
94#define WINDOW_BASE(i) (0x0200 + ((i) << 3)) 75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
95#define WINDOW_SIZE(i) (0x0204 + ((i) << 3)) 76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
96#define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2)) 77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
97#define WINDOW_BAR_ENABLE 0x0290 78#define WINDOW_BAR_ENABLE 0x0290
98#define WINDOW_PROTECT(i) (0x0294 + ((i) << 4)) 79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
99 80
100/* 81/*
101 * Per-port registers. 82 * Per-port registers.
102 */ 83 */
103#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
104#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
105#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
106#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) 87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
107#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) 88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
108#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) 89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
109#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) 90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
110#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) 91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
111#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) 92#define TX_FIFO_EMPTY 0x00000400
112#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
113#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
114#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) 95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
115#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
116#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
117#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
118#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) 99#define INT_TX_END 0x07f80000
119#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) 100#define INT_RX 0x0007fbfc
120#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) 101#define INT_EXT 0x00000002
121#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) 102#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
122#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) 103#define INT_EXT_LINK 0x00100000
123#define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) 104#define INT_EXT_PHY 0x00010000
124 105#define INT_EXT_TX_ERROR_0 0x00000100
125/* These macros describe Ethernet Port configuration reg (Px_cR) bits */ 106#define INT_EXT_TX_0 0x00000001
126#define UNICAST_NORMAL_MODE (0 << 0) 107#define INT_EXT_TX 0x0000ffff
127#define UNICAST_PROMISCUOUS_MODE (1 << 0) 108#define INT_MASK(p) (0x0468 + ((p) << 10))
128#define DEFAULT_RX_QUEUE(queue) ((queue) << 1) 109#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
129#define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) 110#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
130#define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) 111#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
131#define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) 112#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
132#define RECEIVE_BC_IF_IP (0 << 8) 113#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
133#define REJECT_BC_IF_IP (1 << 8) 114#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
134#define RECEIVE_BC_IF_ARP (0 << 9) 115#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
135#define REJECT_BC_IF_ARP (1 << 9) 116#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
136#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) 117#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
137#define CAPTURE_TCP_FRAMES_DIS (0 << 14) 118#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
138#define CAPTURE_TCP_FRAMES_EN (1 << 14) 119#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
139#define CAPTURE_UDP_FRAMES_DIS (0 << 15) 120#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
140#define CAPTURE_UDP_FRAMES_EN (1 << 15) 121#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
141#define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) 122#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
142#define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) 123#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
143#define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) 124#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
144 125
145#define PORT_CONFIG_DEFAULT_VALUE \ 126
146 UNICAST_NORMAL_MODE | \ 127/*
147 DEFAULT_RX_QUEUE(0) | \ 128 * SDMA configuration register.
148 DEFAULT_RX_ARP_QUEUE(0) | \ 129 */
149 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
150 RECEIVE_BC_IF_IP | \
151 RECEIVE_BC_IF_ARP | \
152 CAPTURE_TCP_FRAMES_DIS | \
153 CAPTURE_UDP_FRAMES_DIS | \
154 DEFAULT_RX_TCP_QUEUE(0) | \
155 DEFAULT_RX_UDP_QUEUE(0) | \
156 DEFAULT_RX_BPDU_QUEUE(0)
157
158/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
159#define CLASSIFY_EN (1 << 0)
160#define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
161#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
162#define PARTITION_DISABLE (0 << 2)
163#define PARTITION_ENABLE (1 << 2)
164
165#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
166 SPAN_BPDU_PACKETS_AS_NORMAL | \
167 PARTITION_DISABLE
168
169/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
170#define RIFB (1 << 0)
171#define RX_BURST_SIZE_1_64BIT (0 << 1)
172#define RX_BURST_SIZE_2_64BIT (1 << 1)
173#define RX_BURST_SIZE_4_64BIT (2 << 1) 130#define RX_BURST_SIZE_4_64BIT (2 << 1)
174#define RX_BURST_SIZE_8_64BIT (3 << 1)
175#define RX_BURST_SIZE_16_64BIT (4 << 1)
176#define BLM_RX_NO_SWAP (1 << 4) 131#define BLM_RX_NO_SWAP (1 << 4)
177#define BLM_RX_BYTE_SWAP (0 << 4)
178#define BLM_TX_NO_SWAP (1 << 5) 132#define BLM_TX_NO_SWAP (1 << 5)
179#define BLM_TX_BYTE_SWAP (0 << 5)
180#define DESCRIPTORS_BYTE_SWAP (1 << 6)
181#define DESCRIPTORS_NO_SWAP (0 << 6)
182#define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
183#define TX_BURST_SIZE_1_64BIT (0 << 22)
184#define TX_BURST_SIZE_2_64BIT (1 << 22)
185#define TX_BURST_SIZE_4_64BIT (2 << 22) 133#define TX_BURST_SIZE_4_64BIT (2 << 22)
186#define TX_BURST_SIZE_8_64BIT (3 << 22)
187#define TX_BURST_SIZE_16_64BIT (4 << 22)
188 134
189#if defined(__BIG_ENDIAN) 135#if defined(__BIG_ENDIAN)
190#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 136#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
191 RX_BURST_SIZE_4_64BIT | \ 137 RX_BURST_SIZE_4_64BIT | \
192 IPG_INT_RX(0) | \
193 TX_BURST_SIZE_4_64BIT 138 TX_BURST_SIZE_4_64BIT
194#elif defined(__LITTLE_ENDIAN) 139#elif defined(__LITTLE_ENDIAN)
195#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 140#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
196 RX_BURST_SIZE_4_64BIT | \ 141 RX_BURST_SIZE_4_64BIT | \
197 BLM_RX_NO_SWAP | \ 142 BLM_RX_NO_SWAP | \
198 BLM_TX_NO_SWAP | \ 143 BLM_TX_NO_SWAP | \
199 IPG_INT_RX(0) | \
200 TX_BURST_SIZE_4_64BIT 144 TX_BURST_SIZE_4_64BIT
201#else 145#else
202#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 146#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203#endif 147#endif
204 148
205/* These macros describe Ethernet Port serial control reg (PSCR) bits */ 149
206#define SERIAL_PORT_DISABLE (0 << 0) 150/*
207#define SERIAL_PORT_ENABLE (1 << 0) 151 * Port serial control register.
208#define DO_NOT_FORCE_LINK_PASS (0 << 1) 152 */
209#define FORCE_LINK_PASS (1 << 1) 153#define SET_MII_SPEED_TO_100 (1 << 24)
210#define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) 154#define SET_GMII_SPEED_TO_1000 (1 << 23)
211#define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) 155#define SET_FULL_DUPLEX_MODE (1 << 21)
212#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
213#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
214#define ADV_NO_FLOW_CTRL (0 << 4)
215#define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
216#define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
217#define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
218#define FORCE_BP_MODE_NO_JAM (0 << 7)
219#define FORCE_BP_MODE_JAM_TX (1 << 7)
220#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
221#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
222#define FORCE_LINK_FAIL (0 << 10)
223#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
224#define RETRANSMIT_16_ATTEMPTS (0 << 11)
225#define RETRANSMIT_FOREVER (1 << 11)
226#define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
227#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
228#define DTE_ADV_0 (0 << 14)
229#define DTE_ADV_1 (1 << 14)
230#define DISABLE_AUTO_NEG_BYPASS (0 << 15)
231#define ENABLE_AUTO_NEG_BYPASS (1 << 15)
232#define AUTO_NEG_NO_CHANGE (0 << 16)
233#define RESTART_AUTO_NEG (1 << 16)
234#define MAX_RX_PACKET_1518BYTE (0 << 17)
235#define MAX_RX_PACKET_1522BYTE (1 << 17) 156#define MAX_RX_PACKET_1522BYTE (1 << 17)
236#define MAX_RX_PACKET_1552BYTE (2 << 17)
237#define MAX_RX_PACKET_9022BYTE (3 << 17)
238#define MAX_RX_PACKET_9192BYTE (4 << 17)
239#define MAX_RX_PACKET_9700BYTE (5 << 17) 157#define MAX_RX_PACKET_9700BYTE (5 << 17)
240#define MAX_RX_PACKET_MASK (7 << 17) 158#define MAX_RX_PACKET_MASK (7 << 17)
241#define CLR_EXT_LOOPBACK (0 << 20) 159#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
242#define SET_EXT_LOOPBACK (1 << 20) 160#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
243#define SET_HALF_DUPLEX_MODE (0 << 21) 161#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
244#define SET_FULL_DUPLEX_MODE (1 << 21) 162#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
245#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) 163#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
246#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) 164#define FORCE_LINK_PASS (1 << 1)
247#define SET_GMII_SPEED_TO_10_100 (0 << 23) 165#define SERIAL_PORT_ENABLE (1 << 0)
248#define SET_GMII_SPEED_TO_1000 (1 << 23)
249#define SET_MII_SPEED_TO_10 (0 << 24)
250#define SET_MII_SPEED_TO_100 (1 << 24)
251 166
252#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ 167#define DEFAULT_RX_QUEUE_SIZE 400
253 DO_NOT_FORCE_LINK_PASS | \ 168#define DEFAULT_TX_QUEUE_SIZE 800
254 ENABLE_AUTO_NEG_FOR_DUPLX | \ 169
255 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ 170
256 ADV_SYMMETRIC_FLOW_CTRL | \ 171/*
257 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 172 * RX/TX descriptors.
258 FORCE_BP_MODE_NO_JAM | \
259 (1 << 9) /* reserved */ | \
260 DO_NOT_FORCE_LINK_FAIL | \
261 RETRANSMIT_16_ATTEMPTS | \
262 ENABLE_AUTO_NEG_SPEED_GMII | \
263 DTE_ADV_0 | \
264 DISABLE_AUTO_NEG_BYPASS | \
265 AUTO_NEG_NO_CHANGE | \
266 MAX_RX_PACKET_9700BYTE | \
267 CLR_EXT_LOOPBACK | \
268 SET_FULL_DUPLEX_MODE | \
269 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
270
271/* These macros describe Ethernet Serial Status reg (PSR) bits */
272#define PORT_STATUS_MODE_10_BIT (1 << 0)
273#define PORT_STATUS_LINK_UP (1 << 1)
274#define PORT_STATUS_FULL_DUPLEX (1 << 2)
275#define PORT_STATUS_FLOW_CONTROL (1 << 3)
276#define PORT_STATUS_GMII_1000 (1 << 4)
277#define PORT_STATUS_MII_100 (1 << 5)
278/* PSR bit 6 is undocumented */
279#define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
280#define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
281#define PORT_STATUS_PARTITION (1 << 9)
282#define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
283/* PSR bits 11-31 are reserved */
284
285#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
286#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
287
288#define DESC_SIZE 64
289
290#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
291#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
292
293#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
294#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
295#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
296#define ETH_INT_CAUSE_EXT 0x00000002
297#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
298
299#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
300#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
301#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
302#define ETH_INT_CAUSE_PHY 0x00010000
303#define ETH_INT_CAUSE_STATE 0x00100000
304#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
305 ETH_INT_CAUSE_STATE)
306
307#define ETH_INT_MASK_ALL 0x00000000
308#define ETH_INT_MASK_ALL_EXT 0x00000000
309
310#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
311#define PHY_WAIT_MICRO_SECONDS 10
312
313/* Buffer offset from buffer pointer */
314#define RX_BUF_OFFSET 0x2
315
316/* Gigabit Ethernet Unit Global Registers */
317
318/* MIB Counters register definitions */
319#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
320#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
321#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
322#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
323#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
324#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
325#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
326#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
327#define ETH_MIB_FRAMES_64_OCTETS 0x20
328#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
329#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
330#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
331#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
332#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
333#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
334#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
335#define ETH_MIB_GOOD_FRAMES_SENT 0x40
336#define ETH_MIB_EXCESSIVE_COLLISION 0x44
337#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
338#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
339#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
340#define ETH_MIB_FC_SENT 0x54
341#define ETH_MIB_GOOD_FC_RECEIVED 0x58
342#define ETH_MIB_BAD_FC_RECEIVED 0x5c
343#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
344#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
345#define ETH_MIB_OVERSIZE_RECEIVED 0x68
346#define ETH_MIB_JABBER_RECEIVED 0x6c
347#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
348#define ETH_MIB_BAD_CRC_EVENT 0x74
349#define ETH_MIB_COLLISION 0x78
350#define ETH_MIB_LATE_COLLISION 0x7c
351
352/* Port serial status reg (PSR) */
353#define ETH_INTERFACE_PCM 0x00000001
354#define ETH_LINK_IS_UP 0x00000002
355#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
356#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
357#define ETH_GMII_SPEED_1000 0x00000010
358#define ETH_MII_SPEED_100 0x00000020
359#define ETH_TX_IN_PROGRESS 0x00000080
360#define ETH_BYPASS_ACTIVE 0x00000100
361#define ETH_PORT_AT_PARTITION_STATE 0x00000200
362#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
363
364/* SMI reg */
365#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
366#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
367#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
368#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
369
370/* Interrupt Cause Register Bit Definitions */
371
372/* SDMA command status fields macros */
373
374/* Tx & Rx descriptors status */
375#define ETH_ERROR_SUMMARY 0x00000001
376
377/* Tx & Rx descriptors command */
378#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
379
380/* Tx descriptors status */
381#define ETH_LC_ERROR 0
382#define ETH_UR_ERROR 0x00000002
383#define ETH_RL_ERROR 0x00000004
384#define ETH_LLC_SNAP_FORMAT 0x00000200
385
386/* Rx descriptors status */
387#define ETH_OVERRUN_ERROR 0x00000002
388#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
389#define ETH_RESOURCE_ERROR 0x00000006
390#define ETH_VLAN_TAGGED 0x00080000
391#define ETH_BPDU_FRAME 0x00100000
392#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
393#define ETH_OTHER_FRAME_TYPE 0x00400000
394#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
395#define ETH_FRAME_TYPE_IP_V_4 0x01000000
396#define ETH_FRAME_HEADER_OK 0x02000000
397#define ETH_RX_LAST_DESC 0x04000000
398#define ETH_RX_FIRST_DESC 0x08000000
399#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
400#define ETH_RX_ENABLE_INTERRUPT 0x20000000
401#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
402
403/* Rx descriptors byte count */
404#define ETH_FRAME_FRAGMENTED 0x00000004
405
406/* Tx descriptors command */
407#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
408#define ETH_FRAME_SET_TO_VLAN 0x00008000
409#define ETH_UDP_FRAME 0x00010000
410#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
411#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
412#define ETH_ZERO_PADDING 0x00080000
413#define ETH_TX_LAST_DESC 0x00100000
414#define ETH_TX_FIRST_DESC 0x00200000
415#define ETH_GEN_CRC 0x00400000
416#define ETH_TX_ENABLE_INTERRUPT 0x00800000
417#define ETH_AUTO_MODE 0x40000000
418
419#define ETH_TX_IHL_SHIFT 11
420
421/* typedefs */
422
423typedef enum _eth_func_ret_status {
424 ETH_OK, /* Returned as expected. */
425 ETH_ERROR, /* Fundamental error. */
426 ETH_RETRY, /* Could not process request. Try later.*/
427 ETH_END_OF_JOB, /* Ring has nothing to process. */
428 ETH_QUEUE_FULL, /* Ring resource error. */
429 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
430} ETH_FUNC_RET_STATUS;
431
432/* These are for big-endian machines. Little endian needs different
433 * definitions.
434 */ 173 */
435#if defined(__BIG_ENDIAN) 174#if defined(__BIG_ENDIAN)
436struct eth_rx_desc { 175struct rx_desc {
437 u16 byte_cnt; /* Descriptor buffer byte count */ 176 u16 byte_cnt; /* Descriptor buffer byte count */
438 u16 buf_size; /* Buffer size */ 177 u16 buf_size; /* Buffer size */
439 u32 cmd_sts; /* Descriptor command status */ 178 u32 cmd_sts; /* Descriptor command status */
@@ -441,7 +180,7 @@ struct eth_rx_desc {
441 u32 buf_ptr; /* Descriptor buffer pointer */ 180 u32 buf_ptr; /* Descriptor buffer pointer */
442}; 181};
443 182
444struct eth_tx_desc { 183struct tx_desc {
445 u16 byte_cnt; /* buffer byte count */ 184 u16 byte_cnt; /* buffer byte count */
446 u16 l4i_chk; /* CPU provided TCP checksum */ 185 u16 l4i_chk; /* CPU provided TCP checksum */
447 u32 cmd_sts; /* Command/status field */ 186 u32 cmd_sts; /* Command/status field */
@@ -449,7 +188,7 @@ struct eth_tx_desc {
449 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 188 u32 buf_ptr; /* pointer to buffer for this descriptor*/
450}; 189};
451#elif defined(__LITTLE_ENDIAN) 190#elif defined(__LITTLE_ENDIAN)
452struct eth_rx_desc { 191struct rx_desc {
453 u32 cmd_sts; /* Descriptor command status */ 192 u32 cmd_sts; /* Descriptor command status */
454 u16 buf_size; /* Buffer size */ 193 u16 buf_size; /* Buffer size */
455 u16 byte_cnt; /* Descriptor buffer byte count */ 194 u16 byte_cnt; /* Descriptor buffer byte count */
@@ -457,7 +196,7 @@ struct eth_rx_desc {
457 u32 next_desc_ptr; /* Next descriptor pointer */ 196 u32 next_desc_ptr; /* Next descriptor pointer */
458}; 197};
459 198
460struct eth_tx_desc { 199struct tx_desc {
461 u32 cmd_sts; /* Command/status field */ 200 u32 cmd_sts; /* Command/status field */
462 u16 l4i_chk; /* CPU provided TCP checksum */ 201 u16 l4i_chk; /* CPU provided TCP checksum */
463 u16 byte_cnt; /* buffer byte count */ 202 u16 byte_cnt; /* buffer byte count */
@@ -468,18 +207,59 @@ struct eth_tx_desc {
468#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 207#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
469#endif 208#endif
470 209
471/* Unified struct for Rx and Tx operations. The user is not required to */ 210/* RX & TX descriptor command */
472/* be familier with neither Tx nor Rx descriptors. */ 211#define BUFFER_OWNED_BY_DMA 0x80000000
473struct pkt_info { 212
474 unsigned short byte_cnt; /* Descriptor buffer byte count */ 213/* RX & TX descriptor status */
475 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ 214#define ERROR_SUMMARY 0x00000001
476 unsigned int cmd_sts; /* Descriptor command status */ 215
477 dma_addr_t buf_ptr; /* Descriptor buffer pointer */ 216/* RX descriptor status */
478 struct sk_buff *return_info; /* User resource return information */ 217#define LAYER_4_CHECKSUM_OK 0x40000000
218#define RX_ENABLE_INTERRUPT 0x20000000
219#define RX_FIRST_DESC 0x08000000
220#define RX_LAST_DESC 0x04000000
221
222/* TX descriptor command */
223#define TX_ENABLE_INTERRUPT 0x00800000
224#define GEN_CRC 0x00400000
225#define TX_FIRST_DESC 0x00200000
226#define TX_LAST_DESC 0x00100000
227#define ZERO_PADDING 0x00080000
228#define GEN_IP_V4_CHECKSUM 0x00040000
229#define GEN_TCP_UDP_CHECKSUM 0x00020000
230#define UDP_FRAME 0x00010000
231
232#define TX_IHL_SHIFT 11
233
234
235/* global *******************************************************************/
236struct mv643xx_eth_shared_private {
237 /*
238 * Ethernet controller base address.
239 */
240 void __iomem *base;
241
242 /*
243 * Protects access to SMI_REG, which is shared between ports.
244 */
245 spinlock_t phy_lock;
246
247 /*
248 * Per-port MBUS window access register value.
249 */
250 u32 win_protect;
251
252 /*
253 * Hardware-specific parameters.
254 */
255 unsigned int t_clk;
256 int extended_rx_coal_limit;
257 int tx_bw_control_moved;
479}; 258};
480 259
481/* Ethernet port specific information */ 260
482struct mv643xx_mib_counters { 261/* per-port *****************************************************************/
262struct mib_counters {
483 u64 good_octets_received; 263 u64 good_octets_received;
484 u32 bad_octets_received; 264 u32 bad_octets_received;
485 u32 internal_mac_transmit_err; 265 u32 internal_mac_transmit_err;
@@ -512,461 +292,282 @@ struct mv643xx_mib_counters {
512 u32 late_collision; 292 u32 late_collision;
513}; 293};
514 294
515struct mv643xx_shared_private { 295struct rx_queue {
516 void __iomem *eth_base; 296 int index;
517
518 /* used to protect SMI_REG, which is shared across ports */
519 spinlock_t phy_lock;
520 297
521 u32 win_protect; 298 int rx_ring_size;
522
523 unsigned int t_clk;
524};
525
526struct mv643xx_private {
527 struct mv643xx_shared_private *shared;
528 int port_num; /* User Ethernet port number */
529
530 struct mv643xx_shared_private *shared_smi;
531
532 u32 rx_sram_addr; /* Base address of rx sram area */
533 u32 rx_sram_size; /* Size of rx sram area */
534 u32 tx_sram_addr; /* Base address of tx sram area */
535 u32 tx_sram_size; /* Size of tx sram area */
536 299
537 int rx_resource_err; /* Rx ring resource error flag */ 300 int rx_desc_count;
301 int rx_curr_desc;
302 int rx_used_desc;
538 303
539 /* Tx/Rx rings managment indexes fields. For driver use */ 304 struct rx_desc *rx_desc_area;
305 dma_addr_t rx_desc_dma;
306 int rx_desc_area_size;
307 struct sk_buff **rx_skb;
540 308
541 /* Next available and first returning Rx resource */ 309 struct timer_list rx_oom;
542 int rx_curr_desc_q, rx_used_desc_q; 310};
543 311
544 /* Next available and first returning Tx resource */ 312struct tx_queue {
545 int tx_curr_desc_q, tx_used_desc_q; 313 int index;
546 314
547#ifdef MV643XX_TX_FAST_REFILL 315 int tx_ring_size;
548 u32 tx_clean_threshold;
549#endif
550 316
551 struct eth_rx_desc *p_rx_desc_area; 317 int tx_desc_count;
552 dma_addr_t rx_desc_dma; 318 int tx_curr_desc;
553 int rx_desc_area_size; 319 int tx_used_desc;
554 struct sk_buff **rx_skb;
555 320
556 struct eth_tx_desc *p_tx_desc_area; 321 struct tx_desc *tx_desc_area;
557 dma_addr_t tx_desc_dma; 322 dma_addr_t tx_desc_dma;
558 int tx_desc_area_size; 323 int tx_desc_area_size;
559 struct sk_buff **tx_skb; 324 struct sk_buff **tx_skb;
325};
560 326
561 struct work_struct tx_timeout_task; 327struct mv643xx_eth_private {
328 struct mv643xx_eth_shared_private *shared;
329 int port_num;
562 330
563 struct net_device *dev; 331 struct net_device *dev;
564 struct napi_struct napi; 332
565 struct net_device_stats stats; 333 struct mv643xx_eth_shared_private *shared_smi;
566 struct mv643xx_mib_counters mib_counters; 334 int phy_addr;
335
567 spinlock_t lock; 336 spinlock_t lock;
568 /* Size of Tx Ring per queue */ 337
569 int tx_ring_size; 338 struct mib_counters mib_counters;
570 /* Number of tx descriptors in use */ 339 struct work_struct tx_timeout_task;
571 int tx_desc_count; 340 struct mii_if_info mii;
572 /* Size of Rx Ring per queue */
573 int rx_ring_size;
574 /* Number of rx descriptors in use */
575 int rx_desc_count;
576 341
577 /* 342 /*
578 * Used in case RX Ring is empty, which can be caused when 343 * RX state.
579 * system does not have resources (skb's)
580 */ 344 */
581 struct timer_list timeout; 345 int default_rx_ring_size;
582 346 unsigned long rx_desc_sram_addr;
583 u32 rx_int_coal; 347 int rx_desc_sram_size;
584 u32 tx_int_coal; 348 u8 rxq_mask;
585 struct mii_if_info mii; 349 int rxq_primary;
586}; 350 struct napi_struct napi;
351 struct rx_queue rxq[8];
587 352
588/* Static function declarations */ 353 /*
589static void eth_port_init(struct mv643xx_private *mp); 354 * TX state.
590static void eth_port_reset(struct mv643xx_private *mp); 355 */
591static void eth_port_start(struct net_device *dev); 356 int default_tx_ring_size;
592 357 unsigned long tx_desc_sram_addr;
593static void ethernet_phy_reset(struct mv643xx_private *mp); 358 int tx_desc_sram_size;
594 359 u8 txq_mask;
595static void eth_port_write_smi_reg(struct mv643xx_private *mp, 360 int txq_primary;
596 unsigned int phy_reg, unsigned int value); 361 struct tx_queue txq[8];
597 362#ifdef MV643XX_ETH_TX_FAST_REFILL
598static void eth_port_read_smi_reg(struct mv643xx_private *mp, 363 int tx_clean_threshold;
599 unsigned int phy_reg, unsigned int *value);
600
601static void eth_clear_mib_counters(struct mv643xx_private *mp);
602
603static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
604 struct pkt_info *p_pkt_info);
605static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
606 struct pkt_info *p_pkt_info);
607
608static void eth_port_uc_addr_get(struct mv643xx_private *mp,
609 unsigned char *p_addr);
610static void eth_port_uc_addr_set(struct mv643xx_private *mp,
611 unsigned char *p_addr);
612static void eth_port_set_multicast_list(struct net_device *);
613static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
614 unsigned int queues);
615static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
616 unsigned int queues);
617static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
618static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
619static int mv643xx_eth_open(struct net_device *);
620static int mv643xx_eth_stop(struct net_device *);
621static void eth_port_init_mac_tables(struct mv643xx_private *mp);
622#ifdef MV643XX_NAPI
623static int mv643xx_poll(struct napi_struct *napi, int budget);
624#endif 364#endif
625static int ethernet_phy_get(struct mv643xx_private *mp); 365};
626static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
627static int ethernet_phy_detect(struct mv643xx_private *mp);
628static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
629static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
630static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
631static const struct ethtool_ops mv643xx_ethtool_ops;
632 366
633static char mv643xx_driver_name[] = "mv643xx_eth";
634static char mv643xx_driver_version[] = "1.0";
635 367
636static inline u32 rdl(struct mv643xx_private *mp, int offset) 368/* port register accessors **************************************************/
369static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
637{ 370{
638 return readl(mp->shared->eth_base + offset); 371 return readl(mp->shared->base + offset);
639} 372}
640 373
641static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) 374static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
642{ 375{
643 writel(data, mp->shared->eth_base + offset); 376 writel(data, mp->shared->base + offset);
644} 377}
645 378
646/*
647 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
648 *
649 * Input : pointer to ethernet interface network device structure
650 * new mtu size
651 * Output : 0 upon success, -EINVAL upon failure
652 */
653static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
654{
655 if ((new_mtu > 9500) || (new_mtu < 64))
656 return -EINVAL;
657 379
658 dev->mtu = new_mtu; 380/* rxq/txq helper functions *************************************************/
659 if (!netif_running(dev)) 381static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
660 return 0;
661
662 /*
663 * Stop and then re-open the interface. This will allocate RX
664 * skbs of the new MTU.
665 * There is a possible danger that the open will not succeed,
666 * due to memory being full, which might fail the open function.
667 */
668 mv643xx_eth_stop(dev);
669 if (mv643xx_eth_open(dev)) {
670 printk(KERN_ERR "%s: Fatal error on opening device\n",
671 dev->name);
672 }
673
674 return 0;
675}
676
677/*
678 * mv643xx_eth_rx_refill_descs
679 *
680 * Fills / refills RX queue on a certain gigabit ethernet port
681 *
682 * Input : pointer to ethernet interface network device structure
683 * Output : N/A
684 */
685static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
686{ 382{
687 struct mv643xx_private *mp = netdev_priv(dev); 383 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
688 struct pkt_info pkt_info;
689 struct sk_buff *skb;
690 int unaligned;
691
692 while (mp->rx_desc_count < mp->rx_ring_size) {
693 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
694 if (!skb)
695 break;
696 mp->rx_desc_count++;
697 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
698 if (unaligned)
699 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
700 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
701 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
702 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
703 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
704 pkt_info.return_info = skb;
705 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
706 printk(KERN_ERR
707 "%s: Error allocating RX Ring\n", dev->name);
708 break;
709 }
710 skb_reserve(skb, ETH_HW_IP_ALIGN);
711 }
712 /*
713 * If RX ring is empty of SKB, set a timer to try allocating
714 * again at a later time.
715 */
716 if (mp->rx_desc_count == 0) {
717 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
718 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
719 add_timer(&mp->timeout);
720 }
721} 384}
722 385
723/* 386static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
724 * mv643xx_eth_rx_refill_descs_timer_wrapper
725 *
726 * Timer routine to wake up RX queue filling task. This function is
727 * used only in case the RX queue is empty, and all alloc_skb has
728 * failed (due to out of memory event).
729 *
730 * Input : pointer to ethernet interface network device structure
731 * Output : N/A
732 */
733static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
734{ 387{
735 mv643xx_eth_rx_refill_descs((struct net_device *)data); 388 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
736} 389}
737 390
738/* 391static void rxq_enable(struct rx_queue *rxq)
739 * mv643xx_eth_update_mac_address
740 *
741 * Update the MAC address of the port in the address table
742 *
743 * Input : pointer to ethernet interface network device structure
744 * Output : N/A
745 */
746static void mv643xx_eth_update_mac_address(struct net_device *dev)
747{ 392{
748 struct mv643xx_private *mp = netdev_priv(dev); 393 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
749 394 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
750 eth_port_init_mac_tables(mp);
751 eth_port_uc_addr_set(mp, dev->dev_addr);
752} 395}
753 396
754/* 397static void rxq_disable(struct rx_queue *rxq)
755 * mv643xx_eth_set_rx_mode
756 *
757 * Change from promiscuos to regular rx mode
758 *
759 * Input : pointer to ethernet interface network device structure
760 * Output : N/A
761 */
762static void mv643xx_eth_set_rx_mode(struct net_device *dev)
763{ 398{
764 struct mv643xx_private *mp = netdev_priv(dev); 399 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
765 u32 config_reg; 400 u8 mask = 1 << rxq->index;
766 401
767 config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num)); 402 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
768 if (dev->flags & IFF_PROMISC) 403 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
769 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; 404 udelay(10);
770 else
771 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
772 wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
773
774 eth_port_set_multicast_list(dev);
775} 405}
776 406
777/* 407static void txq_enable(struct tx_queue *txq)
778 * mv643xx_eth_set_mac_address
779 *
780 * Change the interface's mac address.
781 * No special hardware thing should be done because interface is always
782 * put in promiscuous mode.
783 *
784 * Input : pointer to ethernet interface network device structure and
785 * a pointer to the designated entry to be added to the cache.
786 * Output : zero upon success, negative upon failure
787 */
788static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
789{ 408{
790 int i; 409 struct mv643xx_eth_private *mp = txq_to_mp(txq);
791 410 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
792 for (i = 0; i < 6; i++)
793 /* +2 is for the offset of the HW addr type */
794 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
795 mv643xx_eth_update_mac_address(dev);
796 return 0;
797} 411}
798 412
799/* 413static void txq_disable(struct tx_queue *txq)
800 * mv643xx_eth_tx_timeout
801 *
802 * Called upon a timeout on transmitting a packet
803 *
804 * Input : pointer to ethernet interface network device structure.
805 * Output : N/A
806 */
807static void mv643xx_eth_tx_timeout(struct net_device *dev)
808{ 414{
809 struct mv643xx_private *mp = netdev_priv(dev); 415 struct mv643xx_eth_private *mp = txq_to_mp(txq);
810 416 u8 mask = 1 << txq->index;
811 printk(KERN_INFO "%s: TX timeout ", dev->name);
812 417
813 /* Do the reset outside of interrupt context */ 418 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
814 schedule_work(&mp->tx_timeout_task); 419 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
420 udelay(10);
815} 421}
816 422
817/* 423static void __txq_maybe_wake(struct tx_queue *txq)
818 * mv643xx_eth_tx_timeout_task
819 *
820 * Actual routine to reset the adapter when a timeout on Tx has occurred
821 */
822static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
823{ 424{
824 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, 425 struct mv643xx_eth_private *mp = txq_to_mp(txq);
825 tx_timeout_task);
826 struct net_device *dev = mp->dev;
827 426
828 if (!netif_running(dev)) 427 /*
829 return; 428 * netif_{stop,wake}_queue() flow control only applies to
429 * the primary queue.
430 */
431 BUG_ON(txq->index != mp->txq_primary);
830 432
831 netif_stop_queue(dev); 433 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
434 netif_wake_queue(mp->dev);
435}
832 436
833 eth_port_reset(mp);
834 eth_port_start(dev);
835 437
836 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) 438/* rx ***********************************************************************/
837 netif_wake_queue(dev); 439static void txq_reclaim(struct tx_queue *txq, int force);
838}
839 440
840/** 441static void rxq_refill(struct rx_queue *rxq)
841 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
842 *
843 * If force is non-zero, frees uncompleted descriptors as well
844 */
845static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
846{ 442{
847 struct mv643xx_private *mp = netdev_priv(dev); 443 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
848 struct eth_tx_desc *desc;
849 u32 cmd_sts;
850 struct sk_buff *skb;
851 unsigned long flags; 444 unsigned long flags;
852 int tx_index;
853 dma_addr_t addr;
854 int count;
855 int released = 0;
856 445
857 while (mp->tx_desc_count > 0) { 446 spin_lock_irqsave(&mp->lock, flags);
858 spin_lock_irqsave(&mp->lock, flags);
859
860 /* tx_desc_count might have changed before acquiring the lock */
861 if (mp->tx_desc_count <= 0) {
862 spin_unlock_irqrestore(&mp->lock, flags);
863 return released;
864 }
865
866 tx_index = mp->tx_used_desc_q;
867 desc = &mp->p_tx_desc_area[tx_index];
868 cmd_sts = desc->cmd_sts;
869 447
870 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { 448 while (rxq->rx_desc_count < rxq->rx_ring_size) {
871 spin_unlock_irqrestore(&mp->lock, flags); 449 int skb_size;
872 return released; 450 struct sk_buff *skb;
873 } 451 int unaligned;
452 int rx;
874 453
875 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; 454 /*
876 mp->tx_desc_count--; 455 * Reserve 2+14 bytes for an ethernet header (the
456 * hardware automatically prepends 2 bytes of dummy
457 * data to each received packet), 4 bytes for a VLAN
458 * header, and 4 bytes for the trailing FCS -- 24
459 * bytes total.
460 */
461 skb_size = mp->dev->mtu + 24;
877 462
878 addr = desc->buf_ptr; 463 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
879 count = desc->byte_cnt; 464 if (skb == NULL)
880 skb = mp->tx_skb[tx_index]; 465 break;
881 if (skb)
882 mp->tx_skb[tx_index] = NULL;
883 466
884 if (cmd_sts & ETH_ERROR_SUMMARY) { 467 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
885 printk("%s: Error in TX\n", dev->name); 468 if (unaligned)
886 dev->stats.tx_errors++; 469 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
887 }
888 470
889 spin_unlock_irqrestore(&mp->lock, flags); 471 rxq->rx_desc_count++;
472 rx = rxq->rx_used_desc;
473 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
890 474
891 if (cmd_sts & ETH_TX_FIRST_DESC) 475 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
892 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 476 skb_size, DMA_FROM_DEVICE);
893 else 477 rxq->rx_desc_area[rx].buf_size = skb_size;
894 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); 478 rxq->rx_skb[rx] = skb;
479 wmb();
480 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
481 RX_ENABLE_INTERRUPT;
482 wmb();
895 483
896 if (skb) 484 /*
897 dev_kfree_skb_irq(skb); 485 * The hardware automatically prepends 2 bytes of
486 * dummy data to each received packet, so that the
487 * IP header ends up 16-byte aligned.
488 */
489 skb_reserve(skb, 2);
490 }
898 491
899 released = 1; 492 if (rxq->rx_desc_count != rxq->rx_ring_size) {
493 rxq->rx_oom.expires = jiffies + (HZ / 10);
494 add_timer(&rxq->rx_oom);
900 } 495 }
901 496
902 return released; 497 spin_unlock_irqrestore(&mp->lock, flags);
903} 498}
904 499
905static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) 500static inline void rxq_refill_timer_wrapper(unsigned long data)
906{ 501{
907 struct mv643xx_private *mp = netdev_priv(dev); 502 rxq_refill((struct rx_queue *)data);
908
909 if (mv643xx_eth_free_tx_descs(dev, 0) &&
910 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
911 netif_wake_queue(dev);
912} 503}
913 504
914static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) 505static int rxq_process(struct rx_queue *rxq, int budget)
915{ 506{
916 mv643xx_eth_free_tx_descs(dev, 1); 507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
917} 508 struct net_device_stats *stats = &mp->dev->stats;
509 int rx;
918 510
919/* 511 rx = 0;
920 * mv643xx_eth_receive 512 while (rx < budget) {
921 * 513 struct rx_desc *rx_desc;
922 * This function is forward packets that are received from the port's 514 unsigned int cmd_sts;
923 * queues toward kernel core or FastRoute them to another interface. 515 struct sk_buff *skb;
924 * 516 unsigned long flags;
925 * Input : dev - a pointer to the required interface 517
926 * max - maximum number to receive (0 means unlimted) 518 spin_lock_irqsave(&mp->lock, flags);
927 * 519
928 * Output : number of served packets 520 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
929 */ 521
930static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) 522 cmd_sts = rx_desc->cmd_sts;
931{ 523 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
932 struct mv643xx_private *mp = netdev_priv(dev); 524 spin_unlock_irqrestore(&mp->lock, flags);
933 struct net_device_stats *stats = &dev->stats; 525 break;
934 unsigned int received_packets = 0; 526 }
935 struct sk_buff *skb; 527 rmb();
936 struct pkt_info pkt_info; 528
529 skb = rxq->rx_skb[rxq->rx_curr_desc];
530 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
937 531
938 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { 532 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
939 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, 533
940 DMA_FROM_DEVICE); 534 spin_unlock_irqrestore(&mp->lock, flags);
941 mp->rx_desc_count--; 535
942 received_packets++; 536 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
537 mp->dev->mtu + 24, DMA_FROM_DEVICE);
538 rxq->rx_desc_count--;
539 rx++;
943 540
944 /* 541 /*
945 * Update statistics. 542 * Update statistics.
946 * Note byte count includes 4 byte CRC count 543 *
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
947 */ 548 */
948 stats->rx_packets++; 549 stats->rx_packets++;
949 stats->rx_bytes += pkt_info.byte_cnt; 550 stats->rx_bytes += rx_desc->byte_cnt - 2;
950 skb = pkt_info.return_info; 551
951 /* 552 /*
952 * In case received a packet without first / last bits on OR 553 * In case we received a packet without first / last bits
953 * the error summary bit is on, the packets needs to be dropeed. 554 * on, or the error summary bit is set, the packet needs
555 * to be dropped.
954 */ 556 */
955 if (((pkt_info.cmd_sts 557 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
956 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != 558 (RX_FIRST_DESC | RX_LAST_DESC))
957 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) 559 || (cmd_sts & ERROR_SUMMARY)) {
958 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
959 stats->rx_dropped++; 560 stats->rx_dropped++;
960 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | 561
961 ETH_RX_LAST_DESC)) != 562 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
962 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { 563 (RX_FIRST_DESC | RX_LAST_DESC)) {
963 if (net_ratelimit()) 564 if (net_ratelimit())
964 printk(KERN_ERR 565 dev_printk(KERN_ERR, &mp->dev->dev,
965 "%s: Received packet spread " 566 "received packet spanning "
966 "on multiple descriptors\n", 567 "multiple descriptors\n");
967 dev->name);
968 } 568 }
969 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) 569
570 if (cmd_sts & ERROR_SUMMARY)
970 stats->rx_errors++; 571 stats->rx_errors++;
971 572
972 dev_kfree_skb_irq(skb); 573 dev_kfree_skb_irq(skb);
@@ -975,2391 +576,2003 @@ static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
975 * The -4 is for the CRC in the trailer of the 576 * The -4 is for the CRC in the trailer of the
976 * received packet 577 * received packet
977 */ 578 */
978 skb_put(skb, pkt_info.byte_cnt - 4); 579 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
979 580
980 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { 581 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
981 skb->ip_summed = CHECKSUM_UNNECESSARY; 582 skb->ip_summed = CHECKSUM_UNNECESSARY;
982 skb->csum = htons( 583 skb->csum = htons(
983 (pkt_info.cmd_sts & 0x0007fff8) >> 3); 584 (cmd_sts & 0x0007fff8) >> 3);
984 } 585 }
985 skb->protocol = eth_type_trans(skb, dev); 586 skb->protocol = eth_type_trans(skb, mp->dev);
986#ifdef MV643XX_NAPI 587#ifdef MV643XX_ETH_NAPI
987 netif_receive_skb(skb); 588 netif_receive_skb(skb);
988#else 589#else
989 netif_rx(skb); 590 netif_rx(skb);
990#endif 591#endif
991 } 592 }
992 dev->last_rx = jiffies; 593
594 mp->dev->last_rx = jiffies;
993 } 595 }
994 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
995 596
996 return received_packets; 597 rxq_refill(rxq);
598
599 return rx;
997} 600}
998 601
999/* Set the mv643xx port configuration register for the speed/duplex mode. */ 602#ifdef MV643XX_ETH_NAPI
1000static void mv643xx_eth_update_pscr(struct net_device *dev, 603static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1001 struct ethtool_cmd *ecmd)
1002{ 604{
1003 struct mv643xx_private *mp = netdev_priv(dev); 605 struct mv643xx_eth_private *mp;
1004 int port_num = mp->port_num; 606 int rx;
1005 u32 o_pscr, n_pscr; 607 int i;
1006 unsigned int queues;
1007 608
1008 o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 609 mp = container_of(napi, struct mv643xx_eth_private, napi);
1009 n_pscr = o_pscr;
1010 610
1011 /* clear speed, duplex and rx buffer size fields */ 611#ifdef MV643XX_ETH_TX_FAST_REFILL
1012 n_pscr &= ~(SET_MII_SPEED_TO_100 | 612 if (++mp->tx_clean_threshold > 5) {
1013 SET_GMII_SPEED_TO_1000 | 613 mp->tx_clean_threshold = 0;
1014 SET_FULL_DUPLEX_MODE | 614 for (i = 0; i < 8; i++)
1015 MAX_RX_PACKET_MASK); 615 if (mp->txq_mask & (1 << i))
1016 616 txq_reclaim(mp->txq + i, 0);
1017 if (ecmd->duplex == DUPLEX_FULL)
1018 n_pscr |= SET_FULL_DUPLEX_MODE;
1019
1020 if (ecmd->speed == SPEED_1000)
1021 n_pscr |= SET_GMII_SPEED_TO_1000 |
1022 MAX_RX_PACKET_9700BYTE;
1023 else {
1024 if (ecmd->speed == SPEED_100)
1025 n_pscr |= SET_MII_SPEED_TO_100;
1026 n_pscr |= MAX_RX_PACKET_1522BYTE;
1027 } 617 }
618#endif
1028 619
1029 if (n_pscr != o_pscr) { 620 rx = 0;
1030 if ((o_pscr & SERIAL_PORT_ENABLE) == 0) 621 for (i = 7; rx < budget && i >= 0; i--)
1031 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 622 if (mp->rxq_mask & (1 << i))
1032 else { 623 rx += rxq_process(mp->rxq + i, budget - rx);
1033 queues = mv643xx_eth_port_disable_tx(mp); 624
1034 625 if (rx < budget) {
1035 o_pscr &= ~SERIAL_PORT_ENABLE; 626 netif_rx_complete(mp->dev, napi);
1036 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr); 627 wrl(mp, INT_CAUSE(mp->port_num), 0);
1037 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 628 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1038 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 629 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1039 if (queues)
1040 mv643xx_eth_port_enable_tx(mp, queues);
1041 }
1042 } 630 }
631
632 return rx;
1043} 633}
634#endif
1044 635
1045/*
1046 * mv643xx_eth_int_handler
1047 *
1048 * Main interrupt handler for the gigbit ethernet ports
1049 *
1050 * Input : irq - irq number (not used)
1051 * dev_id - a pointer to the required interface's data structure
1052 * regs - not used
1053 * Output : N/A
1054 */
1055 636
1056static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) 637/* tx ***********************************************************************/
638static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1057{ 639{
1058 struct net_device *dev = (struct net_device *)dev_id; 640 int frag;
1059 struct mv643xx_private *mp = netdev_priv(dev);
1060 u32 eth_int_cause, eth_int_cause_ext = 0;
1061 unsigned int port_num = mp->port_num;
1062
1063 /* Read interrupt cause registers */
1064 eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
1065 ETH_INT_UNMASK_ALL;
1066 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1067 eth_int_cause_ext = rdl(mp,
1068 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1069 ETH_INT_UNMASK_ALL_EXT;
1070 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
1071 ~eth_int_cause_ext);
1072 }
1073
1074 /* PHY status changed */
1075 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1076 struct ethtool_cmd cmd;
1077 641
1078 if (mii_link_ok(&mp->mii)) { 642 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1079 mii_ethtool_gset(&mp->mii, &cmd); 643 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
1080 mv643xx_eth_update_pscr(dev, &cmd); 644 if (fragp->size <= 8 && fragp->page_offset & 7)
1081 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); 645 return 1;
1082 if (!netif_carrier_ok(dev)) {
1083 netif_carrier_on(dev);
1084 if (mp->tx_ring_size - mp->tx_desc_count >=
1085 MAX_DESCS_PER_SKB)
1086 netif_wake_queue(dev);
1087 }
1088 } else if (netif_carrier_ok(dev)) {
1089 netif_stop_queue(dev);
1090 netif_carrier_off(dev);
1091 }
1092 } 646 }
1093 647
1094#ifdef MV643XX_NAPI 648 return 0;
1095 if (eth_int_cause & ETH_INT_CAUSE_RX) { 649}
1096 /* schedule the NAPI poll routine to maintain port */
1097 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1098 650
1099 /* wait for previous write to complete */ 651static int txq_alloc_desc_index(struct tx_queue *txq)
1100 rdl(mp, INTERRUPT_MASK_REG(port_num)); 652{
653 int tx_desc_curr;
1101 654
1102 netif_rx_schedule(dev, &mp->napi); 655 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1103 }
1104#else
1105 if (eth_int_cause & ETH_INT_CAUSE_RX)
1106 mv643xx_eth_receive_queue(dev, INT_MAX);
1107#endif
1108 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
1109 mv643xx_eth_free_completed_tx_descs(dev);
1110 656
1111 /* 657 tx_desc_curr = txq->tx_curr_desc;
1112 * If no real interrupt occured, exit. 658 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
1113 * This can happen when using gigE interrupt coalescing mechanism.
1114 */
1115 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
1116 return IRQ_NONE;
1117 659
1118 return IRQ_HANDLED; 660 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
1119}
1120 661
1121#ifdef MV643XX_COAL 662 return tx_desc_curr;
663}
1122 664
1123/* 665static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
1124 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1125 *
1126 * DESCRIPTION:
1127 * This routine sets the RX coalescing interrupt mechanism parameter.
1128 * This parameter is a timeout counter, that counts in 64 t_clk
1129 * chunks ; that when timeout event occurs a maskable interrupt
1130 * occurs.
1131 * The parameter is calculated using the tClk of the MV-643xx chip
1132 * , and the required delay of the interrupt in usec.
1133 *
1134 * INPUT:
1135 * struct mv643xx_private *mp Ethernet port
1136 * unsigned int delay Delay in usec
1137 *
1138 * OUTPUT:
1139 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1140 *
1141 * RETURN:
1142 * The interrupt coalescing value set in the gigE port.
1143 *
1144 */
1145static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
1146 unsigned int delay)
1147{ 666{
1148 unsigned int port_num = mp->port_num; 667 int nr_frags = skb_shinfo(skb)->nr_frags;
1149 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; 668 int frag;
1150 669
1151 /* Set RX Coalescing mechanism */ 670 for (frag = 0; frag < nr_frags; frag++) {
1152 wrl(mp, SDMA_CONFIG_REG(port_num), 671 skb_frag_t *this_frag;
1153 ((coal & 0x3fff) << 8) | 672 int tx_index;
1154 (rdl(mp, SDMA_CONFIG_REG(port_num)) 673 struct tx_desc *desc;
1155 & 0xffc000ff));
1156 674
1157 return coal; 675 this_frag = &skb_shinfo(skb)->frags[frag];
1158} 676 tx_index = txq_alloc_desc_index(txq);
1159#endif 677 desc = &txq->tx_desc_area[tx_index];
1160 678
1161/* 679 /*
1162 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path 680 * The last fragment will generate an interrupt
1163 * 681 * which will free the skb on TX completion.
1164 * DESCRIPTION: 682 */
1165 * This routine sets the TX coalescing interrupt mechanism parameter. 683 if (frag == nr_frags - 1) {
1166 * This parameter is a timeout counter, that counts in 64 t_clk 684 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
1167 * chunks ; that when timeout event occurs a maskable interrupt 685 ZERO_PADDING | TX_LAST_DESC |
1168 * occurs. 686 TX_ENABLE_INTERRUPT;
1169 * The parameter is calculated using the t_cLK frequency of the 687 txq->tx_skb[tx_index] = skb;
1170 * MV-643xx chip and the required delay in the interrupt in uSec 688 } else {
1171 * 689 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
1172 * INPUT: 690 txq->tx_skb[tx_index] = NULL;
1173 * struct mv643xx_private *mp Ethernet port 691 }
1174 * unsigned int delay Delay in uSeconds
1175 *
1176 * OUTPUT:
1177 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1178 *
1179 * RETURN:
1180 * The interrupt coalescing value set in the gigE port.
1181 *
1182 */
1183static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
1184 unsigned int delay)
1185{
1186 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1187 692
1188 /* Set TX Coalescing mechanism */ 693 desc->l4i_chk = 0;
1189 wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4); 694 desc->byte_cnt = this_frag->size;
695 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
696 this_frag->page_offset,
697 this_frag->size,
698 DMA_TO_DEVICE);
699 }
700}
1190 701
1191 return coal; 702static inline __be16 sum16_as_be(__sum16 sum)
703{
704 return (__force __be16)sum;
1192} 705}
1193 706
1194/* 707static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1195 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1196 *
1197 * DESCRIPTION:
1198 * This function prepares a Rx chained list of descriptors and packet
1199 * buffers in a form of a ring. The routine must be called after port
1200 * initialization routine and before port start routine.
1201 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1202 * devices in the system (i.e. DRAM). This function uses the ethernet
1203 * struct 'virtual to physical' routine (set by the user) to set the ring
1204 * with physical addresses.
1205 *
1206 * INPUT:
1207 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1208 *
1209 * OUTPUT:
1210 * The routine updates the Ethernet port control struct with information
1211 * regarding the Rx descriptors and buffers.
1212 *
1213 * RETURN:
1214 * None.
1215 */
1216static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1217{ 708{
1218 volatile struct eth_rx_desc *p_rx_desc; 709 int nr_frags = skb_shinfo(skb)->nr_frags;
1219 int rx_desc_num = mp->rx_ring_size; 710 int tx_index;
1220 int i; 711 struct tx_desc *desc;
712 u32 cmd_sts;
713 int length;
1221 714
1222 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 715 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1223 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; 716
1224 for (i = 0; i < rx_desc_num; i++) { 717 tx_index = txq_alloc_desc_index(txq);
1225 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + 718 desc = &txq->tx_desc_area[tx_index];
1226 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); 719
720 if (nr_frags) {
721 txq_submit_frag_skb(txq, skb);
722
723 length = skb_headlen(skb);
724 txq->tx_skb[tx_index] = NULL;
725 } else {
726 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
727 length = skb->len;
728 txq->tx_skb[tx_index] = skb;
1227 } 729 }
1228 730
1229 /* Save Rx desc pointer to driver struct. */ 731 desc->byte_cnt = length;
1230 mp->rx_curr_desc_q = 0; 732 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1231 mp->rx_used_desc_q = 0;
1232 733
1233 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); 734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1234} 735 BUG_ON(skb->protocol != htons(ETH_P_IP));
1235 736
1236/* 737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
1237 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. 738 GEN_IP_V4_CHECKSUM |
1238 * 739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
1239 * DESCRIPTION:
1240 * This function prepares a Tx chained list of descriptors and packet
1241 * buffers in a form of a ring. The routine must be called after port
1242 * initialization routine and before port start routine.
1243 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1244 * devices in the system (i.e. DRAM). This function uses the ethernet
1245 * struct 'virtual to physical' routine (set by the user) to set the ring
1246 * with physical addresses.
1247 *
1248 * INPUT:
1249 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1250 *
1251 * OUTPUT:
1252 * The routine updates the Ethernet port control struct with information
1253 * regarding the Tx descriptors and buffers.
1254 *
1255 * RETURN:
1256 * None.
1257 */
1258static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1259{
1260 int tx_desc_num = mp->tx_ring_size;
1261 struct eth_tx_desc *p_tx_desc;
1262 int i;
1263 740
1264 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 741 switch (ip_hdr(skb)->protocol) {
1265 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; 742 case IPPROTO_UDP:
1266 for (i = 0; i < tx_desc_num; i++) { 743 cmd_sts |= UDP_FRAME;
1267 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + 744 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
1268 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); 745 break;
746 case IPPROTO_TCP:
747 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
748 break;
749 default:
750 BUG();
751 }
752 } else {
753 /* Errata BTS #50, IHL must be 5 if no HW checksum */
754 cmd_sts |= 5 << TX_IHL_SHIFT;
755 desc->l4i_chk = 0;
1269 } 756 }
1270 757
1271 mp->tx_curr_desc_q = 0; 758 /* ensure all other descriptors are written before first cmd_sts */
1272 mp->tx_used_desc_q = 0; 759 wmb();
760 desc->cmd_sts = cmd_sts;
761
762 /* ensure all descriptors are written before poking hardware */
763 wmb();
764 txq_enable(txq);
1273 765
1274 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); 766 txq->tx_desc_count += nr_frags + 1;
1275} 767}
1276 768
1277static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 769static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1278{ 770{
1279 struct mv643xx_private *mp = netdev_priv(dev); 771 struct mv643xx_eth_private *mp = netdev_priv(dev);
1280 int err; 772 struct net_device_stats *stats = &dev->stats;
773 struct tx_queue *txq;
774 unsigned long flags;
1281 775
1282 spin_lock_irq(&mp->lock); 776 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1283 err = mii_ethtool_sset(&mp->mii, cmd); 777 stats->tx_dropped++;
1284 spin_unlock_irq(&mp->lock); 778 dev_printk(KERN_DEBUG, &dev->dev,
779 "failed to linearize skb with tiny "
780 "unaligned fragment\n");
781 return NETDEV_TX_BUSY;
782 }
1285 783
1286 return err; 784 spin_lock_irqsave(&mp->lock, flags);
1287}
1288 785
1289static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 786 txq = mp->txq + mp->txq_primary;
1290{
1291 struct mv643xx_private *mp = netdev_priv(dev);
1292 int err;
1293 787
1294 spin_lock_irq(&mp->lock); 788 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
1295 err = mii_ethtool_gset(&mp->mii, cmd); 789 spin_unlock_irqrestore(&mp->lock, flags);
1296 spin_unlock_irq(&mp->lock); 790 if (txq->index == mp->txq_primary && net_ratelimit())
791 dev_printk(KERN_ERR, &dev->dev,
792 "primary tx queue full?!\n");
793 kfree_skb(skb);
794 return NETDEV_TX_OK;
795 }
1297 796
1298 /* The PHY may support 1000baseT_Half, but the mv643xx does not */ 797 txq_submit_skb(txq, skb);
1299 cmd->supported &= ~SUPPORTED_1000baseT_Half; 798 stats->tx_bytes += skb->len;
1300 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 799 stats->tx_packets++;
800 dev->trans_start = jiffies;
1301 801
1302 return err; 802 if (txq->index == mp->txq_primary) {
803 int entries_left;
804
805 entries_left = txq->tx_ring_size - txq->tx_desc_count;
806 if (entries_left < MAX_DESCS_PER_SKB)
807 netif_stop_queue(dev);
808 }
809
810 spin_unlock_irqrestore(&mp->lock, flags);
811
812 return NETDEV_TX_OK;
1303} 813}
1304 814
815
816/* tx rate control **********************************************************/
1305/* 817/*
1306 * mv643xx_eth_open 818 * Set total maximum TX rate (shared by all TX queues for this port)
1307 * 819 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1308 * This function is called when openning the network device. The function
1309 * should initialize all the hardware, initialize cyclic Rx/Tx
1310 * descriptors chain and buffers and allocate an IRQ to the network
1311 * device.
1312 *
1313 * Input : a pointer to the network device structure
1314 *
1315 * Output : zero of success , nonzero if fails.
1316 */ 820 */
1317 821static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1318static int mv643xx_eth_open(struct net_device *dev)
1319{ 822{
1320 struct mv643xx_private *mp = netdev_priv(dev); 823 int token_rate;
1321 unsigned int port_num = mp->port_num; 824 int mtu;
1322 unsigned int size; 825 int bucket_size;
1323 int err;
1324 826
1325 /* Clear any pending ethernet port interrupts */ 827 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1326 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); 828 if (token_rate > 1023)
1327 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 829 token_rate = 1023;
1328 /* wait for previous write to complete */
1329 rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
1330 830
1331 err = request_irq(dev->irq, mv643xx_eth_int_handler, 831 mtu = (mp->dev->mtu + 255) >> 8;
1332 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); 832 if (mtu > 63)
1333 if (err) { 833 mtu = 63;
1334 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1335 return -EAGAIN;
1336 }
1337 834
1338 eth_port_init(mp); 835 bucket_size = (burst + 255) >> 8;
836 if (bucket_size > 65535)
837 bucket_size = 65535;
1339 838
1340 memset(&mp->timeout, 0, sizeof(struct timer_list)); 839 if (mp->shared->tx_bw_control_moved) {
1341 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; 840 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
1342 mp->timeout.data = (unsigned long)dev; 841 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
1343 842 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
1344 /* Allocate RX and TX skb rings */ 843 } else {
1345 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, 844 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
1346 GFP_KERNEL); 845 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
1347 if (!mp->rx_skb) { 846 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
1348 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1349 err = -ENOMEM;
1350 goto out_free_irq;
1351 }
1352 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1353 GFP_KERNEL);
1354 if (!mp->tx_skb) {
1355 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1356 err = -ENOMEM;
1357 goto out_free_rx_skb;
1358 } 847 }
848}
1359 849
1360 /* Allocate TX ring */ 850static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1361 mp->tx_desc_count = 0; 851{
1362 size = mp->tx_ring_size * sizeof(struct eth_tx_desc); 852 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1363 mp->tx_desc_area_size = size; 853 int token_rate;
1364 854 int bucket_size;
1365 if (mp->tx_sram_size) {
1366 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1367 mp->tx_sram_size);
1368 mp->tx_desc_dma = mp->tx_sram_addr;
1369 } else
1370 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1371 &mp->tx_desc_dma,
1372 GFP_KERNEL);
1373 855
1374 if (!mp->p_tx_desc_area) { 856 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1375 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", 857 if (token_rate > 1023)
1376 dev->name, size); 858 token_rate = 1023;
1377 err = -ENOMEM;
1378 goto out_free_tx_skb;
1379 }
1380 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1381 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
1382
1383 ether_init_tx_desc_ring(mp);
1384
1385 /* Allocate RX ring */
1386 mp->rx_desc_count = 0;
1387 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
1388 mp->rx_desc_area_size = size;
1389
1390 if (mp->rx_sram_size) {
1391 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1392 mp->rx_sram_size);
1393 mp->rx_desc_dma = mp->rx_sram_addr;
1394 } else
1395 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1396 &mp->rx_desc_dma,
1397 GFP_KERNEL);
1398 859
1399 if (!mp->p_rx_desc_area) { 860 bucket_size = (burst + 255) >> 8;
1400 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", 861 if (bucket_size > 65535)
1401 dev->name, size); 862 bucket_size = 65535;
1402 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1403 dev->name);
1404 if (mp->rx_sram_size)
1405 iounmap(mp->p_tx_desc_area);
1406 else
1407 dma_free_coherent(NULL, mp->tx_desc_area_size,
1408 mp->p_tx_desc_area, mp->tx_desc_dma);
1409 err = -ENOMEM;
1410 goto out_free_tx_skb;
1411 }
1412 memset((void *)mp->p_rx_desc_area, 0, size);
1413 863
1414 ether_init_rx_desc_ring(mp); 864 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
1415 865 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
1416 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ 866 (bucket_size << 10) | token_rate);
867}
1417 868
1418#ifdef MV643XX_NAPI 869static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1419 napi_enable(&mp->napi); 870{
1420#endif 871 struct mv643xx_eth_private *mp = txq_to_mp(txq);
872 int off;
873 u32 val;
1421 874
1422 eth_port_start(dev); 875 /*
876 * Turn on fixed priority mode.
877 */
878 if (mp->shared->tx_bw_control_moved)
879 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
880 else
881 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1423 882
1424 /* Interrupt Coalescing */ 883 val = rdl(mp, off);
884 val |= 1 << txq->index;
885 wrl(mp, off, val);
886}
1425 887
1426#ifdef MV643XX_COAL 888static void txq_set_wrr(struct tx_queue *txq, int weight)
1427 mp->rx_int_coal = 889{
1428 eth_port_set_rx_coal(mp, MV643XX_RX_COAL); 890 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1429#endif 891 int off;
892 u32 val;
1430 893
1431 mp->tx_int_coal = 894 /*
1432 eth_port_set_tx_coal(mp, MV643XX_TX_COAL); 895 * Turn off fixed priority mode.
896 */
897 if (mp->shared->tx_bw_control_moved)
898 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
899 else
900 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1433 901
1434 /* Unmask phy and link status changes interrupts */ 902 val = rdl(mp, off);
1435 wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); 903 val &= ~(1 << txq->index);
904 wrl(mp, off, val);
1436 905
1437 /* Unmask RX buffer and TX end interrupt */ 906 /*
1438 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 907 * Configure WRR weight for this queue.
908 */
909 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1439 910
1440 return 0; 911 val = rdl(mp, off);
912 val = (val & ~0xff) | (weight & 0xff);
913 wrl(mp, off, val);
914}
1441 915
1442out_free_tx_skb:
1443 kfree(mp->tx_skb);
1444out_free_rx_skb:
1445 kfree(mp->rx_skb);
1446out_free_irq:
1447 free_irq(dev->irq, dev);
1448 916
1449 return err; 917/* mii management interface *************************************************/
1450} 918#define SMI_BUSY 0x10000000
919#define SMI_READ_VALID 0x08000000
920#define SMI_OPCODE_READ 0x04000000
921#define SMI_OPCODE_WRITE 0x00000000
1451 922
1452static void mv643xx_eth_free_tx_rings(struct net_device *dev) 923static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
924 unsigned int reg, unsigned int *value)
1453{ 925{
1454 struct mv643xx_private *mp = netdev_priv(dev); 926 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
927 unsigned long flags;
928 int i;
1455 929
1456 /* Stop Tx Queues */ 930 /* the SMI register is a shared resource */
1457 mv643xx_eth_port_disable_tx(mp); 931 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1458 932
1459 /* Free outstanding skb's on TX ring */ 933 /* wait for the SMI register to become available */
1460 mv643xx_eth_free_all_tx_descs(dev); 934 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
935 if (i == 1000) {
936 printk("%s: PHY busy timeout\n", mp->dev->name);
937 goto out;
938 }
939 udelay(10);
940 }
1461 941
1462 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); 942 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1463 943
1464 /* Free TX ring */ 944 /* now wait for the data to be valid */
1465 if (mp->tx_sram_size) 945 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
1466 iounmap(mp->p_tx_desc_area); 946 if (i == 1000) {
1467 else 947 printk("%s: PHY read timeout\n", mp->dev->name);
1468 dma_free_coherent(NULL, mp->tx_desc_area_size, 948 goto out;
1469 mp->p_tx_desc_area, mp->tx_desc_dma); 949 }
950 udelay(10);
951 }
952
953 *value = readl(smi_reg) & 0xffff;
954out:
955 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1470} 956}
1471 957
1472static void mv643xx_eth_free_rx_rings(struct net_device *dev) 958static void smi_reg_write(struct mv643xx_eth_private *mp,
959 unsigned int addr,
960 unsigned int reg, unsigned int value)
1473{ 961{
1474 struct mv643xx_private *mp = netdev_priv(dev); 962 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
1475 int curr; 963 unsigned long flags;
964 int i;
1476 965
1477 /* Stop RX Queues */ 966 /* the SMI register is a shared resource */
1478 mv643xx_eth_port_disable_rx(mp); 967 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1479 968
1480 /* Free preallocated skb's on RX rings */ 969 /* wait for the SMI register to become available */
1481 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { 970 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
1482 if (mp->rx_skb[curr]) { 971 if (i == 1000) {
1483 dev_kfree_skb(mp->rx_skb[curr]); 972 printk("%s: PHY busy timeout\n", mp->dev->name);
1484 mp->rx_desc_count--; 973 goto out;
1485 } 974 }
975 udelay(10);
1486 } 976 }
1487 977
1488 if (mp->rx_desc_count) 978 writel(SMI_OPCODE_WRITE | (reg << 21) |
1489 printk(KERN_ERR 979 (addr << 16) | (value & 0xffff), smi_reg);
1490 "%s: Error in freeing Rx Ring. %d skb's still" 980out:
1491 " stuck in RX Ring - ignoring them\n", dev->name, 981 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1492 mp->rx_desc_count);
1493 /* Free RX ring */
1494 if (mp->rx_sram_size)
1495 iounmap(mp->p_rx_desc_area);
1496 else
1497 dma_free_coherent(NULL, mp->rx_desc_area_size,
1498 mp->p_rx_desc_area, mp->rx_desc_dma);
1499} 982}
1500 983
1501/*
1502 * mv643xx_eth_stop
1503 *
1504 * This function is used when closing the network device.
1505 * It updates the hardware,
1506 * release all memory that holds buffers and descriptors and release the IRQ.
1507 * Input : a pointer to the device structure
1508 * Output : zero if success , nonzero if fails
1509 */
1510 984
1511static int mv643xx_eth_stop(struct net_device *dev) 985/* mib counters *************************************************************/
986static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1512{ 987{
1513 struct mv643xx_private *mp = netdev_priv(dev); 988 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1514 unsigned int port_num = mp->port_num; 989}
1515 990
1516 /* Mask all interrupts on ethernet port */ 991static void mib_counters_clear(struct mv643xx_eth_private *mp)
1517 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 992{
1518 /* wait for previous write to complete */ 993 int i;
1519 rdl(mp, INTERRUPT_MASK_REG(port_num));
1520 994
1521#ifdef MV643XX_NAPI 995 for (i = 0; i < 0x80; i += 4)
1522 napi_disable(&mp->napi); 996 mib_read(mp, i);
1523#endif 997}
1524 netif_carrier_off(dev); 998
1525 netif_stop_queue(dev); 999static void mib_counters_update(struct mv643xx_eth_private *mp)
1000{
1001 struct mib_counters *p = &mp->mib_counters;
1002
1003 p->good_octets_received += mib_read(mp, 0x00);
1004 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1005 p->bad_octets_received += mib_read(mp, 0x08);
1006 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1007 p->good_frames_received += mib_read(mp, 0x10);
1008 p->bad_frames_received += mib_read(mp, 0x14);
1009 p->broadcast_frames_received += mib_read(mp, 0x18);
1010 p->multicast_frames_received += mib_read(mp, 0x1c);
1011 p->frames_64_octets += mib_read(mp, 0x20);
1012 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1013 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1014 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1015 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1016 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1017 p->good_octets_sent += mib_read(mp, 0x38);
1018 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1019 p->good_frames_sent += mib_read(mp, 0x40);
1020 p->excessive_collision += mib_read(mp, 0x44);
1021 p->multicast_frames_sent += mib_read(mp, 0x48);
1022 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1023 p->unrec_mac_control_received += mib_read(mp, 0x50);
1024 p->fc_sent += mib_read(mp, 0x54);
1025 p->good_fc_received += mib_read(mp, 0x58);
1026 p->bad_fc_received += mib_read(mp, 0x5c);
1027 p->undersize_received += mib_read(mp, 0x60);
1028 p->fragments_received += mib_read(mp, 0x64);
1029 p->oversize_received += mib_read(mp, 0x68);
1030 p->jabber_received += mib_read(mp, 0x6c);
1031 p->mac_receive_error += mib_read(mp, 0x70);
1032 p->bad_crc_event += mib_read(mp, 0x74);
1033 p->collision += mib_read(mp, 0x78);
1034 p->late_collision += mib_read(mp, 0x7c);
1035}
1036
1037
1038/* ethtool ******************************************************************/
1039struct mv643xx_eth_stats {
1040 char stat_string[ETH_GSTRING_LEN];
1041 int sizeof_stat;
1042 int netdev_off;
1043 int mp_off;
1044};
1045
1046#define SSTAT(m) \
1047 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1048 offsetof(struct net_device, stats.m), -1 }
1049
1050#define MIBSTAT(m) \
1051 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1052 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1053
1054static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1055 SSTAT(rx_packets),
1056 SSTAT(tx_packets),
1057 SSTAT(rx_bytes),
1058 SSTAT(tx_bytes),
1059 SSTAT(rx_errors),
1060 SSTAT(tx_errors),
1061 SSTAT(rx_dropped),
1062 SSTAT(tx_dropped),
1063 MIBSTAT(good_octets_received),
1064 MIBSTAT(bad_octets_received),
1065 MIBSTAT(internal_mac_transmit_err),
1066 MIBSTAT(good_frames_received),
1067 MIBSTAT(bad_frames_received),
1068 MIBSTAT(broadcast_frames_received),
1069 MIBSTAT(multicast_frames_received),
1070 MIBSTAT(frames_64_octets),
1071 MIBSTAT(frames_65_to_127_octets),
1072 MIBSTAT(frames_128_to_255_octets),
1073 MIBSTAT(frames_256_to_511_octets),
1074 MIBSTAT(frames_512_to_1023_octets),
1075 MIBSTAT(frames_1024_to_max_octets),
1076 MIBSTAT(good_octets_sent),
1077 MIBSTAT(good_frames_sent),
1078 MIBSTAT(excessive_collision),
1079 MIBSTAT(multicast_frames_sent),
1080 MIBSTAT(broadcast_frames_sent),
1081 MIBSTAT(unrec_mac_control_received),
1082 MIBSTAT(fc_sent),
1083 MIBSTAT(good_fc_received),
1084 MIBSTAT(bad_fc_received),
1085 MIBSTAT(undersize_received),
1086 MIBSTAT(fragments_received),
1087 MIBSTAT(oversize_received),
1088 MIBSTAT(jabber_received),
1089 MIBSTAT(mac_receive_error),
1090 MIBSTAT(bad_crc_event),
1091 MIBSTAT(collision),
1092 MIBSTAT(late_collision),
1093};
1526 1094
1527 eth_port_reset(mp); 1095static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1096{
1097 struct mv643xx_eth_private *mp = netdev_priv(dev);
1098 int err;
1528 1099
1529 mv643xx_eth_free_tx_rings(dev); 1100 spin_lock_irq(&mp->lock);
1530 mv643xx_eth_free_rx_rings(dev); 1101 err = mii_ethtool_gset(&mp->mii, cmd);
1102 spin_unlock_irq(&mp->lock);
1531 1103
1532 free_irq(dev->irq, dev); 1104 /*
1105 * The MAC does not support 1000baseT_Half.
1106 */
1107 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1108 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1109
1110 return err;
1111}
1112
1113static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1114{
1115 cmd->supported = SUPPORTED_MII;
1116 cmd->advertising = ADVERTISED_MII;
1117 cmd->speed = SPEED_1000;
1118 cmd->duplex = DUPLEX_FULL;
1119 cmd->port = PORT_MII;
1120 cmd->phy_address = 0;
1121 cmd->transceiver = XCVR_INTERNAL;
1122 cmd->autoneg = AUTONEG_DISABLE;
1123 cmd->maxtxpkt = 1;
1124 cmd->maxrxpkt = 1;
1533 1125
1534 return 0; 1126 return 0;
1535} 1127}
1536 1128
1537#ifdef MV643XX_NAPI 1129static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1538/*
1539 * mv643xx_poll
1540 *
1541 * This function is used in case of NAPI
1542 */
1543static int mv643xx_poll(struct napi_struct *napi, int budget)
1544{ 1130{
1545 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); 1131 struct mv643xx_eth_private *mp = netdev_priv(dev);
1546 struct net_device *dev = mp->dev; 1132 int err;
1547 unsigned int port_num = mp->port_num;
1548 int work_done;
1549 1133
1550#ifdef MV643XX_TX_FAST_REFILL 1134 /*
1551 if (++mp->tx_clean_threshold > 5) { 1135 * The MAC does not support 1000baseT_Half.
1552 mv643xx_eth_free_completed_tx_descs(dev); 1136 */
1553 mp->tx_clean_threshold = 0; 1137 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1554 }
1555#endif
1556 1138
1557 work_done = 0; 1139 spin_lock_irq(&mp->lock);
1558 if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) 1140 err = mii_ethtool_sset(&mp->mii, cmd);
1559 != (u32) mp->rx_used_desc_q) 1141 spin_unlock_irq(&mp->lock);
1560 work_done = mv643xx_eth_receive_queue(dev, budget);
1561 1142
1562 if (work_done < budget) { 1143 return err;
1563 netif_rx_complete(dev, napi); 1144}
1564 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1565 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1566 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1567 }
1568 1145
1569 return work_done; 1146static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1147{
1148 return -EINVAL;
1570} 1149}
1571#endif
1572 1150
1573/** 1151static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1574 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments 1152 struct ethtool_drvinfo *drvinfo)
1575 * 1153{
1576 * Hardware can't handle unaligned fragments smaller than 9 bytes. 1154 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1577 * This helper function detects that case. 1155 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1578 */ 1156 strncpy(drvinfo->fw_version, "N/A", 32);
1157 strncpy(drvinfo->bus_info, "platform", 32);
1158 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1159}
1579 1160
1580static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 1161static int mv643xx_eth_nway_reset(struct net_device *dev)
1581{ 1162{
1582 unsigned int frag; 1163 struct mv643xx_eth_private *mp = netdev_priv(dev);
1583 skb_frag_t *fragp;
1584 1164
1585 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1165 return mii_nway_restart(&mp->mii);
1586 fragp = &skb_shinfo(skb)->frags[frag];
1587 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1588 return 1;
1589 }
1590 return 0;
1591} 1166}
1592 1167
1593/** 1168static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1594 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1595 */
1596static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1597{ 1169{
1598 int tx_desc_curr; 1170 return -EINVAL;
1599 1171}
1600 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1601 1172
1602 tx_desc_curr = mp->tx_curr_desc_q; 1173static u32 mv643xx_eth_get_link(struct net_device *dev)
1603 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; 1174{
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1604 1176
1605 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); 1177 return mii_link_ok(&mp->mii);
1178}
1606 1179
1607 return tx_desc_curr; 1180static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1181{
1182 return 1;
1608} 1183}
1609 1184
1610/** 1185static void mv643xx_eth_get_strings(struct net_device *dev,
1611 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. 1186 uint32_t stringset, uint8_t *data)
1612 *
1613 * Ensure the data for each fragment to be transmitted is mapped properly,
1614 * then fill in descriptors in the tx hw queue.
1615 */
1616static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1617 struct sk_buff *skb)
1618{ 1187{
1619 int frag; 1188 int i;
1620 int tx_index;
1621 struct eth_tx_desc *desc;
1622 1189
1623 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 1190 if (stringset == ETH_SS_STATS) {
1624 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 1191 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1625 1192 memcpy(data + i * ETH_GSTRING_LEN,
1626 tx_index = eth_alloc_tx_desc_index(mp); 1193 mv643xx_eth_stats[i].stat_string,
1627 desc = &mp->p_tx_desc_area[tx_index]; 1194 ETH_GSTRING_LEN);
1628 1195 }
1629 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1630 /* Last Frag enables interrupt and frees the skb */
1631 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1632 desc->cmd_sts |= ETH_ZERO_PADDING |
1633 ETH_TX_LAST_DESC |
1634 ETH_TX_ENABLE_INTERRUPT;
1635 mp->tx_skb[tx_index] = skb;
1636 } else
1637 mp->tx_skb[tx_index] = NULL;
1638
1639 desc = &mp->p_tx_desc_area[tx_index];
1640 desc->l4i_chk = 0;
1641 desc->byte_cnt = this_frag->size;
1642 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1643 this_frag->page_offset,
1644 this_frag->size,
1645 DMA_TO_DEVICE);
1646 } 1196 }
1647} 1197}
1648 1198
1649static inline __be16 sum16_as_be(__sum16 sum) 1199static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1200 struct ethtool_stats *stats,
1201 uint64_t *data)
1650{ 1202{
1651 return (__force __be16)sum; 1203 struct mv643xx_eth_private *mp = dev->priv;
1652} 1204 int i;
1653 1205
1654/** 1206 mib_counters_update(mp);
1655 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1656 *
1657 * Ensure the data for an skb to be transmitted is mapped properly,
1658 * then fill in descriptors in the tx hw queue and start the hardware.
1659 */
1660static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1661 struct sk_buff *skb)
1662{
1663 int tx_index;
1664 struct eth_tx_desc *desc;
1665 u32 cmd_sts;
1666 int length;
1667 int nr_frags = skb_shinfo(skb)->nr_frags;
1668 1207
1669 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; 1208 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1209 const struct mv643xx_eth_stats *stat;
1210 void *p;
1670 1211
1671 tx_index = eth_alloc_tx_desc_index(mp); 1212 stat = mv643xx_eth_stats + i;
1672 desc = &mp->p_tx_desc_area[tx_index];
1673 1213
1674 if (nr_frags) { 1214 if (stat->netdev_off >= 0)
1675 eth_tx_fill_frag_descs(mp, skb); 1215 p = ((void *)mp->dev) + stat->netdev_off;
1216 else
1217 p = ((void *)mp) + stat->mp_off;
1676 1218
1677 length = skb_headlen(skb); 1219 data[i] = (stat->sizeof_stat == 8) ?
1678 mp->tx_skb[tx_index] = NULL; 1220 *(uint64_t *)p : *(uint32_t *)p;
1679 } else {
1680 cmd_sts |= ETH_ZERO_PADDING |
1681 ETH_TX_LAST_DESC |
1682 ETH_TX_ENABLE_INTERRUPT;
1683 length = skb->len;
1684 mp->tx_skb[tx_index] = skb;
1685 } 1221 }
1222}
1686 1223
1687 desc->byte_cnt = length; 1224static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1688 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1225{
1226 if (sset == ETH_SS_STATS)
1227 return ARRAY_SIZE(mv643xx_eth_stats);
1689 1228
1690 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1229 return -EOPNOTSUPP;
1691 BUG_ON(skb->protocol != htons(ETH_P_IP)); 1230}
1692 1231
1693 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | 1232static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1694 ETH_GEN_IP_V_4_CHECKSUM | 1233 .get_settings = mv643xx_eth_get_settings,
1695 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; 1234 .set_settings = mv643xx_eth_set_settings,
1235 .get_drvinfo = mv643xx_eth_get_drvinfo,
1236 .nway_reset = mv643xx_eth_nway_reset,
1237 .get_link = mv643xx_eth_get_link,
1238 .set_sg = ethtool_op_set_sg,
1239 .get_strings = mv643xx_eth_get_strings,
1240 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1241 .get_sset_count = mv643xx_eth_get_sset_count,
1242};
1696 1243
1697 switch (ip_hdr(skb)->protocol) { 1244static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1698 case IPPROTO_UDP: 1245 .get_settings = mv643xx_eth_get_settings_phyless,
1699 cmd_sts |= ETH_UDP_FRAME; 1246 .set_settings = mv643xx_eth_set_settings_phyless,
1700 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); 1247 .get_drvinfo = mv643xx_eth_get_drvinfo,
1701 break; 1248 .nway_reset = mv643xx_eth_nway_reset_phyless,
1702 case IPPROTO_TCP: 1249 .get_link = mv643xx_eth_get_link_phyless,
1703 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); 1250 .set_sg = ethtool_op_set_sg,
1704 break; 1251 .get_strings = mv643xx_eth_get_strings,
1705 default: 1252 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1706 BUG(); 1253 .get_sset_count = mv643xx_eth_get_sset_count,
1707 } 1254};
1708 } else {
1709 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1710 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1711 desc->l4i_chk = 0;
1712 }
1713 1255
1714 /* ensure all other descriptors are written before first cmd_sts */
1715 wmb();
1716 desc->cmd_sts = cmd_sts;
1717 1256
1718 /* ensure all descriptors are written before poking hardware */ 1257/* address handling *********************************************************/
1719 wmb(); 1258static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1720 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); 1259{
1260 unsigned int mac_h;
1261 unsigned int mac_l;
1262
1263 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1264 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1721 1265
1722 mp->tx_desc_count += nr_frags + 1; 1266 addr[0] = (mac_h >> 24) & 0xff;
1267 addr[1] = (mac_h >> 16) & 0xff;
1268 addr[2] = (mac_h >> 8) & 0xff;
1269 addr[3] = mac_h & 0xff;
1270 addr[4] = (mac_l >> 8) & 0xff;
1271 addr[5] = mac_l & 0xff;
1723} 1272}
1724 1273
1725/** 1274static void init_mac_tables(struct mv643xx_eth_private *mp)
1726 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1727 *
1728 */
1729static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1730{ 1275{
1731 struct mv643xx_private *mp = netdev_priv(dev); 1276 int i;
1732 struct net_device_stats *stats = &dev->stats;
1733 unsigned long flags;
1734
1735 BUG_ON(netif_queue_stopped(dev));
1736 1277
1737 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 1278 for (i = 0; i < 0x100; i += 4) {
1738 stats->tx_dropped++; 1279 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1739 printk(KERN_DEBUG "%s: failed to linearize tiny " 1280 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1740 "unaligned fragment\n", dev->name);
1741 return NETDEV_TX_BUSY;
1742 } 1281 }
1743 1282
1744 spin_lock_irqsave(&mp->lock, flags); 1283 for (i = 0; i < 0x10; i += 4)
1284 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1285}
1745 1286
1746 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { 1287static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1747 printk(KERN_ERR "%s: transmit with queue full\n", dev->name); 1288 int table, unsigned char entry)
1748 netif_stop_queue(dev); 1289{
1749 spin_unlock_irqrestore(&mp->lock, flags); 1290 unsigned int table_reg;
1750 return NETDEV_TX_BUSY;
1751 }
1752 1291
1753 eth_tx_submit_descs_for_skb(mp, skb); 1292 /* Set "accepts frame bit" at specified table entry */
1754 stats->tx_bytes += skb->len; 1293 table_reg = rdl(mp, table + (entry & 0xfc));
1755 stats->tx_packets++; 1294 table_reg |= 0x01 << (8 * (entry & 3));
1756 dev->trans_start = jiffies; 1295 wrl(mp, table + (entry & 0xfc), table_reg);
1296}
1757 1297
1758 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) 1298static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1759 netif_stop_queue(dev); 1299{
1300 unsigned int mac_h;
1301 unsigned int mac_l;
1302 int table;
1760 1303
1761 spin_unlock_irqrestore(&mp->lock, flags); 1304 mac_l = (addr[4] << 8) | addr[5];
1305 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1762 1306
1763 return NETDEV_TX_OK; 1307 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1308 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1309
1310 table = UNICAST_TABLE(mp->port_num);
1311 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1764} 1312}
1765 1313
1766#ifdef CONFIG_NET_POLL_CONTROLLER 1314static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1767static void mv643xx_netpoll(struct net_device *netdev)
1768{ 1315{
1769 struct mv643xx_private *mp = netdev_priv(netdev); 1316 struct mv643xx_eth_private *mp = netdev_priv(dev);
1770 int port_num = mp->port_num;
1771 1317
1772 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1318 /* +2 is for the offset of the HW addr type */
1773 /* wait for previous write to complete */ 1319 memcpy(dev->dev_addr, addr + 2, 6);
1774 rdl(mp, INTERRUPT_MASK_REG(port_num));
1775 1320
1776 mv643xx_eth_int_handler(netdev->irq, netdev); 1321 init_mac_tables(mp);
1322 uc_addr_set(mp, dev->dev_addr);
1777 1323
1778 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1324 return 0;
1779} 1325}
1780#endif
1781 1326
1782static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, 1327static int addr_crc(unsigned char *addr)
1783 int speed, int duplex,
1784 struct ethtool_cmd *cmd)
1785{ 1328{
1786 struct mv643xx_private *mp = netdev_priv(dev); 1329 int crc = 0;
1330 int i;
1787 1331
1788 memset(cmd, 0, sizeof(*cmd)); 1332 for (i = 0; i < 6; i++) {
1333 int j;
1789 1334
1790 cmd->port = PORT_MII; 1335 crc = (crc ^ addr[i]) << 8;
1791 cmd->transceiver = XCVR_INTERNAL; 1336 for (j = 7; j >= 0; j--) {
1792 cmd->phy_address = phy_address; 1337 if (crc & (0x100 << j))
1793 1338 crc ^= 0x107 << j;
1794 if (speed == 0) { 1339 }
1795 cmd->autoneg = AUTONEG_ENABLE;
1796 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1797 cmd->speed = SPEED_100;
1798 cmd->advertising = ADVERTISED_10baseT_Half |
1799 ADVERTISED_10baseT_Full |
1800 ADVERTISED_100baseT_Half |
1801 ADVERTISED_100baseT_Full;
1802 if (mp->mii.supports_gmii)
1803 cmd->advertising |= ADVERTISED_1000baseT_Full;
1804 } else {
1805 cmd->autoneg = AUTONEG_DISABLE;
1806 cmd->speed = speed;
1807 cmd->duplex = duplex;
1808 } 1340 }
1341
1342 return crc;
1809} 1343}
1810 1344
1811/*/ 1345static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1812 * mv643xx_eth_probe
1813 *
1814 * First function called after registering the network device.
1815 * It's purpose is to initialize the device as an ethernet device,
1816 * fill the ethernet device structure with pointers * to functions,
1817 * and set the MAC address of the interface
1818 *
1819 * Input : struct device *
1820 * Output : -ENOMEM if failed , 0 if success
1821 */
1822static int mv643xx_eth_probe(struct platform_device *pdev)
1823{ 1346{
1824 struct mv643xx_eth_platform_data *pd; 1347 struct mv643xx_eth_private *mp = netdev_priv(dev);
1825 int port_num; 1348 u32 port_config;
1826 struct mv643xx_private *mp; 1349 struct dev_addr_list *addr;
1827 struct net_device *dev; 1350 int i;
1828 u8 *p;
1829 struct resource *res;
1830 int err;
1831 struct ethtool_cmd cmd;
1832 int duplex = DUPLEX_HALF;
1833 int speed = 0; /* default to auto-negotiation */
1834 DECLARE_MAC_BUF(mac);
1835 1351
1836 pd = pdev->dev.platform_data; 1352 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1837 if (pd == NULL) { 1353 if (dev->flags & IFF_PROMISC)
1838 printk(KERN_ERR "No mv643xx_eth_platform_data\n"); 1354 port_config |= UNICAST_PROMISCUOUS_MODE;
1839 return -ENODEV; 1355 else
1356 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1357 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1358
1359 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1360 int port_num = mp->port_num;
1361 u32 accept = 0x01010101;
1362
1363 for (i = 0; i < 0x100; i += 4) {
1364 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1365 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1366 }
1367 return;
1840 } 1368 }
1841 1369
1842 if (pd->shared == NULL) { 1370 for (i = 0; i < 0x100; i += 4) {
1843 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); 1371 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1844 return -ENODEV; 1372 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1845 } 1373 }
1846 1374
1847 dev = alloc_etherdev(sizeof(struct mv643xx_private)); 1375 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1848 if (!dev) 1376 u8 *a = addr->da_addr;
1849 return -ENOMEM; 1377 int table;
1850 1378
1851 platform_set_drvdata(pdev, dev); 1379 if (addr->da_addrlen != 6)
1380 continue;
1852 1381
1853 mp = netdev_priv(dev); 1382 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1854 mp->dev = dev; 1383 table = SPECIAL_MCAST_TABLE(mp->port_num);
1855#ifdef MV643XX_NAPI 1384 set_filter_table_entry(mp, table, a[5]);
1856 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); 1385 } else {
1857#endif 1386 int crc = addr_crc(a);
1858 1387
1859 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1388 table = OTHER_MCAST_TABLE(mp->port_num);
1860 BUG_ON(!res); 1389 set_filter_table_entry(mp, table, crc);
1861 dev->irq = res->start; 1390 }
1391 }
1392}
1862 1393
1863 dev->open = mv643xx_eth_open;
1864 dev->stop = mv643xx_eth_stop;
1865 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1866 dev->set_mac_address = mv643xx_eth_set_mac_address;
1867 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1868 1394
1869 /* No need to Tx Timeout */ 1395/* rx/tx queue initialisation ***********************************************/
1870 dev->tx_timeout = mv643xx_eth_tx_timeout; 1396static int rxq_init(struct mv643xx_eth_private *mp, int index)
1397{
1398 struct rx_queue *rxq = mp->rxq + index;
1399 struct rx_desc *rx_desc;
1400 int size;
1401 int i;
1871 1402
1872#ifdef CONFIG_NET_POLL_CONTROLLER 1403 rxq->index = index;
1873 dev->poll_controller = mv643xx_netpoll;
1874#endif
1875 1404
1876 dev->watchdog_timeo = 2 * HZ; 1405 rxq->rx_ring_size = mp->default_rx_ring_size;
1877 dev->base_addr = 0;
1878 dev->change_mtu = mv643xx_eth_change_mtu;
1879 dev->do_ioctl = mv643xx_eth_do_ioctl;
1880 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1881 1406
1882#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1407 rxq->rx_desc_count = 0;
1883#ifdef MAX_SKB_FRAGS 1408 rxq->rx_curr_desc = 0;
1884 /* 1409 rxq->rx_used_desc = 0;
1885 * Zero copy can only work if we use Discovery II memory. Else, we will
1886 * have to map the buffers to ISA memory which is only 16 MB
1887 */
1888 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1889#endif
1890#endif
1891 1410
1892 /* Configure the timeout task */ 1411 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1893 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1894 1412
1895 spin_lock_init(&mp->lock); 1413 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1414 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1415 mp->rx_desc_sram_size);
1416 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1417 } else {
1418 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1419 &rxq->rx_desc_dma,
1420 GFP_KERNEL);
1421 }
1896 1422
1897 mp->shared = platform_get_drvdata(pd->shared); 1423 if (rxq->rx_desc_area == NULL) {
1898 port_num = mp->port_num = pd->port_number; 1424 dev_printk(KERN_ERR, &mp->dev->dev,
1425 "can't allocate rx ring (%d bytes)\n", size);
1426 goto out;
1427 }
1428 memset(rxq->rx_desc_area, 0, size);
1899 1429
1900 if (mp->shared->win_protect) 1430 rxq->rx_desc_area_size = size;
1901 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); 1431 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1432 GFP_KERNEL);
1433 if (rxq->rx_skb == NULL) {
1434 dev_printk(KERN_ERR, &mp->dev->dev,
1435 "can't allocate rx skb ring\n");
1436 goto out_free;
1437 }
1902 1438
1903 mp->shared_smi = mp->shared; 1439 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1904 if (pd->shared_smi != NULL) 1440 for (i = 0; i < rxq->rx_ring_size; i++) {
1905 mp->shared_smi = platform_get_drvdata(pd->shared_smi); 1441 int nexti = (i + 1) % rxq->rx_ring_size;
1442 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1443 nexti * sizeof(struct rx_desc);
1444 }
1906 1445
1907 /* set default config values */ 1446 init_timer(&rxq->rx_oom);
1908 eth_port_uc_addr_get(mp, dev->dev_addr); 1447 rxq->rx_oom.data = (unsigned long)rxq;
1909 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; 1448 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1910 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1911 1449
1912 if (is_valid_ether_addr(pd->mac_addr)) 1450 return 0;
1913 memcpy(dev->dev_addr, pd->mac_addr, 6);
1914 1451
1915 if (pd->phy_addr || pd->force_phy_addr)
1916 ethernet_phy_set(mp, pd->phy_addr);
1917 1452
1918 if (pd->rx_queue_size) 1453out_free:
1919 mp->rx_ring_size = pd->rx_queue_size; 1454 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1455 iounmap(rxq->rx_desc_area);
1456 else
1457 dma_free_coherent(NULL, size,
1458 rxq->rx_desc_area,
1459 rxq->rx_desc_dma);
1920 1460
1921 if (pd->tx_queue_size) 1461out:
1922 mp->tx_ring_size = pd->tx_queue_size; 1462 return -ENOMEM;
1463}
1923 1464
1924 if (pd->tx_sram_size) { 1465static void rxq_deinit(struct rx_queue *rxq)
1925 mp->tx_sram_size = pd->tx_sram_size; 1466{
1926 mp->tx_sram_addr = pd->tx_sram_addr; 1467 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1927 } 1468 int i;
1928 1469
1929 if (pd->rx_sram_size) { 1470 rxq_disable(rxq);
1930 mp->rx_sram_size = pd->rx_sram_size;
1931 mp->rx_sram_addr = pd->rx_sram_addr;
1932 }
1933 1471
1934 duplex = pd->duplex; 1472 del_timer_sync(&rxq->rx_oom);
1935 speed = pd->speed;
1936 1473
1937 /* Hook up MII support for ethtool */ 1474 for (i = 0; i < rxq->rx_ring_size; i++) {
1938 mp->mii.dev = dev; 1475 if (rxq->rx_skb[i]) {
1939 mp->mii.mdio_read = mv643xx_mdio_read; 1476 dev_kfree_skb(rxq->rx_skb[i]);
1940 mp->mii.mdio_write = mv643xx_mdio_write; 1477 rxq->rx_desc_count--;
1941 mp->mii.phy_id = ethernet_phy_get(mp); 1478 }
1942 mp->mii.phy_id_mask = 0x3f; 1479 }
1943 mp->mii.reg_num_mask = 0x1f;
1944 1480
1945 err = ethernet_phy_detect(mp); 1481 if (rxq->rx_desc_count) {
1946 if (err) { 1482 dev_printk(KERN_ERR, &mp->dev->dev,
1947 pr_debug("%s: No PHY detected at addr %d\n", 1483 "error freeing rx ring -- %d skbs stuck\n",
1948 dev->name, ethernet_phy_get(mp)); 1484 rxq->rx_desc_count);
1949 goto out;
1950 } 1485 }
1951 1486
1952 ethernet_phy_reset(mp); 1487 if (rxq->index == mp->rxq_primary &&
1953 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); 1488 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1954 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); 1489 iounmap(rxq->rx_desc_area);
1955 mv643xx_eth_update_pscr(dev, &cmd); 1490 else
1956 mv643xx_set_settings(dev, &cmd); 1491 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1492 rxq->rx_desc_area, rxq->rx_desc_dma);
1957 1493
1958 SET_NETDEV_DEV(dev, &pdev->dev); 1494 kfree(rxq->rx_skb);
1959 err = register_netdev(dev); 1495}
1960 if (err)
1961 goto out;
1962 1496
1963 p = dev->dev_addr; 1497static int txq_init(struct mv643xx_eth_private *mp, int index)
1964 printk(KERN_NOTICE 1498{
1965 "%s: port %d with MAC address %s\n", 1499 struct tx_queue *txq = mp->txq + index;
1966 dev->name, port_num, print_mac(mac, p)); 1500 struct tx_desc *tx_desc;
1501 int size;
1502 int i;
1967 1503
1968 if (dev->features & NETIF_F_SG) 1504 txq->index = index;
1969 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1970 1505
1971 if (dev->features & NETIF_F_IP_CSUM) 1506 txq->tx_ring_size = mp->default_tx_ring_size;
1972 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1973 dev->name);
1974 1507
1975#ifdef MV643XX_CHECKSUM_OFFLOAD_TX 1508 txq->tx_desc_count = 0;
1976 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); 1509 txq->tx_curr_desc = 0;
1977#endif 1510 txq->tx_used_desc = 0;
1978 1511
1979#ifdef MV643XX_COAL 1512 size = txq->tx_ring_size * sizeof(struct tx_desc);
1980 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1981 dev->name);
1982#endif
1983 1513
1984#ifdef MV643XX_NAPI 1514 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1985 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); 1515 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1986#endif 1516 mp->tx_desc_sram_size);
1517 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1518 } else {
1519 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1520 &txq->tx_desc_dma,
1521 GFP_KERNEL);
1522 }
1523
1524 if (txq->tx_desc_area == NULL) {
1525 dev_printk(KERN_ERR, &mp->dev->dev,
1526 "can't allocate tx ring (%d bytes)\n", size);
1527 goto out;
1528 }
1529 memset(txq->tx_desc_area, 0, size);
1987 1530
1988 if (mp->tx_sram_size > 0) 1531 txq->tx_desc_area_size = size;
1989 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); 1532 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1533 GFP_KERNEL);
1534 if (txq->tx_skb == NULL) {
1535 dev_printk(KERN_ERR, &mp->dev->dev,
1536 "can't allocate tx skb ring\n");
1537 goto out_free;
1538 }
1539
1540 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1541 for (i = 0; i < txq->tx_ring_size; i++) {
1542 int nexti = (i + 1) % txq->tx_ring_size;
1543 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1544 nexti * sizeof(struct tx_desc);
1545 }
1990 1546
1991 return 0; 1547 return 0;
1992 1548
1993out:
1994 free_netdev(dev);
1995 1549
1996 return err; 1550out_free:
1551 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1552 iounmap(txq->tx_desc_area);
1553 else
1554 dma_free_coherent(NULL, size,
1555 txq->tx_desc_area,
1556 txq->tx_desc_dma);
1557
1558out:
1559 return -ENOMEM;
1997} 1560}
1998 1561
1999static int mv643xx_eth_remove(struct platform_device *pdev) 1562static void txq_reclaim(struct tx_queue *txq, int force)
2000{ 1563{
2001 struct net_device *dev = platform_get_drvdata(pdev); 1564 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1565 unsigned long flags;
2002 1566
2003 unregister_netdev(dev); 1567 spin_lock_irqsave(&mp->lock, flags);
2004 flush_scheduled_work(); 1568 while (txq->tx_desc_count > 0) {
1569 int tx_index;
1570 struct tx_desc *desc;
1571 u32 cmd_sts;
1572 struct sk_buff *skb;
1573 dma_addr_t addr;
1574 int count;
1575
1576 tx_index = txq->tx_used_desc;
1577 desc = &txq->tx_desc_area[tx_index];
1578 cmd_sts = desc->cmd_sts;
2005 1579
2006 free_netdev(dev); 1580 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
2007 platform_set_drvdata(pdev, NULL); 1581 break;
2008 return 0;
2009}
2010 1582
2011static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, 1583 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
2012 struct mbus_dram_target_info *dram) 1584 txq->tx_desc_count--;
2013{
2014 void __iomem *base = msp->eth_base;
2015 u32 win_enable;
2016 u32 win_protect;
2017 int i;
2018 1585
2019 for (i = 0; i < 6; i++) { 1586 addr = desc->buf_ptr;
2020 writel(0, base + WINDOW_BASE(i)); 1587 count = desc->byte_cnt;
2021 writel(0, base + WINDOW_SIZE(i)); 1588 skb = txq->tx_skb[tx_index];
2022 if (i < 4) 1589 txq->tx_skb[tx_index] = NULL;
2023 writel(0, base + WINDOW_REMAP_HIGH(i));
2024 }
2025 1590
2026 win_enable = 0x3f; 1591 if (cmd_sts & ERROR_SUMMARY) {
2027 win_protect = 0; 1592 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1593 mp->dev->stats.tx_errors++;
1594 }
2028 1595
2029 for (i = 0; i < dram->num_cs; i++) { 1596 /*
2030 struct mbus_dram_window *cs = dram->cs + i; 1597 * Drop mp->lock while we free the skb.
1598 */
1599 spin_unlock_irqrestore(&mp->lock, flags);
2031 1600
2032 writel((cs->base & 0xffff0000) | 1601 if (cmd_sts & TX_FIRST_DESC)
2033 (cs->mbus_attr << 8) | 1602 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
2034 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 1603 else
2035 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 1604 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
2036 1605
2037 win_enable &= ~(1 << i); 1606 if (skb)
2038 win_protect |= 3 << (2 * i); 1607 dev_kfree_skb_irq(skb);
2039 }
2040 1608
2041 writel(win_enable, base + WINDOW_BAR_ENABLE); 1609 spin_lock_irqsave(&mp->lock, flags);
2042 msp->win_protect = win_protect; 1610 }
1611 spin_unlock_irqrestore(&mp->lock, flags);
2043} 1612}
2044 1613
2045static int mv643xx_eth_shared_probe(struct platform_device *pdev) 1614static void txq_deinit(struct tx_queue *txq)
2046{ 1615{
2047 static int mv643xx_version_printed = 0; 1616 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2048 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2049 struct mv643xx_shared_private *msp;
2050 struct resource *res;
2051 int ret;
2052 1617
2053 if (!mv643xx_version_printed++) 1618 txq_disable(txq);
2054 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); 1619 txq_reclaim(txq, 1);
2055 1620
2056 ret = -EINVAL; 1621 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2057 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2058 if (res == NULL)
2059 goto out;
2060 1622
2061 ret = -ENOMEM; 1623 if (txq->index == mp->txq_primary &&
2062 msp = kmalloc(sizeof(*msp), GFP_KERNEL); 1624 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2063 if (msp == NULL) 1625 iounmap(txq->tx_desc_area);
2064 goto out; 1626 else
2065 memset(msp, 0, sizeof(*msp)); 1627 dma_free_coherent(NULL, txq->tx_desc_area_size,
1628 txq->tx_desc_area, txq->tx_desc_dma);
2066 1629
2067 msp->eth_base = ioremap(res->start, res->end - res->start + 1); 1630 kfree(txq->tx_skb);
2068 if (msp->eth_base == NULL) 1631}
2069 goto out_free;
2070 1632
2071 spin_lock_init(&msp->phy_lock);
2072 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2073 1633
2074 platform_set_drvdata(pdev, msp); 1634/* netdev ops and related ***************************************************/
1635static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1636{
1637 u32 pscr_o;
1638 u32 pscr_n;
2075 1639
2076 /* 1640 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2077 * (Re-)program MBUS remapping windows if we are asked to.
2078 */
2079 if (pd != NULL && pd->dram != NULL)
2080 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2081 1641
2082 return 0; 1642 /* clear speed, duplex and rx buffer size fields */
1643 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1644 SET_GMII_SPEED_TO_1000 |
1645 SET_FULL_DUPLEX_MODE |
1646 MAX_RX_PACKET_MASK);
2083 1647
2084out_free: 1648 if (speed == SPEED_1000) {
2085 kfree(msp); 1649 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
2086out: 1650 } else {
2087 return ret; 1651 if (speed == SPEED_100)
2088} 1652 pscr_n |= SET_MII_SPEED_TO_100;
1653 pscr_n |= MAX_RX_PACKET_1522BYTE;
1654 }
2089 1655
2090static int mv643xx_eth_shared_remove(struct platform_device *pdev) 1656 if (duplex == DUPLEX_FULL)
2091{ 1657 pscr_n |= SET_FULL_DUPLEX_MODE;
2092 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2093 1658
2094 iounmap(msp->eth_base); 1659 if (pscr_n != pscr_o) {
2095 kfree(msp); 1660 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1661 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1662 else {
1663 int i;
2096 1664
2097 return 0; 1665 for (i = 0; i < 8; i++)
1666 if (mp->txq_mask & (1 << i))
1667 txq_disable(mp->txq + i);
1668
1669 pscr_o &= ~SERIAL_PORT_ENABLE;
1670 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1671 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1672 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1673
1674 for (i = 0; i < 8; i++)
1675 if (mp->txq_mask & (1 << i))
1676 txq_enable(mp->txq + i);
1677 }
1678 }
2098} 1679}
2099 1680
2100static void mv643xx_eth_shutdown(struct platform_device *pdev) 1681static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2101{ 1682{
2102 struct net_device *dev = platform_get_drvdata(pdev); 1683 struct net_device *dev = (struct net_device *)dev_id;
2103 struct mv643xx_private *mp = netdev_priv(dev); 1684 struct mv643xx_eth_private *mp = netdev_priv(dev);
2104 unsigned int port_num = mp->port_num; 1685 u32 int_cause;
1686 u32 int_cause_ext;
1687 u32 txq_active;
1688
1689 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1690 (INT_TX_END | INT_RX | INT_EXT);
1691 if (int_cause == 0)
1692 return IRQ_NONE;
2105 1693
2106 /* Mask all interrupts on ethernet port */ 1694 int_cause_ext = 0;
2107 wrl(mp, INTERRUPT_MASK_REG(port_num), 0); 1695 if (int_cause & INT_EXT) {
2108 rdl(mp, INTERRUPT_MASK_REG(port_num)); 1696 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1697 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1698 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1699 }
2109 1700
2110 eth_port_reset(mp); 1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
2111} 1702 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1703 int i;
2112 1704
2113static struct platform_driver mv643xx_eth_driver = { 1705 if (mp->phy_addr != -1) {
2114 .probe = mv643xx_eth_probe, 1706 struct ethtool_cmd cmd;
2115 .remove = mv643xx_eth_remove,
2116 .shutdown = mv643xx_eth_shutdown,
2117 .driver = {
2118 .name = MV643XX_ETH_NAME,
2119 .owner = THIS_MODULE,
2120 },
2121};
2122 1707
2123static struct platform_driver mv643xx_eth_shared_driver = { 1708 mii_ethtool_gset(&mp->mii, &cmd);
2124 .probe = mv643xx_eth_shared_probe, 1709 update_pscr(mp, cmd.speed, cmd.duplex);
2125 .remove = mv643xx_eth_shared_remove, 1710 }
2126 .driver = {
2127 .name = MV643XX_ETH_SHARED_NAME,
2128 .owner = THIS_MODULE,
2129 },
2130};
2131 1711
2132/* 1712 for (i = 0; i < 8; i++)
2133 * mv643xx_init_module 1713 if (mp->txq_mask & (1 << i))
2134 * 1714 txq_enable(mp->txq + i);
2135 * Registers the network drivers into the Linux kernel
2136 *
2137 * Input : N/A
2138 *
2139 * Output : N/A
2140 */
2141static int __init mv643xx_init_module(void)
2142{
2143 int rc;
2144 1715
2145 rc = platform_driver_register(&mv643xx_eth_shared_driver); 1716 if (!netif_carrier_ok(dev)) {
2146 if (!rc) { 1717 netif_carrier_on(dev);
2147 rc = platform_driver_register(&mv643xx_eth_driver); 1718 __txq_maybe_wake(mp->txq + mp->txq_primary);
2148 if (rc) 1719 }
2149 platform_driver_unregister(&mv643xx_eth_shared_driver); 1720 } else if (netif_carrier_ok(dev)) {
1721 netif_stop_queue(dev);
1722 netif_carrier_off(dev);
1723 }
2150 } 1724 }
2151 return rc;
2152}
2153 1725
2154/* 1726 /*
2155 * mv643xx_cleanup_module 1727 * RxBuffer or RxError set for any of the 8 queues?
2156 * 1728 */
2157 * Registers the network drivers into the Linux kernel 1729#ifdef MV643XX_ETH_NAPI
2158 * 1730 if (int_cause & INT_RX) {
2159 * Input : N/A 1731 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2160 * 1732 rdl(mp, INT_MASK(mp->port_num));
2161 * Output : N/A
2162 */
2163static void __exit mv643xx_cleanup_module(void)
2164{
2165 platform_driver_unregister(&mv643xx_eth_driver);
2166 platform_driver_unregister(&mv643xx_eth_shared_driver);
2167}
2168 1733
2169module_init(mv643xx_init_module); 1734 netif_rx_schedule(dev, &mp->napi);
2170module_exit(mv643xx_cleanup_module); 1735 }
1736#else
1737 if (int_cause & INT_RX) {
1738 int i;
2171 1739
2172MODULE_LICENSE("GPL"); 1740 for (i = 7; i >= 0; i--)
2173MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" 1741 if (mp->rxq_mask & (1 << i))
2174 " and Dale Farnsworth"); 1742 rxq_process(mp->rxq + i, INT_MAX);
2175MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 1743 }
2176MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 1744#endif
2177MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2178 1745
2179/* 1746 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
2180 * The second part is the low level driver of the gigE ethernet ports.
2181 */
2182 1747
2183/* 1748 /*
2184 * Marvell's Gigabit Ethernet controller low level driver 1749 * TxBuffer or TxError set for any of the 8 queues?
2185 * 1750 */
2186 * DESCRIPTION: 1751 if (int_cause_ext & INT_EXT_TX) {
2187 * This file introduce low level API to Marvell's Gigabit Ethernet 1752 int i;
2188 * controller. This Gigabit Ethernet Controller driver API controls
2189 * 1) Operations (i.e. port init, start, reset etc').
2190 * 2) Data flow (i.e. port send, receive etc').
2191 * Each Gigabit Ethernet port is controlled via
2192 * struct mv643xx_private.
2193 * This struct includes user configuration information as well as
2194 * driver internal data needed for its operations.
2195 *
2196 * Supported Features:
2197 * - This low level driver is OS independent. Allocating memory for
2198 * the descriptor rings and buffers are not within the scope of
2199 * this driver.
2200 * - The user is free from Rx/Tx queue managing.
2201 * - This low level driver introduce functionality API that enable
2202 * the to operate Marvell's Gigabit Ethernet Controller in a
2203 * convenient way.
2204 * - Simple Gigabit Ethernet port operation API.
2205 * - Simple Gigabit Ethernet port data flow API.
2206 * - Data flow and operation API support per queue functionality.
2207 * - Support cached descriptors for better performance.
2208 * - Enable access to all four DRAM banks and internal SRAM memory
2209 * spaces.
2210 * - PHY access and control API.
2211 * - Port control register configuration API.
2212 * - Full control over Unicast and Multicast MAC configurations.
2213 *
2214 * Operation flow:
2215 *
2216 * Initialization phase
2217 * This phase complete the initialization of the the
2218 * mv643xx_private struct.
2219 * User information regarding port configuration has to be set
2220 * prior to calling the port initialization routine.
2221 *
2222 * In this phase any port Tx/Rx activity is halted, MIB counters
2223 * are cleared, PHY address is set according to user parameter and
2224 * access to DRAM and internal SRAM memory spaces.
2225 *
2226 * Driver ring initialization
2227 * Allocating memory for the descriptor rings and buffers is not
2228 * within the scope of this driver. Thus, the user is required to
2229 * allocate memory for the descriptors ring and buffers. Those
2230 * memory parameters are used by the Rx and Tx ring initialization
2231 * routines in order to curve the descriptor linked list in a form
2232 * of a ring.
2233 * Note: Pay special attention to alignment issues when using
2234 * cached descriptors/buffers. In this phase the driver store
2235 * information in the mv643xx_private struct regarding each queue
2236 * ring.
2237 *
2238 * Driver start
2239 * This phase prepares the Ethernet port for Rx and Tx activity.
2240 * It uses the information stored in the mv643xx_private struct to
2241 * initialize the various port registers.
2242 *
2243 * Data flow:
2244 * All packet references to/from the driver are done using
2245 * struct pkt_info.
2246 * This struct is a unified struct used with Rx and Tx operations.
2247 * This way the user is not required to be familiar with neither
2248 * Tx nor Rx descriptors structures.
2249 * The driver's descriptors rings are management by indexes.
2250 * Those indexes controls the ring resources and used to indicate
2251 * a SW resource error:
2252 * 'current'
2253 * This index points to the current available resource for use. For
2254 * example in Rx process this index will point to the descriptor
2255 * that will be passed to the user upon calling the receive
2256 * routine. In Tx process, this index will point to the descriptor
2257 * that will be assigned with the user packet info and transmitted.
2258 * 'used'
2259 * This index points to the descriptor that need to restore its
2260 * resources. For example in Rx process, using the Rx buffer return
2261 * API will attach the buffer returned in packet info to the
2262 * descriptor pointed by 'used'. In Tx process, using the Tx
2263 * descriptor return will merely return the user packet info with
2264 * the command status of the transmitted buffer pointed by the
2265 * 'used' index. Nevertheless, it is essential to use this routine
2266 * to update the 'used' index.
2267 * 'first'
2268 * This index supports Tx Scatter-Gather. It points to the first
2269 * descriptor of a packet assembled of multiple buffers. For
2270 * example when in middle of Such packet we have a Tx resource
2271 * error the 'curr' index get the value of 'first' to indicate
2272 * that the ring returned to its state before trying to transmit
2273 * this packet.
2274 *
2275 * Receive operation:
2276 * The eth_port_receive API set the packet information struct,
2277 * passed by the caller, with received information from the
2278 * 'current' SDMA descriptor.
2279 * It is the user responsibility to return this resource back
2280 * to the Rx descriptor ring to enable the reuse of this source.
2281 * Return Rx resource is done using the eth_rx_return_buff API.
2282 *
2283 * Prior to calling the initialization routine eth_port_init() the user
2284 * must set the following fields under mv643xx_private struct:
2285 * port_num User Ethernet port number.
2286 * port_config User port configuration value.
2287 * port_config_extend User port config extend value.
2288 * port_sdma_config User port SDMA config value.
2289 * port_serial_control User port serial control value.
2290 *
2291 * This driver data flow is done using the struct pkt_info which
2292 * is a unified struct for Rx and Tx operations:
2293 *
2294 * byte_cnt Tx/Rx descriptor buffer byte count.
2295 * l4i_chk CPU provided TCP Checksum. For Tx operation
2296 * only.
2297 * cmd_sts Tx/Rx descriptor command status.
2298 * buf_ptr Tx/Rx descriptor buffer pointer.
2299 * return_info Tx/Rx user resource return information.
2300 */
2301 1753
2302/* Ethernet Port routines */ 1754 for (i = 0; i < 8; i++)
2303static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, 1755 if (mp->txq_mask & (1 << i))
2304 int table, unsigned char entry); 1756 txq_reclaim(mp->txq + i, 0);
1757 }
2305 1758
2306/* 1759 /*
2307 * eth_port_init - Initialize the Ethernet port driver 1760 * Any TxEnd interrupts?
2308 * 1761 */
2309 * DESCRIPTION: 1762 if (int_cause & INT_TX_END) {
2310 * This function prepares the ethernet port to start its activity: 1763 int i;
2311 * 1) Completes the ethernet port driver struct initialization toward port 1764
2312 * start routine. 1765 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
2313 * 2) Resets the device to a quiescent state in case of warm reboot. 1766 for (i = 0; i < 8; i++) {
2314 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. 1767 struct tx_queue *txq = mp->txq + i;
2315 * 4) Clean MAC tables. The reset status of those tables is unknown. 1768 if (txq->tx_desc_count && !((txq_active >> i) & 1))
2316 * 5) Set PHY address. 1769 txq_enable(txq);
2317 * Note: Call this routine prior to eth_port_start routine and after 1770 }
2318 * setting user values in the user fields of Ethernet port control 1771 }
2319 * struct.
2320 *
2321 * INPUT:
2322 * struct mv643xx_private *mp Ethernet port control struct
2323 *
2324 * OUTPUT:
2325 * See description.
2326 *
2327 * RETURN:
2328 * None.
2329 */
2330static void eth_port_init(struct mv643xx_private *mp)
2331{
2332 mp->rx_resource_err = 0;
2333 1772
2334 eth_port_reset(mp); 1773 /*
1774 * Enough space again in the primary TX queue for a full packet?
1775 */
1776 if (int_cause_ext & INT_EXT_TX) {
1777 struct tx_queue *txq = mp->txq + mp->txq_primary;
1778 __txq_maybe_wake(txq);
1779 }
2335 1780
2336 eth_port_init_mac_tables(mp); 1781 return IRQ_HANDLED;
2337} 1782}
2338 1783
2339/* 1784static void phy_reset(struct mv643xx_eth_private *mp)
2340 * eth_port_start - Start the Ethernet port activity.
2341 *
2342 * DESCRIPTION:
2343 * This routine prepares the Ethernet port for Rx and Tx activity:
2344 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2345 * has been initialized a descriptor's ring (using
2346 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2347 * 2. Initialize and enable the Ethernet configuration port by writing to
2348 * the port's configuration and command registers.
2349 * 3. Initialize and enable the SDMA by writing to the SDMA's
2350 * configuration and command registers. After completing these steps,
2351 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2352 *
2353 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2354 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2355 * and ether_init_rx_desc_ring for Rx queues).
2356 *
2357 * INPUT:
2358 * dev - a pointer to the required interface
2359 *
2360 * OUTPUT:
2361 * Ethernet port is ready to receive and transmit.
2362 *
2363 * RETURN:
2364 * None.
2365 */
2366static void eth_port_start(struct net_device *dev)
2367{ 1785{
2368 struct mv643xx_private *mp = netdev_priv(dev); 1786 unsigned int data;
2369 unsigned int port_num = mp->port_num;
2370 int tx_curr_desc, rx_curr_desc;
2371 u32 pscr;
2372 struct ethtool_cmd ethtool_cmd;
2373
2374 /* Assignment of Tx CTRP of given queue */
2375 tx_curr_desc = mp->tx_curr_desc_q;
2376 wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2377 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2378
2379 /* Assignment of Rx CRDP of given queue */
2380 rx_curr_desc = mp->rx_curr_desc_q;
2381 wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2382 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2383 1787
2384 /* Add the assigned Ethernet address to the port's address table */ 1788 smi_reg_read(mp, mp->phy_addr, 0, &data);
2385 eth_port_uc_addr_set(mp, dev->dev_addr); 1789 data |= 0x8000;
1790 smi_reg_write(mp, mp->phy_addr, 0, data);
2386 1791
2387 /* Assign port configuration and command. */ 1792 do {
2388 wrl(mp, PORT_CONFIG_REG(port_num), 1793 udelay(1);
2389 PORT_CONFIG_DEFAULT_VALUE); 1794 smi_reg_read(mp, mp->phy_addr, 0, &data);
2390 1795 } while (data & 0x8000);
2391 wrl(mp, PORT_CONFIG_EXTEND_REG(port_num), 1796}
2392 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2393 1797
2394 pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 1798static void port_start(struct mv643xx_eth_private *mp)
1799{
1800 u32 pscr;
1801 int i;
2395 1802
1803 /*
1804 * Configure basic link parameters.
1805 */
1806 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2396 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); 1807 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2397 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1808 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2398
2399 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1809 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2400 DISABLE_AUTO_NEG_SPEED_GMII | 1810 DISABLE_AUTO_NEG_SPEED_GMII |
2401 DISABLE_AUTO_NEG_FOR_DUPLX | 1811 DISABLE_AUTO_NEG_FOR_DUPLEX |
2402 DO_NOT_FORCE_LINK_FAIL | 1812 DO_NOT_FORCE_LINK_FAIL |
2403 SERIAL_PORT_CONTROL_RESERVED; 1813 SERIAL_PORT_CONTROL_RESERVED;
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1815 pscr |= SERIAL_PORT_ENABLE;
1816 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2404 1817
2405 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1818 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2406 1819
2407 pscr |= SERIAL_PORT_ENABLE; 1820 /*
2408 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); 1821 * Perform PHY reset, if there is a PHY.
1822 */
1823 if (mp->phy_addr != -1) {
1824 struct ethtool_cmd cmd;
2409 1825
2410 /* Assign port SDMA configuration */ 1826 mv643xx_eth_get_settings(mp->dev, &cmd);
2411 wrl(mp, SDMA_CONFIG_REG(port_num), 1827 phy_reset(mp);
2412 PORT_SDMA_CONFIG_DEFAULT_VALUE); 1828 mv643xx_eth_set_settings(mp->dev, &cmd);
1829 }
2413 1830
2414 /* Enable port Rx. */ 1831 /*
2415 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); 1832 * Configure TX path and queues.
1833 */
1834 tx_set_rate(mp, 1000000000, 16777216);
1835 for (i = 0; i < 8; i++) {
1836 struct tx_queue *txq = mp->txq + i;
1837 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1838 u32 addr;
2416 1839
2417 /* Disable port bandwidth limits by clearing MTU register */ 1840 if ((mp->txq_mask & (1 << i)) == 0)
2418 wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0); 1841 continue;
2419 1842
2420 /* save phy settings across reset */ 1843 addr = (u32)txq->tx_desc_dma;
2421 mv643xx_get_settings(dev, &ethtool_cmd); 1844 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
2422 ethernet_phy_reset(mp); 1845 wrl(mp, off, addr);
2423 mv643xx_set_settings(dev, &ethtool_cmd);
2424}
2425 1846
2426/* 1847 txq_set_rate(txq, 1000000000, 16777216);
2427 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers 1848 txq_set_fixed_prio_mode(txq);
2428 */ 1849 }
2429static void eth_port_uc_addr_set(struct mv643xx_private *mp,
2430 unsigned char *p_addr)
2431{
2432 unsigned int port_num = mp->port_num;
2433 unsigned int mac_h;
2434 unsigned int mac_l;
2435 int table;
2436 1850
2437 mac_l = (p_addr[4] << 8) | (p_addr[5]); 1851 /*
2438 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 1852 * Add configured unicast address to address filter table.
2439 (p_addr[3] << 0); 1853 */
1854 uc_addr_set(mp, mp->dev->dev_addr);
2440 1855
2441 wrl(mp, MAC_ADDR_LOW(port_num), mac_l); 1856 /*
2442 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); 1857 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1858 * frames to RX queue #0.
1859 */
1860 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
2443 1861
2444 /* Accept frames with this address */ 1862 /*
2445 table = DA_FILTER_UNICAST_TABLE_BASE(port_num); 1863 * Treat BPDUs as normal multicasts, and disable partition mode.
2446 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); 1864 */
2447} 1865 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2448 1866
2449/* 1867 /*
2450 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers 1868 * Enable the receive queues.
2451 */ 1869 */
2452static void eth_port_uc_addr_get(struct mv643xx_private *mp, 1870 for (i = 0; i < 8; i++) {
2453 unsigned char *p_addr) 1871 struct rx_queue *rxq = mp->rxq + i;
2454{ 1872 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2455 unsigned int port_num = mp->port_num; 1873 u32 addr;
2456 unsigned int mac_h; 1874
2457 unsigned int mac_l; 1875 if ((mp->rxq_mask & (1 << i)) == 0)
1876 continue;
2458 1877
2459 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); 1878 addr = (u32)rxq->rx_desc_dma;
2460 mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); 1879 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1880 wrl(mp, off, addr);
2461 1881
2462 p_addr[0] = (mac_h >> 24) & 0xff; 1882 rxq_enable(rxq);
2463 p_addr[1] = (mac_h >> 16) & 0xff; 1883 }
2464 p_addr[2] = (mac_h >> 8) & 0xff;
2465 p_addr[3] = mac_h & 0xff;
2466 p_addr[4] = (mac_l >> 8) & 0xff;
2467 p_addr[5] = mac_l & 0xff;
2468} 1884}
2469 1885
2470/* 1886static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2471 * The entries in each table are indexed by a hash of a packet's MAC
2472 * address. One bit in each entry determines whether the packet is
2473 * accepted. There are 4 entries (each 8 bits wide) in each register
2474 * of the table. The bits in each entry are defined as follows:
2475 * 0 Accept=1, Drop=0
2476 * 3-1 Queue (ETH_Q0=0)
2477 * 7-4 Reserved = 0;
2478 */
2479static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2480 int table, unsigned char entry)
2481{ 1887{
2482 unsigned int table_reg; 1888 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2483 unsigned int tbl_offset; 1889 u32 val;
2484 unsigned int reg_offset; 1890
1891 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1892 if (mp->shared->extended_rx_coal_limit) {
1893 if (coal > 0xffff)
1894 coal = 0xffff;
1895 val &= ~0x023fff80;
1896 val |= (coal & 0x8000) << 10;
1897 val |= (coal & 0x7fff) << 7;
1898 } else {
1899 if (coal > 0x3fff)
1900 coal = 0x3fff;
1901 val &= ~0x003fff00;
1902 val |= (coal & 0x3fff) << 8;
1903 }
1904 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1905}
2485 1906
2486 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ 1907static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2487 reg_offset = entry % 4; /* Entry offset within the register */ 1908{
1909 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2488 1910
2489 /* Set "accepts frame bit" at specified table entry */ 1911 if (coal > 0x3fff)
2490 table_reg = rdl(mp, table + tbl_offset); 1912 coal = 0x3fff;
2491 table_reg |= 0x01 << (8 * reg_offset); 1913 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2492 wrl(mp, table + tbl_offset, table_reg);
2493} 1914}
2494 1915
2495/* 1916static int mv643xx_eth_open(struct net_device *dev)
2496 * eth_port_mc_addr - Multicast address settings.
2497 *
2498 * The MV device supports multicast using two tables:
2499 * 1) Special Multicast Table for MAC addresses of the form
2500 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2501 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2502 * Table entries in the DA-Filter table.
2503 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2504 * is used as an index to the Other Multicast Table entries in the
2505 * DA-Filter table. This function calculates the CRC-8bit value.
2506 * In either case, eth_port_set_filter_table_entry() is then called
2507 * to set to set the actual table entry.
2508 */
2509static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
2510{ 1917{
2511 unsigned int port_num = mp->port_num; 1918 struct mv643xx_eth_private *mp = netdev_priv(dev);
2512 unsigned int mac_h; 1919 int err;
2513 unsigned int mac_l;
2514 unsigned char crc_result = 0;
2515 int table;
2516 int mac_array[48];
2517 int crc[8];
2518 int i; 1920 int i;
2519 1921
2520 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && 1922 wrl(mp, INT_CAUSE(mp->port_num), 0);
2521 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { 1923 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2522 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num); 1924 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2523 eth_port_set_filter_table_entry(mp, table, p_addr[5]); 1925
2524 return; 1926 err = request_irq(dev->irq, mv643xx_eth_irq,
1927 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1928 dev->name, dev);
1929 if (err) {
1930 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1931 return -EAGAIN;
2525 } 1932 }
2526 1933
2527 /* Calculate CRC-8 out of the given address */ 1934 init_mac_tables(mp);
2528 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2529 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2530 (p_addr[4] << 8) | (p_addr[5] << 0);
2531
2532 for (i = 0; i < 32; i++)
2533 mac_array[i] = (mac_l >> i) & 0x1;
2534 for (i = 32; i < 48; i++)
2535 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2536
2537 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2538 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2539 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2540 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2541 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2542
2543 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2544 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2545 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2546 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2547 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2548 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2549 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2550
2551 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2552 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2553 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2554 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2555 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2556 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2557
2558 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2559 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2560 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2561 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2562 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2563 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2564
2565 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2566 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2567 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2568 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2569 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2570 mac_array[3] ^ mac_array[2];
2571
2572 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2573 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2574 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2575 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2576 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2577 mac_array[4] ^ mac_array[3];
2578
2579 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2580 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2581 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2582 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2583 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2584 mac_array[4];
2585
2586 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2587 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2588 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2589 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2590 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2591 1935
2592 for (i = 0; i < 8; i++) 1936 for (i = 0; i < 8; i++) {
2593 crc_result = crc_result | (crc[i] << i); 1937 if ((mp->rxq_mask & (1 << i)) == 0)
1938 continue;
2594 1939
2595 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num); 1940 err = rxq_init(mp, i);
2596 eth_port_set_filter_table_entry(mp, table, crc_result); 1941 if (err) {
2597} 1942 while (--i >= 0)
1943 if (mp->rxq_mask & (1 << i))
1944 rxq_deinit(mp->rxq + i);
1945 goto out;
1946 }
2598 1947
2599/* 1948 rxq_refill(mp->rxq + i);
2600 * Set the entire multicast list based on dev->mc_list. 1949 }
2601 */
2602static void eth_port_set_multicast_list(struct net_device *dev)
2603{
2604 1950
2605 struct dev_mc_list *mc_list; 1951 for (i = 0; i < 8; i++) {
2606 int i; 1952 if ((mp->txq_mask & (1 << i)) == 0)
2607 int table_index; 1953 continue;
2608 struct mv643xx_private *mp = netdev_priv(dev);
2609 unsigned int eth_port_num = mp->port_num;
2610 1954
2611 /* If the device is in promiscuous mode or in all multicast mode, 1955 err = txq_init(mp, i);
2612 * we will fully populate both multicast tables with accept. 1956 if (err) {
2613 * This is guaranteed to yield a match on all multicast addresses... 1957 while (--i >= 0)
2614 */ 1958 if (mp->txq_mask & (1 << i))
2615 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { 1959 txq_deinit(mp->txq + i);
2616 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 1960 goto out_free;
2617 /* Set all entries in DA filter special multicast
2618 * table (Ex_dFSMT)
2619 * Set for ETH_Q0 for now
2620 * Bits
2621 * 0 Accept=1, Drop=0
2622 * 3-1 Queue ETH_Q0=0
2623 * 7-4 Reserved = 0;
2624 */
2625 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2626
2627 /* Set all entries in DA filter other multicast
2628 * table (Ex_dFOMT)
2629 * Set for ETH_Q0 for now
2630 * Bits
2631 * 0 Accept=1, Drop=0
2632 * 3-1 Queue ETH_Q0=0
2633 * 7-4 Reserved = 0;
2634 */
2635 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2636 } 1961 }
2637 return;
2638 } 1962 }
2639 1963
2640 /* We will clear out multicast tables every time we get the list. 1964#ifdef MV643XX_ETH_NAPI
2641 * Then add the entire new list... 1965 napi_enable(&mp->napi);
2642 */ 1966#endif
2643 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 1967
2644 /* Clear DA filter special multicast table (Ex_dFSMT) */ 1968 port_start(mp);
2645 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2646 (eth_port_num) + table_index, 0);
2647
2648 /* Clear DA filter other multicast table (Ex_dFOMT) */
2649 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2650 (eth_port_num) + table_index, 0);
2651 }
2652 1969
2653 /* Get pointer to net_device multicast list and add each one... */ 1970 set_rx_coal(mp, 0);
2654 for (i = 0, mc_list = dev->mc_list; 1971 set_tx_coal(mp, 0);
2655 (i < 256) && (mc_list != NULL) && (i < dev->mc_count); 1972
2656 i++, mc_list = mc_list->next) 1973 wrl(mp, INT_MASK_EXT(mp->port_num),
2657 if (mc_list->dmi_addrlen == 6) 1974 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2658 eth_port_mc_addr(mp, mc_list->dmi_addr); 1975
1976 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1977
1978 return 0;
1979
1980
1981out_free:
1982 for (i = 0; i < 8; i++)
1983 if (mp->rxq_mask & (1 << i))
1984 rxq_deinit(mp->rxq + i);
1985out:
1986 free_irq(dev->irq, dev);
1987
1988 return err;
2659} 1989}
2660 1990
2661/* 1991static void port_reset(struct mv643xx_eth_private *mp)
2662 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 1992{
2663 * 1993 unsigned int data;
2664 * DESCRIPTION: 1994 int i;
2665 * Go through all the DA filter tables (Unicast, Special Multicast & 1995
2666 * Other Multicast) and set each entry to 0. 1996 for (i = 0; i < 8; i++) {
2667 * 1997 if (mp->rxq_mask & (1 << i))
2668 * INPUT: 1998 rxq_disable(mp->rxq + i);
2669 * struct mv643xx_private *mp Ethernet Port. 1999 if (mp->txq_mask & (1 << i))
2670 * 2000 txq_disable(mp->txq + i);
2671 * OUTPUT:
2672 * Multicast and Unicast packets are rejected.
2673 *
2674 * RETURN:
2675 * None.
2676 */
2677static void eth_port_init_mac_tables(struct mv643xx_private *mp)
2678{
2679 unsigned int port_num = mp->port_num;
2680 int table_index;
2681
2682 /* Clear DA filter unicast table (Ex_dFUT) */
2683 for (table_index = 0; table_index <= 0xC; table_index += 4)
2684 wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
2685 table_index, 0);
2686
2687 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2688 /* Clear DA filter special multicast table (Ex_dFSMT) */
2689 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
2690 table_index, 0);
2691 /* Clear DA filter other multicast table (Ex_dFOMT) */
2692 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
2693 table_index, 0);
2694 } 2001 }
2002 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2003 udelay(10);
2004
2005 /* Reset the Enable bit in the Configuration Register */
2006 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2007 data &= ~(SERIAL_PORT_ENABLE |
2008 DO_NOT_FORCE_LINK_FAIL |
2009 FORCE_LINK_PASS);
2010 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2695} 2011}
2696 2012
2697/* 2013static int mv643xx_eth_stop(struct net_device *dev)
2698 * eth_clear_mib_counters - Clear all MIB counters
2699 *
2700 * DESCRIPTION:
2701 * This function clears all MIB counters of a specific ethernet port.
2702 * A read from the MIB counter will reset the counter.
2703 *
2704 * INPUT:
2705 * struct mv643xx_private *mp Ethernet Port.
2706 *
2707 * OUTPUT:
2708 * After reading all MIB counters, the counters resets.
2709 *
2710 * RETURN:
2711 * MIB counter value.
2712 *
2713 */
2714static void eth_clear_mib_counters(struct mv643xx_private *mp)
2715{ 2014{
2716 unsigned int port_num = mp->port_num; 2015 struct mv643xx_eth_private *mp = netdev_priv(dev);
2717 int i; 2016 int i;
2718 2017
2719 /* Perform dummy reads from MIB counters */ 2018 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2720 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; 2019 rdl(mp, INT_MASK(mp->port_num));
2721 i += 4) 2020
2722 rdl(mp, MIB_COUNTERS_BASE(port_num) + i); 2021#ifdef MV643XX_ETH_NAPI
2022 napi_disable(&mp->napi);
2023#endif
2024 netif_carrier_off(dev);
2025 netif_stop_queue(dev);
2026
2027 free_irq(dev->irq, dev);
2028
2029 port_reset(mp);
2030 mib_counters_update(mp);
2031
2032 for (i = 0; i < 8; i++) {
2033 if (mp->rxq_mask & (1 << i))
2034 rxq_deinit(mp->rxq + i);
2035 if (mp->txq_mask & (1 << i))
2036 txq_deinit(mp->txq + i);
2037 }
2038
2039 return 0;
2723} 2040}
2724 2041
2725static inline u32 read_mib(struct mv643xx_private *mp, int offset) 2042static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2726{ 2043{
2727 return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset); 2044 struct mv643xx_eth_private *mp = netdev_priv(dev);
2045
2046 if (mp->phy_addr != -1)
2047 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2048
2049 return -EOPNOTSUPP;
2728} 2050}
2729 2051
2730static void eth_update_mib_counters(struct mv643xx_private *mp) 2052static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2731{ 2053{
2732 struct mv643xx_mib_counters *p = &mp->mib_counters; 2054 struct mv643xx_eth_private *mp = netdev_priv(dev);
2733 int offset;
2734 2055
2735 p->good_octets_received += 2056 if (new_mtu < 64 || new_mtu > 9500)
2736 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); 2057 return -EINVAL;
2737 p->good_octets_received +=
2738 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2739 2058
2740 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; 2059 dev->mtu = new_mtu;
2741 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; 2060 tx_set_rate(mp, 1000000000, 16777216);
2742 offset += 4)
2743 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2744 2061
2745 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); 2062 if (!netif_running(dev))
2746 p->good_octets_sent += 2063 return 0;
2747 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2748 2064
2749 for (offset = ETH_MIB_GOOD_FRAMES_SENT; 2065 /*
2750 offset <= ETH_MIB_LATE_COLLISION; 2066 * Stop and then re-open the interface. This will allocate RX
2751 offset += 4) 2067 * skbs of the new MTU.
2752 *(u32 *)((char *)p + offset) += read_mib(mp, offset); 2068 * There is a possible danger that the open will not succeed,
2069 * due to memory being full.
2070 */
2071 mv643xx_eth_stop(dev);
2072 if (mv643xx_eth_open(dev)) {
2073 dev_printk(KERN_ERR, &dev->dev,
2074 "fatal error on re-opening device after "
2075 "MTU change\n");
2076 }
2077
2078 return 0;
2753} 2079}
2754 2080
2755/* 2081static void tx_timeout_task(struct work_struct *ugly)
2756 * ethernet_phy_detect - Detect whether a phy is present
2757 *
2758 * DESCRIPTION:
2759 * This function tests whether there is a PHY present on
2760 * the specified port.
2761 *
2762 * INPUT:
2763 * struct mv643xx_private *mp Ethernet Port.
2764 *
2765 * OUTPUT:
2766 * None
2767 *
2768 * RETURN:
2769 * 0 on success
2770 * -ENODEV on failure
2771 *
2772 */
2773static int ethernet_phy_detect(struct mv643xx_private *mp)
2774{ 2082{
2775 unsigned int phy_reg_data0; 2083 struct mv643xx_eth_private *mp;
2776 int auto_neg;
2777 2084
2778 eth_port_read_smi_reg(mp, 0, &phy_reg_data0); 2085 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2779 auto_neg = phy_reg_data0 & 0x1000; 2086 if (netif_running(mp->dev)) {
2780 phy_reg_data0 ^= 0x1000; /* invert auto_neg */ 2087 netif_stop_queue(mp->dev);
2781 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2782 2088
2783 eth_port_read_smi_reg(mp, 0, &phy_reg_data0); 2089 port_reset(mp);
2784 if ((phy_reg_data0 & 0x1000) == auto_neg) 2090 port_start(mp);
2785 return -ENODEV; /* change didn't take */
2786 2091
2787 phy_reg_data0 ^= 0x1000; 2092 __txq_maybe_wake(mp->txq + mp->txq_primary);
2788 eth_port_write_smi_reg(mp, 0, phy_reg_data0); 2093 }
2789 return 0;
2790} 2094}
2791 2095
2792/* 2096static void mv643xx_eth_tx_timeout(struct net_device *dev)
2793 * ethernet_phy_get - Get the ethernet port PHY address.
2794 *
2795 * DESCRIPTION:
2796 * This routine returns the given ethernet port PHY address.
2797 *
2798 * INPUT:
2799 * struct mv643xx_private *mp Ethernet Port.
2800 *
2801 * OUTPUT:
2802 * None.
2803 *
2804 * RETURN:
2805 * PHY address.
2806 *
2807 */
2808static int ethernet_phy_get(struct mv643xx_private *mp)
2809{ 2097{
2810 unsigned int reg_data; 2098 struct mv643xx_eth_private *mp = netdev_priv(dev);
2811 2099
2812 reg_data = rdl(mp, PHY_ADDR_REG); 2100 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2813 2101
2814 return ((reg_data >> (5 * mp->port_num)) & 0x1f); 2102 schedule_work(&mp->tx_timeout_task);
2815} 2103}
2816 2104
2817/* 2105#ifdef CONFIG_NET_POLL_CONTROLLER
2818 * ethernet_phy_set - Set the ethernet port PHY address. 2106static void mv643xx_eth_netpoll(struct net_device *dev)
2819 *
2820 * DESCRIPTION:
2821 * This routine sets the given ethernet port PHY address.
2822 *
2823 * INPUT:
2824 * struct mv643xx_private *mp Ethernet Port.
2825 * int phy_addr PHY address.
2826 *
2827 * OUTPUT:
2828 * None.
2829 *
2830 * RETURN:
2831 * None.
2832 *
2833 */
2834static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2835{ 2107{
2836 u32 reg_data; 2108 struct mv643xx_eth_private *mp = netdev_priv(dev);
2837 int addr_shift = 5 * mp->port_num; 2109
2110 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2111 rdl(mp, INT_MASK(mp->port_num));
2112
2113 mv643xx_eth_irq(dev->irq, dev);
2838 2114
2839 reg_data = rdl(mp, PHY_ADDR_REG); 2115 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
2840 reg_data &= ~(0x1f << addr_shift);
2841 reg_data |= (phy_addr & 0x1f) << addr_shift;
2842 wrl(mp, PHY_ADDR_REG, reg_data);
2843} 2116}
2117#endif
2844 2118
2845/* 2119static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2846 * ethernet_phy_reset - Reset Ethernet port PHY.
2847 *
2848 * DESCRIPTION:
2849 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2850 *
2851 * INPUT:
2852 * struct mv643xx_private *mp Ethernet Port.
2853 *
2854 * OUTPUT:
2855 * The PHY is reset.
2856 *
2857 * RETURN:
2858 * None.
2859 *
2860 */
2861static void ethernet_phy_reset(struct mv643xx_private *mp)
2862{ 2120{
2863 unsigned int phy_reg_data; 2121 struct mv643xx_eth_private *mp = netdev_priv(dev);
2122 int val;
2864 2123
2865 /* Reset the PHY */ 2124 smi_reg_read(mp, addr, reg, &val);
2866 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2867 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2868 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2869 2125
2870 /* wait for PHY to come out of reset */ 2126 return val;
2871 do {
2872 udelay(1);
2873 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2874 } while (phy_reg_data & 0x8000);
2875} 2127}
2876 2128
2877static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, 2129static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2878 unsigned int queues)
2879{ 2130{
2880 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues); 2131 struct mv643xx_eth_private *mp = netdev_priv(dev);
2132 smi_reg_write(mp, addr, reg, val);
2881} 2133}
2882 2134
2883static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
2884 unsigned int queues)
2885{
2886 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
2887}
2888 2135
2889static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) 2136/* platform glue ************************************************************/
2137static void
2138mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2139 struct mbus_dram_target_info *dram)
2890{ 2140{
2891 unsigned int port_num = mp->port_num; 2141 void __iomem *base = msp->base;
2892 u32 queues; 2142 u32 win_enable;
2143 u32 win_protect;
2144 int i;
2893 2145
2894 /* Stop Tx port activity. Check port Tx activity. */ 2146 for (i = 0; i < 6; i++) {
2895 queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2147 writel(0, base + WINDOW_BASE(i));
2896 if (queues) { 2148 writel(0, base + WINDOW_SIZE(i));
2897 /* Issue stop command for active queues only */ 2149 if (i < 4)
2898 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2150 writel(0, base + WINDOW_REMAP_HIGH(i));
2151 }
2899 2152
2900 /* Wait for all Tx activity to terminate. */ 2153 win_enable = 0x3f;
2901 /* Check port cause register that all Tx queues are stopped */ 2154 win_protect = 0;
2902 while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2903 udelay(PHY_WAIT_MICRO_SECONDS);
2904 2155
2905 /* Wait for Tx FIFO to empty */ 2156 for (i = 0; i < dram->num_cs; i++) {
2906 while (rdl(mp, PORT_STATUS_REG(port_num)) & 2157 struct mbus_dram_window *cs = dram->cs + i;
2907 ETH_PORT_TX_FIFO_EMPTY) 2158
2908 udelay(PHY_WAIT_MICRO_SECONDS); 2159 writel((cs->base & 0xffff0000) |
2160 (cs->mbus_attr << 8) |
2161 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2162 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2163
2164 win_enable &= ~(1 << i);
2165 win_protect |= 3 << (2 * i);
2909 } 2166 }
2910 2167
2911 return queues; 2168 writel(win_enable, base + WINDOW_BAR_ENABLE);
2169 msp->win_protect = win_protect;
2912} 2170}
2913 2171
2914static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) 2172static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2915{ 2173{
2916 unsigned int port_num = mp->port_num; 2174 /*
2917 u32 queues; 2175 * Check whether we have a 14-bit coal limit field in bits
2918 2176 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2919 /* Stop Rx port activity. Check port Rx activity. */ 2177 * SDMA config register.
2920 queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2178 */
2921 if (queues) { 2179 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2922 /* Issue stop command for active queues only */ 2180 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2923 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2181 msp->extended_rx_coal_limit = 1;
2924 2182 else
2925 /* Wait for all Rx activity to terminate. */ 2183 msp->extended_rx_coal_limit = 0;
2926 /* Check port cause register that all Rx queues are stopped */
2927 while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2928 udelay(PHY_WAIT_MICRO_SECONDS);
2929 }
2930 2184
2931 return queues; 2185 /*
2186 * Check whether the TX rate control registers are in the
2187 * old or the new place.
2188 */
2189 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2190 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2191 msp->tx_bw_control_moved = 1;
2192 else
2193 msp->tx_bw_control_moved = 0;
2932} 2194}
2933 2195
2934/* 2196static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2935 * eth_port_reset - Reset Ethernet port
2936 *
2937 * DESCRIPTION:
2938 * This routine resets the chip by aborting any SDMA engine activity and
2939 * clearing the MIB counters. The Receiver and the Transmit unit are in
2940 * idle state after this command is performed and the port is disabled.
2941 *
2942 * INPUT:
2943 * struct mv643xx_private *mp Ethernet Port.
2944 *
2945 * OUTPUT:
2946 * Channel activity is halted.
2947 *
2948 * RETURN:
2949 * None.
2950 *
2951 */
2952static void eth_port_reset(struct mv643xx_private *mp)
2953{ 2197{
2954 unsigned int port_num = mp->port_num; 2198 static int mv643xx_eth_version_printed = 0;
2955 unsigned int reg_data; 2199 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2200 struct mv643xx_eth_shared_private *msp;
2201 struct resource *res;
2202 int ret;
2956 2203
2957 mv643xx_eth_port_disable_tx(mp); 2204 if (!mv643xx_eth_version_printed++)
2958 mv643xx_eth_port_disable_rx(mp); 2205 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2959 2206
2960 /* Clear all MIB counters */ 2207 ret = -EINVAL;
2961 eth_clear_mib_counters(mp); 2208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2209 if (res == NULL)
2210 goto out;
2962 2211
2963 /* Reset the Enable bit in the Configuration Register */ 2212 ret = -ENOMEM;
2964 reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); 2213 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2965 reg_data &= ~(SERIAL_PORT_ENABLE | 2214 if (msp == NULL)
2966 DO_NOT_FORCE_LINK_FAIL | 2215 goto out;
2967 FORCE_LINK_PASS); 2216 memset(msp, 0, sizeof(*msp));
2968 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2969}
2970 2217
2218 msp->base = ioremap(res->start, res->end - res->start + 1);
2219 if (msp->base == NULL)
2220 goto out_free;
2971 2221
2972/* 2222 spin_lock_init(&msp->phy_lock);
2973 * eth_port_read_smi_reg - Read PHY registers
2974 *
2975 * DESCRIPTION:
2976 * This routine utilize the SMI interface to interact with the PHY in
2977 * order to perform PHY register read.
2978 *
2979 * INPUT:
2980 * struct mv643xx_private *mp Ethernet Port.
2981 * unsigned int phy_reg PHY register address offset.
2982 * unsigned int *value Register value buffer.
2983 *
2984 * OUTPUT:
2985 * Write the value of a specified PHY register into given buffer.
2986 *
2987 * RETURN:
2988 * false if the PHY is busy or read data is not in valid state.
2989 * true otherwise.
2990 *
2991 */
2992static void eth_port_read_smi_reg(struct mv643xx_private *mp,
2993 unsigned int phy_reg, unsigned int *value)
2994{
2995 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
2996 int phy_addr = ethernet_phy_get(mp);
2997 unsigned long flags;
2998 int i;
2999 2223
3000 /* the SMI register is a shared resource */ 2224 /*
3001 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); 2225 * (Re-)program MBUS remapping windows if we are asked to.
2226 */
2227 if (pd != NULL && pd->dram != NULL)
2228 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
3002 2229
3003 /* wait for the SMI register to become available */ 2230 /*
3004 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { 2231 * Detect hardware parameters.
3005 if (i == PHY_WAIT_ITERATIONS) { 2232 */
3006 printk("%s: PHY busy timeout\n", mp->dev->name); 2233 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
3007 goto out; 2234 infer_hw_params(msp);
3008 }
3009 udelay(PHY_WAIT_MICRO_SECONDS);
3010 }
3011 2235
3012 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, 2236 platform_set_drvdata(pdev, msp);
3013 smi_reg);
3014 2237
3015 /* now wait for the data to be valid */ 2238 return 0;
3016 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
3017 if (i == PHY_WAIT_ITERATIONS) {
3018 printk("%s: PHY read timeout\n", mp->dev->name);
3019 goto out;
3020 }
3021 udelay(PHY_WAIT_MICRO_SECONDS);
3022 }
3023 2239
3024 *value = readl(smi_reg) & 0xffff; 2240out_free:
2241 kfree(msp);
3025out: 2242out:
3026 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); 2243 return ret;
3027} 2244}
3028 2245
3029/* 2246static int mv643xx_eth_shared_remove(struct platform_device *pdev)
3030 * eth_port_write_smi_reg - Write to PHY registers
3031 *
3032 * DESCRIPTION:
3033 * This routine utilize the SMI interface to interact with the PHY in
3034 * order to perform writes to PHY registers.
3035 *
3036 * INPUT:
3037 * struct mv643xx_private *mp Ethernet Port.
3038 * unsigned int phy_reg PHY register address offset.
3039 * unsigned int value Register value.
3040 *
3041 * OUTPUT:
3042 * Write the given value to the specified PHY register.
3043 *
3044 * RETURN:
3045 * false if the PHY is busy.
3046 * true otherwise.
3047 *
3048 */
3049static void eth_port_write_smi_reg(struct mv643xx_private *mp,
3050 unsigned int phy_reg, unsigned int value)
3051{ 2247{
3052 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; 2248 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
3053 int phy_addr = ethernet_phy_get(mp);
3054 unsigned long flags;
3055 int i;
3056
3057 /* the SMI register is a shared resource */
3058 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
3059 2249
3060 /* wait for the SMI register to become available */ 2250 iounmap(msp->base);
3061 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { 2251 kfree(msp);
3062 if (i == PHY_WAIT_ITERATIONS) {
3063 printk("%s: PHY busy timeout\n", mp->dev->name);
3064 goto out;
3065 }
3066 udelay(PHY_WAIT_MICRO_SECONDS);
3067 }
3068 2252
3069 writel((phy_addr << 16) | (phy_reg << 21) | 2253 return 0;
3070 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
3071out:
3072 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
3073} 2254}
3074 2255
3075/* 2256static struct platform_driver mv643xx_eth_shared_driver = {
3076 * Wrappers for MII support library. 2257 .probe = mv643xx_eth_shared_probe,
3077 */ 2258 .remove = mv643xx_eth_shared_remove,
3078static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) 2259 .driver = {
2260 .name = MV643XX_ETH_SHARED_NAME,
2261 .owner = THIS_MODULE,
2262 },
2263};
2264
2265static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
3079{ 2266{
3080 struct mv643xx_private *mp = netdev_priv(dev); 2267 int addr_shift = 5 * mp->port_num;
3081 int val; 2268 u32 data;
3082 2269
3083 eth_port_read_smi_reg(mp, location, &val); 2270 data = rdl(mp, PHY_ADDR);
3084 return val; 2271 data &= ~(0x1f << addr_shift);
2272 data |= (phy_addr & 0x1f) << addr_shift;
2273 wrl(mp, PHY_ADDR, data);
3085} 2274}
3086 2275
3087static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) 2276static int phy_addr_get(struct mv643xx_eth_private *mp)
3088{ 2277{
3089 struct mv643xx_private *mp = netdev_priv(dev); 2278 unsigned int data;
3090 eth_port_write_smi_reg(mp, location, val); 2279
2280 data = rdl(mp, PHY_ADDR);
2281
2282 return (data >> (5 * mp->port_num)) & 0x1f;
3091} 2283}
3092 2284
3093/* 2285static void set_params(struct mv643xx_eth_private *mp,
3094 * eth_port_receive - Get received information from Rx ring. 2286 struct mv643xx_eth_platform_data *pd)
3095 *
3096 * DESCRIPTION:
3097 * This routine returns the received data to the caller. There is no
3098 * data copying during routine operation. All information is returned
3099 * using pointer to packet information struct passed from the caller.
3100 * If the routine exhausts Rx ring resources then the resource error flag
3101 * is set.
3102 *
3103 * INPUT:
3104 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3105 * struct pkt_info *p_pkt_info User packet buffer.
3106 *
3107 * OUTPUT:
3108 * Rx ring current and used indexes are updated.
3109 *
3110 * RETURN:
3111 * ETH_ERROR in case the routine can not access Rx desc ring.
3112 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3113 * ETH_END_OF_JOB if there is no received data.
3114 * ETH_OK otherwise.
3115 */
3116static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
3117 struct pkt_info *p_pkt_info)
3118{ 2287{
3119 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 2288 struct net_device *dev = mp->dev;
3120 volatile struct eth_rx_desc *p_rx_desc;
3121 unsigned int command_status;
3122 unsigned long flags;
3123 2289
3124 /* Do not process Rx ring in case of Rx ring resource error */ 2290 if (is_valid_ether_addr(pd->mac_addr))
3125 if (mp->rx_resource_err) 2291 memcpy(dev->dev_addr, pd->mac_addr, 6);
3126 return ETH_QUEUE_FULL; 2292 else
2293 uc_addr_get(mp, dev->dev_addr);
3127 2294
3128 spin_lock_irqsave(&mp->lock, flags); 2295 if (pd->phy_addr == -1) {
2296 mp->shared_smi = NULL;
2297 mp->phy_addr = -1;
2298 } else {
2299 mp->shared_smi = mp->shared;
2300 if (pd->shared_smi != NULL)
2301 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
3129 2302
3130 /* Get the Rx Desc ring 'curr and 'used' indexes */ 2303 if (pd->force_phy_addr || pd->phy_addr) {
3131 rx_curr_desc = mp->rx_curr_desc_q; 2304 mp->phy_addr = pd->phy_addr & 0x3f;
3132 rx_used_desc = mp->rx_used_desc_q; 2305 phy_addr_set(mp, mp->phy_addr);
2306 } else {
2307 mp->phy_addr = phy_addr_get(mp);
2308 }
2309 }
3133 2310
3134 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; 2311 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2312 if (pd->rx_queue_size)
2313 mp->default_rx_ring_size = pd->rx_queue_size;
2314 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2315 mp->rx_desc_sram_size = pd->rx_sram_size;
3135 2316
3136 /* The following parameters are used to save readings from memory */ 2317 if (pd->rx_queue_mask)
3137 command_status = p_rx_desc->cmd_sts; 2318 mp->rxq_mask = pd->rx_queue_mask;
3138 rmb(); 2319 else
2320 mp->rxq_mask = 0x01;
2321 mp->rxq_primary = fls(mp->rxq_mask) - 1;
3139 2322
3140 /* Nothing to receive... */ 2323 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
3141 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { 2324 if (pd->tx_queue_size)
3142 spin_unlock_irqrestore(&mp->lock, flags); 2325 mp->default_tx_ring_size = pd->tx_queue_size;
3143 return ETH_END_OF_JOB; 2326 mp->tx_desc_sram_addr = pd->tx_sram_addr;
3144 } 2327 mp->tx_desc_sram_size = pd->tx_sram_size;
3145 2328
3146 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; 2329 if (pd->tx_queue_mask)
3147 p_pkt_info->cmd_sts = command_status; 2330 mp->txq_mask = pd->tx_queue_mask;
3148 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; 2331 else
3149 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; 2332 mp->txq_mask = 0x01;
3150 p_pkt_info->l4i_chk = p_rx_desc->buf_size; 2333 mp->txq_primary = fls(mp->txq_mask) - 1;
2334}
3151 2335
3152 /* 2336static int phy_detect(struct mv643xx_eth_private *mp)
3153 * Clean the return info field to indicate that the 2337{
3154 * packet has been moved to the upper layers 2338 unsigned int data;
3155 */ 2339 unsigned int data2;
3156 mp->rx_skb[rx_curr_desc] = NULL;
3157 2340
3158 /* Update current index in data structure */ 2341 smi_reg_read(mp, mp->phy_addr, 0, &data);
3159 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; 2342 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
3160 mp->rx_curr_desc_q = rx_next_curr_desc;
3161 2343
3162 /* Rx descriptors exhausted. Set the Rx ring resource error flag */ 2344 smi_reg_read(mp, mp->phy_addr, 0, &data2);
3163 if (rx_next_curr_desc == rx_used_desc) 2345 if (((data ^ data2) & 0x1000) == 0)
3164 mp->rx_resource_err = 1; 2346 return -ENODEV;
3165 2347
3166 spin_unlock_irqrestore(&mp->lock, flags); 2348 smi_reg_write(mp, mp->phy_addr, 0, data);
3167 2349
3168 return ETH_OK; 2350 return 0;
3169} 2351}
3170 2352
3171/* 2353static int phy_init(struct mv643xx_eth_private *mp,
3172 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. 2354 struct mv643xx_eth_platform_data *pd)
3173 *
3174 * DESCRIPTION:
3175 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3176 * next 'used' descriptor and attached the returned buffer to it.
3177 * In case the Rx ring was in "resource error" condition, where there are
3178 * no available Rx resources, the function resets the resource error flag.
3179 *
3180 * INPUT:
3181 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3182 * struct pkt_info *p_pkt_info Information on returned buffer.
3183 *
3184 * OUTPUT:
3185 * New available Rx resource in Rx descriptor ring.
3186 *
3187 * RETURN:
3188 * ETH_ERROR in case the routine can not access Rx desc ring.
3189 * ETH_OK otherwise.
3190 */
3191static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
3192 struct pkt_info *p_pkt_info)
3193{ 2355{
3194 int used_rx_desc; /* Where to return Rx resource */ 2356 struct ethtool_cmd cmd;
3195 volatile struct eth_rx_desc *p_used_rx_desc; 2357 int err;
3196 unsigned long flags;
3197 2358
3198 spin_lock_irqsave(&mp->lock, flags); 2359 err = phy_detect(mp);
2360 if (err) {
2361 dev_printk(KERN_INFO, &mp->dev->dev,
2362 "no PHY detected at addr %d\n", mp->phy_addr);
2363 return err;
2364 }
2365 phy_reset(mp);
3199 2366
3200 /* Get 'used' Rx descriptor */ 2367 mp->mii.phy_id = mp->phy_addr;
3201 used_rx_desc = mp->rx_used_desc_q; 2368 mp->mii.phy_id_mask = 0x3f;
3202 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; 2369 mp->mii.reg_num_mask = 0x1f;
2370 mp->mii.dev = mp->dev;
2371 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2372 mp->mii.mdio_write = mv643xx_eth_mdio_write;
3203 2373
3204 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; 2374 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
3205 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3206 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3207 2375
3208 /* Flush the write pipe */ 2376 memset(&cmd, 0, sizeof(cmd));
2377
2378 cmd.port = PORT_MII;
2379 cmd.transceiver = XCVR_INTERNAL;
2380 cmd.phy_address = mp->phy_addr;
2381 if (pd->speed == 0) {
2382 cmd.autoneg = AUTONEG_ENABLE;
2383 cmd.speed = SPEED_100;
2384 cmd.advertising = ADVERTISED_10baseT_Half |
2385 ADVERTISED_10baseT_Full |
2386 ADVERTISED_100baseT_Half |
2387 ADVERTISED_100baseT_Full;
2388 if (mp->mii.supports_gmii)
2389 cmd.advertising |= ADVERTISED_1000baseT_Full;
2390 } else {
2391 cmd.autoneg = AUTONEG_DISABLE;
2392 cmd.speed = pd->speed;
2393 cmd.duplex = pd->duplex;
2394 }
3209 2395
3210 /* Return the descriptor to DMA ownership */ 2396 update_pscr(mp, cmd.speed, cmd.duplex);
3211 wmb(); 2397 mv643xx_eth_set_settings(mp->dev, &cmd);
3212 p_used_rx_desc->cmd_sts =
3213 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3214 wmb();
3215 2398
3216 /* Move the used descriptor pointer to the next descriptor */ 2399 return 0;
3217 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; 2400}
3218 2401
3219 /* Any Rx return cancels the Rx resource error status */ 2402static int mv643xx_eth_probe(struct platform_device *pdev)
3220 mp->rx_resource_err = 0; 2403{
2404 struct mv643xx_eth_platform_data *pd;
2405 struct mv643xx_eth_private *mp;
2406 struct net_device *dev;
2407 struct resource *res;
2408 DECLARE_MAC_BUF(mac);
2409 int err;
3221 2410
3222 spin_unlock_irqrestore(&mp->lock, flags); 2411 pd = pdev->dev.platform_data;
2412 if (pd == NULL) {
2413 dev_printk(KERN_ERR, &pdev->dev,
2414 "no mv643xx_eth_platform_data\n");
2415 return -ENODEV;
2416 }
3223 2417
3224 return ETH_OK; 2418 if (pd->shared == NULL) {
3225} 2419 dev_printk(KERN_ERR, &pdev->dev,
2420 "no mv643xx_eth_platform_data->shared\n");
2421 return -ENODEV;
2422 }
3226 2423
3227/************* Begin ethtool support *************************/ 2424 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2425 if (!dev)
2426 return -ENOMEM;
3228 2427
3229struct mv643xx_stats { 2428 mp = netdev_priv(dev);
3230 char stat_string[ETH_GSTRING_LEN]; 2429 platform_set_drvdata(pdev, mp);
3231 int sizeof_stat;
3232 int stat_offset;
3233};
3234 2430
3235#define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ 2431 mp->shared = platform_get_drvdata(pd->shared);
3236 offsetof(struct mv643xx_private, m) 2432 mp->port_num = pd->port_number;
3237
3238static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3239 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3240 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3241 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3242 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3243 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3244 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3245 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3246 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3247 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3248 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3249 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3250 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3251 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3252 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3253 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3254 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3255 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3256 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3257 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3258 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3259 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3260 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3261 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3262 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3263 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3264 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3265 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3266 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3267 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3268 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3269 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3270 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3271 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3272 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3273 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3274 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3275 { "collision", MV643XX_STAT(mib_counters.collision) },
3276 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3277};
3278 2433
3279#define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) 2434 mp->dev = dev;
2435#ifdef MV643XX_ETH_NAPI
2436 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2437#endif
3280 2438
3281static void mv643xx_get_drvinfo(struct net_device *netdev, 2439 set_params(mp, pd);
3282 struct ethtool_drvinfo *drvinfo)
3283{
3284 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3285 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3286 strncpy(drvinfo->fw_version, "N/A", 32);
3287 strncpy(drvinfo->bus_info, "mv643xx", 32);
3288 drvinfo->n_stats = MV643XX_STATS_LEN;
3289}
3290 2440
3291static int mv643xx_get_sset_count(struct net_device *netdev, int sset) 2441 spin_lock_init(&mp->lock);
3292{
3293 switch (sset) {
3294 case ETH_SS_STATS:
3295 return MV643XX_STATS_LEN;
3296 default:
3297 return -EOPNOTSUPP;
3298 }
3299}
3300 2442
3301static void mv643xx_get_ethtool_stats(struct net_device *netdev, 2443 mib_counters_clear(mp);
3302 struct ethtool_stats *stats, uint64_t *data) 2444 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3303{
3304 struct mv643xx_private *mp = netdev->priv;
3305 int i;
3306 2445
3307 eth_update_mib_counters(mp); 2446 if (mp->phy_addr != -1) {
2447 err = phy_init(mp, pd);
2448 if (err)
2449 goto out;
3308 2450
3309 for (i = 0; i < MV643XX_STATS_LEN; i++) { 2451 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
3310 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; 2452 } else {
3311 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == 2453 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
3312 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3313 } 2454 }
3314}
3315 2455
3316static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3317 uint8_t *data)
3318{
3319 int i;
3320 2456
3321 switch(stringset) { 2457 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3322 case ETH_SS_STATS: 2458 BUG_ON(!res);
3323 for (i=0; i < MV643XX_STATS_LEN; i++) { 2459 dev->irq = res->start;
3324 memcpy(data + i * ETH_GSTRING_LEN, 2460
3325 mv643xx_gstrings_stats[i].stat_string, 2461 dev->hard_start_xmit = mv643xx_eth_xmit;
3326 ETH_GSTRING_LEN); 2462 dev->open = mv643xx_eth_open;
3327 } 2463 dev->stop = mv643xx_eth_stop;
3328 break; 2464 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
3329 } 2465 dev->set_mac_address = mv643xx_eth_set_mac_address;
2466 dev->do_ioctl = mv643xx_eth_ioctl;
2467 dev->change_mtu = mv643xx_eth_change_mtu;
2468 dev->tx_timeout = mv643xx_eth_tx_timeout;
2469#ifdef CONFIG_NET_POLL_CONTROLLER
2470 dev->poll_controller = mv643xx_eth_netpoll;
2471#endif
2472 dev->watchdog_timeo = 2 * HZ;
2473 dev->base_addr = 0;
2474
2475#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2476 /*
2477 * Zero copy can only work if we use Discovery II memory. Else, we will
2478 * have to map the buffers to ISA memory which is only 16 MB
2479 */
2480 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2481#endif
2482
2483 SET_NETDEV_DEV(dev, &pdev->dev);
2484
2485 if (mp->shared->win_protect)
2486 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2487
2488 err = register_netdev(dev);
2489 if (err)
2490 goto out;
2491
2492 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2493 mp->port_num, print_mac(mac, dev->dev_addr));
2494
2495 if (dev->features & NETIF_F_SG)
2496 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2497
2498 if (dev->features & NETIF_F_IP_CSUM)
2499 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2500
2501#ifdef MV643XX_ETH_NAPI
2502 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2503#endif
2504
2505 if (mp->tx_desc_sram_size > 0)
2506 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2507
2508 return 0;
2509
2510out:
2511 free_netdev(dev);
2512
2513 return err;
3330} 2514}
3331 2515
3332static u32 mv643xx_eth_get_link(struct net_device *dev) 2516static int mv643xx_eth_remove(struct platform_device *pdev)
3333{ 2517{
3334 struct mv643xx_private *mp = netdev_priv(dev); 2518 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3335 2519
3336 return mii_link_ok(&mp->mii); 2520 unregister_netdev(mp->dev);
2521 flush_scheduled_work();
2522 free_netdev(mp->dev);
2523
2524 platform_set_drvdata(pdev, NULL);
2525
2526 return 0;
3337} 2527}
3338 2528
3339static int mv643xx_eth_nway_restart(struct net_device *dev) 2529static void mv643xx_eth_shutdown(struct platform_device *pdev)
3340{ 2530{
3341 struct mv643xx_private *mp = netdev_priv(dev); 2531 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3342 2532
3343 return mii_nway_restart(&mp->mii); 2533 /* Mask all interrupts on ethernet port */
2534 wrl(mp, INT_MASK(mp->port_num), 0);
2535 rdl(mp, INT_MASK(mp->port_num));
2536
2537 if (netif_running(mp->dev))
2538 port_reset(mp);
3344} 2539}
3345 2540
3346static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2541static struct platform_driver mv643xx_eth_driver = {
2542 .probe = mv643xx_eth_probe,
2543 .remove = mv643xx_eth_remove,
2544 .shutdown = mv643xx_eth_shutdown,
2545 .driver = {
2546 .name = MV643XX_ETH_NAME,
2547 .owner = THIS_MODULE,
2548 },
2549};
2550
2551static int __init mv643xx_eth_init_module(void)
3347{ 2552{
3348 struct mv643xx_private *mp = netdev_priv(dev); 2553 int rc;
2554
2555 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2556 if (!rc) {
2557 rc = platform_driver_register(&mv643xx_eth_driver);
2558 if (rc)
2559 platform_driver_unregister(&mv643xx_eth_shared_driver);
2560 }
3349 2561
3350 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); 2562 return rc;
3351} 2563}
2564module_init(mv643xx_eth_init_module);
3352 2565
3353static const struct ethtool_ops mv643xx_ethtool_ops = { 2566static void __exit mv643xx_eth_cleanup_module(void)
3354 .get_settings = mv643xx_get_settings, 2567{
3355 .set_settings = mv643xx_set_settings, 2568 platform_driver_unregister(&mv643xx_eth_driver);
3356 .get_drvinfo = mv643xx_get_drvinfo, 2569 platform_driver_unregister(&mv643xx_eth_shared_driver);
3357 .get_link = mv643xx_eth_get_link, 2570}
3358 .set_sg = ethtool_op_set_sg, 2571module_exit(mv643xx_eth_cleanup_module);
3359 .get_sset_count = mv643xx_get_sset_count,
3360 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3361 .get_strings = mv643xx_get_strings,
3362 .nway_reset = mv643xx_eth_nway_restart,
3363};
3364 2572
3365/************* End ethtool support *************************/ 2573MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2574 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2575MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2576MODULE_LICENSE("GPL");
2577MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2578MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-24 21:33:49 -0500