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-rw-r--r--drivers/net/mv643xx_eth.c473
1 files changed, 230 insertions, 243 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index d65cadef4d22..601ffd69ebc8 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -3,7 +3,8 @@
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 * 4 *
5 * Based on the 64360 driver from: 5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
7 * 8 *
8 * Copyright (C) 2003 PMC-Sierra, Inc., 9 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani 10 * written by Manish Lachwani
@@ -16,6 +17,9 @@
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com> 18 * <sjhill@realitydiluted.com>
18 * 19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
19 * This program is free software; you can redistribute it and/or 23 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License 24 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2 25 * as published by the Free Software Foundation; either version 2
@@ -63,20 +67,6 @@
63#define MV643XX_TX_FAST_REFILL 67#define MV643XX_TX_FAST_REFILL
64#undef MV643XX_COAL 68#undef MV643XX_COAL
65 69
66/*
67 * Number of RX / TX descriptors on RX / TX rings.
68 * Note that allocating RX descriptors is done by allocating the RX
69 * ring AND a preallocated RX buffers (skb's) for each descriptor.
70 * The TX descriptors only allocates the TX descriptors ring,
71 * with no pre allocated TX buffers (skb's are allocated by higher layers.
72 */
73
74/* Default TX ring size is 1000 descriptors */
75#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
76
77/* Default RX ring size is 400 descriptors */
78#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
79
80#define MV643XX_TX_COAL 100 70#define MV643XX_TX_COAL 100
81#ifdef MV643XX_COAL 71#ifdef MV643XX_COAL
82#define MV643XX_RX_COAL 100 72#define MV643XX_RX_COAL 100
@@ -434,14 +424,6 @@ typedef enum _eth_func_ret_status {
434 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ 424 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
435} ETH_FUNC_RET_STATUS; 425} ETH_FUNC_RET_STATUS;
436 426
437typedef enum _eth_target {
438 ETH_TARGET_DRAM,
439 ETH_TARGET_DEVICE,
440 ETH_TARGET_CBS,
441 ETH_TARGET_PCI0,
442 ETH_TARGET_PCI1
443} ETH_TARGET;
444
445/* These are for big-endian machines. Little endian needs different 427/* These are for big-endian machines. Little endian needs different
446 * definitions. 428 * definitions.
447 */ 429 */
@@ -586,43 +568,44 @@ struct mv643xx_private {
586 568
587/* Static function declarations */ 569/* Static function declarations */
588static void eth_port_init(struct mv643xx_private *mp); 570static void eth_port_init(struct mv643xx_private *mp);
589static void eth_port_reset(unsigned int eth_port_num); 571static void eth_port_reset(struct mv643xx_private *mp);
590static void eth_port_start(struct net_device *dev); 572static void eth_port_start(struct net_device *dev);
591 573
592static void ethernet_phy_reset(unsigned int eth_port_num); 574static void ethernet_phy_reset(struct mv643xx_private *mp);
593 575
594static void eth_port_write_smi_reg(unsigned int eth_port_num, 576static void eth_port_write_smi_reg(struct mv643xx_private *mp,
595 unsigned int phy_reg, unsigned int value); 577 unsigned int phy_reg, unsigned int value);
596 578
597static void eth_port_read_smi_reg(unsigned int eth_port_num, 579static void eth_port_read_smi_reg(struct mv643xx_private *mp,
598 unsigned int phy_reg, unsigned int *value); 580 unsigned int phy_reg, unsigned int *value);
599 581
600static void eth_clear_mib_counters(unsigned int eth_port_num); 582static void eth_clear_mib_counters(struct mv643xx_private *mp);
601 583
602static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, 584static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
603 struct pkt_info *p_pkt_info); 585 struct pkt_info *p_pkt_info);
604static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, 586static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
605 struct pkt_info *p_pkt_info); 587 struct pkt_info *p_pkt_info);
606 588
607static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr); 589static void eth_port_uc_addr_get(struct mv643xx_private *mp,
608static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr); 590 unsigned char *p_addr);
591static void eth_port_uc_addr_set(struct mv643xx_private *mp,
592 unsigned char *p_addr);
609static void eth_port_set_multicast_list(struct net_device *); 593static void eth_port_set_multicast_list(struct net_device *);
610static void mv643xx_eth_port_enable_tx(unsigned int port_num, 594static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
611 unsigned int queues); 595 unsigned int queues);
612static void mv643xx_eth_port_enable_rx(unsigned int port_num, 596static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
613 unsigned int queues); 597 unsigned int queues);
614static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num); 598static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
615static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num); 599static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
616static int mv643xx_eth_open(struct net_device *); 600static int mv643xx_eth_open(struct net_device *);
617static int mv643xx_eth_stop(struct net_device *); 601static int mv643xx_eth_stop(struct net_device *);
618static int mv643xx_eth_change_mtu(struct net_device *, int); 602static void eth_port_init_mac_tables(struct mv643xx_private *mp);
619static void eth_port_init_mac_tables(unsigned int eth_port_num);
620#ifdef MV643XX_NAPI 603#ifdef MV643XX_NAPI
621static int mv643xx_poll(struct napi_struct *napi, int budget); 604static int mv643xx_poll(struct napi_struct *napi, int budget);
622#endif 605#endif
623static int ethernet_phy_get(unsigned int eth_port_num); 606static int ethernet_phy_get(struct mv643xx_private *mp);
624static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); 607static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
625static int ethernet_phy_detect(unsigned int eth_port_num); 608static int ethernet_phy_detect(struct mv643xx_private *mp);
626static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location); 609static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
627static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val); 610static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
628static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 611static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
@@ -636,12 +619,12 @@ static void __iomem *mv643xx_eth_base;
636/* used to protect SMI_REG, which is shared across ports */ 619/* used to protect SMI_REG, which is shared across ports */
637static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); 620static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
638 621
639static inline u32 mv_read(int offset) 622static inline u32 rdl(struct mv643xx_private *mp, int offset)
640{ 623{
641 return readl(mv643xx_eth_base + offset); 624 return readl(mv643xx_eth_base + offset);
642} 625}
643 626
644static inline void mv_write(int offset, u32 data) 627static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
645{ 628{
646 writel(data, mv643xx_eth_base + offset); 629 writel(data, mv643xx_eth_base + offset);
647} 630}
@@ -659,18 +642,19 @@ static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
659 return -EINVAL; 642 return -EINVAL;
660 643
661 dev->mtu = new_mtu; 644 dev->mtu = new_mtu;
645 if (!netif_running(dev))
646 return 0;
647
662 /* 648 /*
663 * Stop then re-open the interface. This will allocate RX skb's with 649 * Stop and then re-open the interface. This will allocate RX
664 * the new MTU. 650 * skbs of the new MTU.
665 * There is a possible danger that the open will not successed, due 651 * There is a possible danger that the open will not succeed,
666 * to memory is full, which might fail the open function. 652 * due to memory being full, which might fail the open function.
667 */ 653 */
668 if (netif_running(dev)) { 654 mv643xx_eth_stop(dev);
669 mv643xx_eth_stop(dev); 655 if (mv643xx_eth_open(dev)) {
670 if (mv643xx_eth_open(dev)) 656 printk(KERN_ERR "%s: Fatal error on opening device\n",
671 printk(KERN_ERR 657 dev->name);
672 "%s: Fatal error on opening device\n",
673 dev->name);
674 } 658 }
675 659
676 return 0; 660 return 0;
@@ -748,10 +732,9 @@ static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
748static void mv643xx_eth_update_mac_address(struct net_device *dev) 732static void mv643xx_eth_update_mac_address(struct net_device *dev)
749{ 733{
750 struct mv643xx_private *mp = netdev_priv(dev); 734 struct mv643xx_private *mp = netdev_priv(dev);
751 unsigned int port_num = mp->port_num;
752 735
753 eth_port_init_mac_tables(port_num); 736 eth_port_init_mac_tables(mp);
754 eth_port_uc_addr_set(port_num, dev->dev_addr); 737 eth_port_uc_addr_set(mp, dev->dev_addr);
755} 738}
756 739
757/* 740/*
@@ -767,12 +750,12 @@ static void mv643xx_eth_set_rx_mode(struct net_device *dev)
767 struct mv643xx_private *mp = netdev_priv(dev); 750 struct mv643xx_private *mp = netdev_priv(dev);
768 u32 config_reg; 751 u32 config_reg;
769 752
770 config_reg = mv_read(PORT_CONFIG_REG(mp->port_num)); 753 config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num));
771 if (dev->flags & IFF_PROMISC) 754 if (dev->flags & IFF_PROMISC)
772 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; 755 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
773 else 756 else
774 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE; 757 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
775 mv_write(PORT_CONFIG_REG(mp->port_num), config_reg); 758 wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
776 759
777 eth_port_set_multicast_list(dev); 760 eth_port_set_multicast_list(dev);
778} 761}
@@ -826,14 +809,14 @@ static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
826{ 809{
827 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, 810 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
828 tx_timeout_task); 811 tx_timeout_task);
829 struct net_device *dev = mp->mii.dev; /* yuck */ 812 struct net_device *dev = mp->dev;
830 813
831 if (!netif_running(dev)) 814 if (!netif_running(dev))
832 return; 815 return;
833 816
834 netif_stop_queue(dev); 817 netif_stop_queue(dev);
835 818
836 eth_port_reset(mp->port_num); 819 eth_port_reset(mp);
837 eth_port_start(dev); 820 eth_port_start(dev);
838 821
839 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) 822 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
@@ -845,7 +828,7 @@ static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
845 * 828 *
846 * If force is non-zero, frees uncompleted descriptors as well 829 * If force is non-zero, frees uncompleted descriptors as well
847 */ 830 */
848int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) 831static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
849{ 832{
850 struct mv643xx_private *mp = netdev_priv(dev); 833 struct mv643xx_private *mp = netdev_priv(dev);
851 struct eth_tx_desc *desc; 834 struct eth_tx_desc *desc;
@@ -1008,7 +991,7 @@ static void mv643xx_eth_update_pscr(struct net_device *dev,
1008 u32 o_pscr, n_pscr; 991 u32 o_pscr, n_pscr;
1009 unsigned int queues; 992 unsigned int queues;
1010 993
1011 o_pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num)); 994 o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
1012 n_pscr = o_pscr; 995 n_pscr = o_pscr;
1013 996
1014 /* clear speed, duplex and rx buffer size fields */ 997 /* clear speed, duplex and rx buffer size fields */
@@ -1031,16 +1014,16 @@ static void mv643xx_eth_update_pscr(struct net_device *dev,
1031 1014
1032 if (n_pscr != o_pscr) { 1015 if (n_pscr != o_pscr) {
1033 if ((o_pscr & SERIAL_PORT_ENABLE) == 0) 1016 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1034 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 1017 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1035 else { 1018 else {
1036 queues = mv643xx_eth_port_disable_tx(port_num); 1019 queues = mv643xx_eth_port_disable_tx(mp);
1037 1020
1038 o_pscr &= ~SERIAL_PORT_ENABLE; 1021 o_pscr &= ~SERIAL_PORT_ENABLE;
1039 mv_write(PORT_SERIAL_CONTROL_REG(port_num), o_pscr); 1022 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
1040 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 1023 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1041 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr); 1024 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1042 if (queues) 1025 if (queues)
1043 mv643xx_eth_port_enable_tx(port_num, queues); 1026 mv643xx_eth_port_enable_tx(mp, queues);
1044 } 1027 }
1045 } 1028 }
1046} 1029}
@@ -1064,13 +1047,13 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1064 unsigned int port_num = mp->port_num; 1047 unsigned int port_num = mp->port_num;
1065 1048
1066 /* Read interrupt cause registers */ 1049 /* Read interrupt cause registers */
1067 eth_int_cause = mv_read(INTERRUPT_CAUSE_REG(port_num)) & 1050 eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
1068 ETH_INT_UNMASK_ALL; 1051 ETH_INT_UNMASK_ALL;
1069 if (eth_int_cause & ETH_INT_CAUSE_EXT) { 1052 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1070 eth_int_cause_ext = mv_read( 1053 eth_int_cause_ext = rdl(mp,
1071 INTERRUPT_CAUSE_EXTEND_REG(port_num)) & 1054 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1072 ETH_INT_UNMASK_ALL_EXT; 1055 ETH_INT_UNMASK_ALL_EXT;
1073 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 1056 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
1074 ~eth_int_cause_ext); 1057 ~eth_int_cause_ext);
1075 } 1058 }
1076 1059
@@ -1081,8 +1064,7 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1081 if (mii_link_ok(&mp->mii)) { 1064 if (mii_link_ok(&mp->mii)) {
1082 mii_ethtool_gset(&mp->mii, &cmd); 1065 mii_ethtool_gset(&mp->mii, &cmd);
1083 mv643xx_eth_update_pscr(dev, &cmd); 1066 mv643xx_eth_update_pscr(dev, &cmd);
1084 mv643xx_eth_port_enable_tx(port_num, 1067 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1085 ETH_TX_QUEUES_ENABLED);
1086 if (!netif_carrier_ok(dev)) { 1068 if (!netif_carrier_ok(dev)) {
1087 netif_carrier_on(dev); 1069 netif_carrier_on(dev);
1088 if (mp->tx_ring_size - mp->tx_desc_count >= 1070 if (mp->tx_ring_size - mp->tx_desc_count >=
@@ -1098,10 +1080,10 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1098#ifdef MV643XX_NAPI 1080#ifdef MV643XX_NAPI
1099 if (eth_int_cause & ETH_INT_CAUSE_RX) { 1081 if (eth_int_cause & ETH_INT_CAUSE_RX) {
1100 /* schedule the NAPI poll routine to maintain port */ 1082 /* schedule the NAPI poll routine to maintain port */
1101 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1083 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1102 1084
1103 /* wait for previous write to complete */ 1085 /* wait for previous write to complete */
1104 mv_read(INTERRUPT_MASK_REG(port_num)); 1086 rdl(mp, INTERRUPT_MASK_REG(port_num));
1105 1087
1106 netif_rx_schedule(dev, &mp->napi); 1088 netif_rx_schedule(dev, &mp->napi);
1107 } 1089 }
@@ -1136,7 +1118,7 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1136 * , and the required delay of the interrupt in usec. 1118 * , and the required delay of the interrupt in usec.
1137 * 1119 *
1138 * INPUT: 1120 * INPUT:
1139 * unsigned int eth_port_num Ethernet port number 1121 * struct mv643xx_private *mp Ethernet port
1140 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units 1122 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1141 * unsigned int delay Delay in usec 1123 * unsigned int delay Delay in usec
1142 * 1124 *
@@ -1147,15 +1129,16 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1147 * The interrupt coalescing value set in the gigE port. 1129 * The interrupt coalescing value set in the gigE port.
1148 * 1130 *
1149 */ 1131 */
1150static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, 1132static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
1151 unsigned int t_clk, unsigned int delay) 1133 unsigned int t_clk, unsigned int delay)
1152{ 1134{
1135 unsigned int port_num = mp->port_num;
1153 unsigned int coal = ((t_clk / 1000000) * delay) / 64; 1136 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
1154 1137
1155 /* Set RX Coalescing mechanism */ 1138 /* Set RX Coalescing mechanism */
1156 mv_write(SDMA_CONFIG_REG(eth_port_num), 1139 wrl(mp, SDMA_CONFIG_REG(port_num),
1157 ((coal & 0x3fff) << 8) | 1140 ((coal & 0x3fff) << 8) |
1158 (mv_read(SDMA_CONFIG_REG(eth_port_num)) 1141 (rdl(mp, SDMA_CONFIG_REG(port_num))
1159 & 0xffc000ff)); 1142 & 0xffc000ff));
1160 1143
1161 return coal; 1144 return coal;
@@ -1174,7 +1157,7 @@ static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
1174 * MV-643xx chip and the required delay in the interrupt in uSec 1157 * MV-643xx chip and the required delay in the interrupt in uSec
1175 * 1158 *
1176 * INPUT: 1159 * INPUT:
1177 * unsigned int eth_port_num Ethernet port number 1160 * struct mv643xx_private *mp Ethernet port
1178 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units 1161 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1179 * unsigned int delay Delay in uSeconds 1162 * unsigned int delay Delay in uSeconds
1180 * 1163 *
@@ -1185,13 +1168,14 @@ static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
1185 * The interrupt coalescing value set in the gigE port. 1168 * The interrupt coalescing value set in the gigE port.
1186 * 1169 *
1187 */ 1170 */
1188static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, 1171static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
1189 unsigned int t_clk, unsigned int delay) 1172 unsigned int t_clk, unsigned int delay)
1190{ 1173{
1191 unsigned int coal; 1174 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
1192 coal = ((t_clk / 1000000) * delay) / 64; 1175
1193 /* Set TX Coalescing mechanism */ 1176 /* Set TX Coalescing mechanism */
1194 mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), coal << 4); 1177 wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4);
1178
1195 return coal; 1179 return coal;
1196} 1180}
1197 1181
@@ -1327,16 +1311,15 @@ static int mv643xx_eth_open(struct net_device *dev)
1327 int err; 1311 int err;
1328 1312
1329 /* Clear any pending ethernet port interrupts */ 1313 /* Clear any pending ethernet port interrupts */
1330 mv_write(INTERRUPT_CAUSE_REG(port_num), 0); 1314 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1331 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 1315 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1332 /* wait for previous write to complete */ 1316 /* wait for previous write to complete */
1333 mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num)); 1317 rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
1334 1318
1335 err = request_irq(dev->irq, mv643xx_eth_int_handler, 1319 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1336 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); 1320 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1337 if (err) { 1321 if (err) {
1338 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n", 1322 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1339 port_num);
1340 return -EAGAIN; 1323 return -EAGAIN;
1341 } 1324 }
1342 1325
@@ -1430,17 +1413,17 @@ static int mv643xx_eth_open(struct net_device *dev)
1430 1413
1431#ifdef MV643XX_COAL 1414#ifdef MV643XX_COAL
1432 mp->rx_int_coal = 1415 mp->rx_int_coal =
1433 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL); 1416 eth_port_set_rx_coal(mp, 133000000, MV643XX_RX_COAL);
1434#endif 1417#endif
1435 1418
1436 mp->tx_int_coal = 1419 mp->tx_int_coal =
1437 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); 1420 eth_port_set_tx_coal(mp, 133000000, MV643XX_TX_COAL);
1438 1421
1439 /* Unmask phy and link status changes interrupts */ 1422 /* Unmask phy and link status changes interrupts */
1440 mv_write(INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); 1423 wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
1441 1424
1442 /* Unmask RX buffer and TX end interrupt */ 1425 /* Unmask RX buffer and TX end interrupt */
1443 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1426 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1444 1427
1445 return 0; 1428 return 0;
1446 1429
@@ -1459,7 +1442,7 @@ static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1459 struct mv643xx_private *mp = netdev_priv(dev); 1442 struct mv643xx_private *mp = netdev_priv(dev);
1460 1443
1461 /* Stop Tx Queues */ 1444 /* Stop Tx Queues */
1462 mv643xx_eth_port_disable_tx(mp->port_num); 1445 mv643xx_eth_port_disable_tx(mp);
1463 1446
1464 /* Free outstanding skb's on TX ring */ 1447 /* Free outstanding skb's on TX ring */
1465 mv643xx_eth_free_all_tx_descs(dev); 1448 mv643xx_eth_free_all_tx_descs(dev);
@@ -1477,11 +1460,10 @@ static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1477static void mv643xx_eth_free_rx_rings(struct net_device *dev) 1460static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1478{ 1461{
1479 struct mv643xx_private *mp = netdev_priv(dev); 1462 struct mv643xx_private *mp = netdev_priv(dev);
1480 unsigned int port_num = mp->port_num;
1481 int curr; 1463 int curr;
1482 1464
1483 /* Stop RX Queues */ 1465 /* Stop RX Queues */
1484 mv643xx_eth_port_disable_rx(port_num); 1466 mv643xx_eth_port_disable_rx(mp);
1485 1467
1486 /* Free preallocated skb's on RX rings */ 1468 /* Free preallocated skb's on RX rings */
1487 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { 1469 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
@@ -1520,9 +1502,9 @@ static int mv643xx_eth_stop(struct net_device *dev)
1520 unsigned int port_num = mp->port_num; 1502 unsigned int port_num = mp->port_num;
1521 1503
1522 /* Mask all interrupts on ethernet port */ 1504 /* Mask all interrupts on ethernet port */
1523 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1505 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1524 /* wait for previous write to complete */ 1506 /* wait for previous write to complete */
1525 mv_read(INTERRUPT_MASK_REG(port_num)); 1507 rdl(mp, INTERRUPT_MASK_REG(port_num));
1526 1508
1527#ifdef MV643XX_NAPI 1509#ifdef MV643XX_NAPI
1528 napi_disable(&mp->napi); 1510 napi_disable(&mp->napi);
@@ -1530,7 +1512,7 @@ static int mv643xx_eth_stop(struct net_device *dev)
1530 netif_carrier_off(dev); 1512 netif_carrier_off(dev);
1531 netif_stop_queue(dev); 1513 netif_stop_queue(dev);
1532 1514
1533 eth_port_reset(mp->port_num); 1515 eth_port_reset(mp);
1534 1516
1535 mv643xx_eth_free_tx_rings(dev); 1517 mv643xx_eth_free_tx_rings(dev);
1536 mv643xx_eth_free_rx_rings(dev); 1518 mv643xx_eth_free_rx_rings(dev);
@@ -1561,15 +1543,15 @@ static int mv643xx_poll(struct napi_struct *napi, int budget)
1561#endif 1543#endif
1562 1544
1563 work_done = 0; 1545 work_done = 0;
1564 if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) 1546 if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1565 != (u32) mp->rx_used_desc_q) 1547 != (u32) mp->rx_used_desc_q)
1566 work_done = mv643xx_eth_receive_queue(dev, budget); 1548 work_done = mv643xx_eth_receive_queue(dev, budget);
1567 1549
1568 if (work_done < budget) { 1550 if (work_done < budget) {
1569 netif_rx_complete(dev, napi); 1551 netif_rx_complete(dev, napi);
1570 mv_write(INTERRUPT_CAUSE_REG(port_num), 0); 1552 wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
1571 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 1553 wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1572 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1554 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1573 } 1555 }
1574 1556
1575 return work_done; 1557 return work_done;
@@ -1723,7 +1705,7 @@ static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1723 1705
1724 /* ensure all descriptors are written before poking hardware */ 1706 /* ensure all descriptors are written before poking hardware */
1725 wmb(); 1707 wmb();
1726 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED); 1708 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1727 1709
1728 mp->tx_desc_count += nr_frags + 1; 1710 mp->tx_desc_count += nr_frags + 1;
1729} 1711}
@@ -1739,25 +1721,23 @@ static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1739 unsigned long flags; 1721 unsigned long flags;
1740 1722
1741 BUG_ON(netif_queue_stopped(dev)); 1723 BUG_ON(netif_queue_stopped(dev));
1742 BUG_ON(skb == NULL); 1724
1725 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1726 stats->tx_dropped++;
1727 printk(KERN_DEBUG "%s: failed to linearize tiny "
1728 "unaligned fragment\n", dev->name);
1729 return NETDEV_TX_BUSY;
1730 }
1731
1732 spin_lock_irqsave(&mp->lock, flags);
1743 1733
1744 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { 1734 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1745 printk(KERN_ERR "%s: transmit with queue full\n", dev->name); 1735 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1746 netif_stop_queue(dev); 1736 netif_stop_queue(dev);
1747 return 1; 1737 spin_unlock_irqrestore(&mp->lock, flags);
1748 } 1738 return NETDEV_TX_BUSY;
1749
1750 if (has_tiny_unaligned_frags(skb)) {
1751 if (__skb_linearize(skb)) {
1752 stats->tx_dropped++;
1753 printk(KERN_DEBUG "%s: failed to linearize tiny "
1754 "unaligned fragment\n", dev->name);
1755 return 1;
1756 }
1757 } 1739 }
1758 1740
1759 spin_lock_irqsave(&mp->lock, flags);
1760
1761 eth_tx_submit_descs_for_skb(mp, skb); 1741 eth_tx_submit_descs_for_skb(mp, skb);
1762 stats->tx_bytes += skb->len; 1742 stats->tx_bytes += skb->len;
1763 stats->tx_packets++; 1743 stats->tx_packets++;
@@ -1768,7 +1748,7 @@ static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1768 1748
1769 spin_unlock_irqrestore(&mp->lock, flags); 1749 spin_unlock_irqrestore(&mp->lock, flags);
1770 1750
1771 return 0; /* success */ 1751 return NETDEV_TX_OK;
1772} 1752}
1773 1753
1774#ifdef CONFIG_NET_POLL_CONTROLLER 1754#ifdef CONFIG_NET_POLL_CONTROLLER
@@ -1777,13 +1757,13 @@ static void mv643xx_netpoll(struct net_device *netdev)
1777 struct mv643xx_private *mp = netdev_priv(netdev); 1757 struct mv643xx_private *mp = netdev_priv(netdev);
1778 int port_num = mp->port_num; 1758 int port_num = mp->port_num;
1779 1759
1780 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); 1760 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1781 /* wait for previous write to complete */ 1761 /* wait for previous write to complete */
1782 mv_read(INTERRUPT_MASK_REG(port_num)); 1762 rdl(mp, INTERRUPT_MASK_REG(port_num));
1783 1763
1784 mv643xx_eth_int_handler(netdev->irq, netdev); 1764 mv643xx_eth_int_handler(netdev->irq, netdev);
1785 1765
1786 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); 1766 wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1787} 1767}
1788#endif 1768#endif
1789 1769
@@ -1900,7 +1880,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
1900 port_num = mp->port_num = pd->port_number; 1880 port_num = mp->port_num = pd->port_number;
1901 1881
1902 /* set default config values */ 1882 /* set default config values */
1903 eth_port_uc_addr_get(port_num, dev->dev_addr); 1883 eth_port_uc_addr_get(mp, dev->dev_addr);
1904 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; 1884 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1905 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; 1885 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1906 1886
@@ -1908,7 +1888,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
1908 memcpy(dev->dev_addr, pd->mac_addr, 6); 1888 memcpy(dev->dev_addr, pd->mac_addr, 6);
1909 1889
1910 if (pd->phy_addr || pd->force_phy_addr) 1890 if (pd->phy_addr || pd->force_phy_addr)
1911 ethernet_phy_set(port_num, pd->phy_addr); 1891 ethernet_phy_set(mp, pd->phy_addr);
1912 1892
1913 if (pd->rx_queue_size) 1893 if (pd->rx_queue_size)
1914 mp->rx_ring_size = pd->rx_queue_size; 1894 mp->rx_ring_size = pd->rx_queue_size;
@@ -1933,19 +1913,18 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
1933 mp->mii.dev = dev; 1913 mp->mii.dev = dev;
1934 mp->mii.mdio_read = mv643xx_mdio_read; 1914 mp->mii.mdio_read = mv643xx_mdio_read;
1935 mp->mii.mdio_write = mv643xx_mdio_write; 1915 mp->mii.mdio_write = mv643xx_mdio_write;
1936 mp->mii.phy_id = ethernet_phy_get(port_num); 1916 mp->mii.phy_id = ethernet_phy_get(mp);
1937 mp->mii.phy_id_mask = 0x3f; 1917 mp->mii.phy_id_mask = 0x3f;
1938 mp->mii.reg_num_mask = 0x1f; 1918 mp->mii.reg_num_mask = 0x1f;
1939 1919
1940 err = ethernet_phy_detect(port_num); 1920 err = ethernet_phy_detect(mp);
1941 if (err) { 1921 if (err) {
1942 pr_debug("MV643xx ethernet port %d: " 1922 pr_debug("%s: No PHY detected at addr %d\n",
1943 "No PHY detected at addr %d\n", 1923 dev->name, ethernet_phy_get(mp));
1944 port_num, ethernet_phy_get(port_num));
1945 goto out; 1924 goto out;
1946 } 1925 }
1947 1926
1948 ethernet_phy_reset(port_num); 1927 ethernet_phy_reset(mp);
1949 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); 1928 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1950 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); 1929 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1951 mv643xx_eth_update_pscr(dev, &cmd); 1930 mv643xx_eth_update_pscr(dev, &cmd);
@@ -2006,9 +1985,11 @@ static int mv643xx_eth_remove(struct platform_device *pdev)
2006 1985
2007static int mv643xx_eth_shared_probe(struct platform_device *pdev) 1986static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2008{ 1987{
1988 static int mv643xx_version_printed = 0;
2009 struct resource *res; 1989 struct resource *res;
2010 1990
2011 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); 1991 if (!mv643xx_version_printed++)
1992 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2012 1993
2013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1994 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2014 if (res == NULL) 1995 if (res == NULL)
@@ -2037,10 +2018,10 @@ static void mv643xx_eth_shutdown(struct platform_device *pdev)
2037 unsigned int port_num = mp->port_num; 2018 unsigned int port_num = mp->port_num;
2038 2019
2039 /* Mask all interrupts on ethernet port */ 2020 /* Mask all interrupts on ethernet port */
2040 mv_write(INTERRUPT_MASK_REG(port_num), 0); 2021 wrl(mp, INTERRUPT_MASK_REG(port_num), 0);
2041 mv_read (INTERRUPT_MASK_REG(port_num)); 2022 rdl(mp, INTERRUPT_MASK_REG(port_num));
2042 2023
2043 eth_port_reset(port_num); 2024 eth_port_reset(mp);
2044} 2025}
2045 2026
2046static struct platform_driver mv643xx_eth_driver = { 2027static struct platform_driver mv643xx_eth_driver = {
@@ -2229,12 +2210,9 @@ MODULE_ALIAS("platform:mv643xx_eth");
2229 * return_info Tx/Rx user resource return information. 2210 * return_info Tx/Rx user resource return information.
2230 */ 2211 */
2231 2212
2232/* PHY routines */
2233static int ethernet_phy_get(unsigned int eth_port_num);
2234static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
2235
2236/* Ethernet Port routines */ 2213/* Ethernet Port routines */
2237static void eth_port_set_filter_table_entry(int table, unsigned char entry); 2214static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2215 int table, unsigned char entry);
2238 2216
2239/* 2217/*
2240 * eth_port_init - Initialize the Ethernet port driver 2218 * eth_port_init - Initialize the Ethernet port driver
@@ -2264,9 +2242,9 @@ static void eth_port_init(struct mv643xx_private *mp)
2264{ 2242{
2265 mp->rx_resource_err = 0; 2243 mp->rx_resource_err = 0;
2266 2244
2267 eth_port_reset(mp->port_num); 2245 eth_port_reset(mp);
2268 2246
2269 eth_port_init_mac_tables(mp->port_num); 2247 eth_port_init_mac_tables(mp);
2270} 2248}
2271 2249
2272/* 2250/*
@@ -2306,28 +2284,28 @@ static void eth_port_start(struct net_device *dev)
2306 2284
2307 /* Assignment of Tx CTRP of given queue */ 2285 /* Assignment of Tx CTRP of given queue */
2308 tx_curr_desc = mp->tx_curr_desc_q; 2286 tx_curr_desc = mp->tx_curr_desc_q;
2309 mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num), 2287 wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2310 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); 2288 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2311 2289
2312 /* Assignment of Rx CRDP of given queue */ 2290 /* Assignment of Rx CRDP of given queue */
2313 rx_curr_desc = mp->rx_curr_desc_q; 2291 rx_curr_desc = mp->rx_curr_desc_q;
2314 mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num), 2292 wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2315 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); 2293 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2316 2294
2317 /* Add the assigned Ethernet address to the port's address table */ 2295 /* Add the assigned Ethernet address to the port's address table */
2318 eth_port_uc_addr_set(port_num, dev->dev_addr); 2296 eth_port_uc_addr_set(mp, dev->dev_addr);
2319 2297
2320 /* Assign port configuration and command. */ 2298 /* Assign port configuration and command. */
2321 mv_write(PORT_CONFIG_REG(port_num), 2299 wrl(mp, PORT_CONFIG_REG(port_num),
2322 PORT_CONFIG_DEFAULT_VALUE); 2300 PORT_CONFIG_DEFAULT_VALUE);
2323 2301
2324 mv_write(PORT_CONFIG_EXTEND_REG(port_num), 2302 wrl(mp, PORT_CONFIG_EXTEND_REG(port_num),
2325 PORT_CONFIG_EXTEND_DEFAULT_VALUE); 2303 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2326 2304
2327 pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num)); 2305 pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
2328 2306
2329 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); 2307 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2330 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr); 2308 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
2331 2309
2332 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 2310 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2333 DISABLE_AUTO_NEG_SPEED_GMII | 2311 DISABLE_AUTO_NEG_SPEED_GMII |
@@ -2335,32 +2313,34 @@ static void eth_port_start(struct net_device *dev)
2335 DO_NOT_FORCE_LINK_FAIL | 2313 DO_NOT_FORCE_LINK_FAIL |
2336 SERIAL_PORT_CONTROL_RESERVED; 2314 SERIAL_PORT_CONTROL_RESERVED;
2337 2315
2338 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr); 2316 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
2339 2317
2340 pscr |= SERIAL_PORT_ENABLE; 2318 pscr |= SERIAL_PORT_ENABLE;
2341 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr); 2319 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
2342 2320
2343 /* Assign port SDMA configuration */ 2321 /* Assign port SDMA configuration */
2344 mv_write(SDMA_CONFIG_REG(port_num), 2322 wrl(mp, SDMA_CONFIG_REG(port_num),
2345 PORT_SDMA_CONFIG_DEFAULT_VALUE); 2323 PORT_SDMA_CONFIG_DEFAULT_VALUE);
2346 2324
2347 /* Enable port Rx. */ 2325 /* Enable port Rx. */
2348 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED); 2326 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED);
2349 2327
2350 /* Disable port bandwidth limits by clearing MTU register */ 2328 /* Disable port bandwidth limits by clearing MTU register */
2351 mv_write(MAXIMUM_TRANSMIT_UNIT(port_num), 0); 2329 wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0);
2352 2330
2353 /* save phy settings across reset */ 2331 /* save phy settings across reset */
2354 mv643xx_get_settings(dev, &ethtool_cmd); 2332 mv643xx_get_settings(dev, &ethtool_cmd);
2355 ethernet_phy_reset(mp->port_num); 2333 ethernet_phy_reset(mp);
2356 mv643xx_set_settings(dev, &ethtool_cmd); 2334 mv643xx_set_settings(dev, &ethtool_cmd);
2357} 2335}
2358 2336
2359/* 2337/*
2360 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers 2338 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
2361 */ 2339 */
2362static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr) 2340static void eth_port_uc_addr_set(struct mv643xx_private *mp,
2341 unsigned char *p_addr)
2363{ 2342{
2343 unsigned int port_num = mp->port_num;
2364 unsigned int mac_h; 2344 unsigned int mac_h;
2365 unsigned int mac_l; 2345 unsigned int mac_l;
2366 int table; 2346 int table;
@@ -2369,24 +2349,26 @@ static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
2369 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 2349 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
2370 (p_addr[3] << 0); 2350 (p_addr[3] << 0);
2371 2351
2372 mv_write(MAC_ADDR_LOW(port_num), mac_l); 2352 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
2373 mv_write(MAC_ADDR_HIGH(port_num), mac_h); 2353 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
2374 2354
2375 /* Accept frames with this address */ 2355 /* Accept frames with this address */
2376 table = DA_FILTER_UNICAST_TABLE_BASE(port_num); 2356 table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
2377 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f); 2357 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
2378} 2358}
2379 2359
2380/* 2360/*
2381 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers 2361 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
2382 */ 2362 */
2383static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr) 2363static void eth_port_uc_addr_get(struct mv643xx_private *mp,
2364 unsigned char *p_addr)
2384{ 2365{
2366 unsigned int port_num = mp->port_num;
2385 unsigned int mac_h; 2367 unsigned int mac_h;
2386 unsigned int mac_l; 2368 unsigned int mac_l;
2387 2369
2388 mac_h = mv_read(MAC_ADDR_HIGH(port_num)); 2370 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
2389 mac_l = mv_read(MAC_ADDR_LOW(port_num)); 2371 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
2390 2372
2391 p_addr[0] = (mac_h >> 24) & 0xff; 2373 p_addr[0] = (mac_h >> 24) & 0xff;
2392 p_addr[1] = (mac_h >> 16) & 0xff; 2374 p_addr[1] = (mac_h >> 16) & 0xff;
@@ -2405,7 +2387,8 @@ static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
2405 * 3-1 Queue (ETH_Q0=0) 2387 * 3-1 Queue (ETH_Q0=0)
2406 * 7-4 Reserved = 0; 2388 * 7-4 Reserved = 0;
2407 */ 2389 */
2408static void eth_port_set_filter_table_entry(int table, unsigned char entry) 2390static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
2391 int table, unsigned char entry)
2409{ 2392{
2410 unsigned int table_reg; 2393 unsigned int table_reg;
2411 unsigned int tbl_offset; 2394 unsigned int tbl_offset;
@@ -2415,9 +2398,9 @@ static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2415 reg_offset = entry % 4; /* Entry offset within the register */ 2398 reg_offset = entry % 4; /* Entry offset within the register */
2416 2399
2417 /* Set "accepts frame bit" at specified table entry */ 2400 /* Set "accepts frame bit" at specified table entry */
2418 table_reg = mv_read(table + tbl_offset); 2401 table_reg = rdl(mp, table + tbl_offset);
2419 table_reg |= 0x01 << (8 * reg_offset); 2402 table_reg |= 0x01 << (8 * reg_offset);
2420 mv_write(table + tbl_offset, table_reg); 2403 wrl(mp, table + tbl_offset, table_reg);
2421} 2404}
2422 2405
2423/* 2406/*
@@ -2434,8 +2417,9 @@ static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2434 * In either case, eth_port_set_filter_table_entry() is then called 2417 * In either case, eth_port_set_filter_table_entry() is then called
2435 * to set to set the actual table entry. 2418 * to set to set the actual table entry.
2436 */ 2419 */
2437static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) 2420static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
2438{ 2421{
2422 unsigned int port_num = mp->port_num;
2439 unsigned int mac_h; 2423 unsigned int mac_h;
2440 unsigned int mac_l; 2424 unsigned int mac_l;
2441 unsigned char crc_result = 0; 2425 unsigned char crc_result = 0;
@@ -2446,9 +2430,8 @@ static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2446 2430
2447 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && 2431 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2448 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { 2432 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2449 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE 2433 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num);
2450 (eth_port_num); 2434 eth_port_set_filter_table_entry(mp, table, p_addr[5]);
2451 eth_port_set_filter_table_entry(table, p_addr[5]);
2452 return; 2435 return;
2453 } 2436 }
2454 2437
@@ -2520,8 +2503,8 @@ static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2520 for (i = 0; i < 8; i++) 2503 for (i = 0; i < 8; i++)
2521 crc_result = crc_result | (crc[i] << i); 2504 crc_result = crc_result | (crc[i] << i);
2522 2505
2523 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); 2506 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num);
2524 eth_port_set_filter_table_entry(table, crc_result); 2507 eth_port_set_filter_table_entry(mp, table, crc_result);
2525} 2508}
2526 2509
2527/* 2510/*
@@ -2550,7 +2533,7 @@ static void eth_port_set_multicast_list(struct net_device *dev)
2550 * 3-1 Queue ETH_Q0=0 2533 * 3-1 Queue ETH_Q0=0
2551 * 7-4 Reserved = 0; 2534 * 7-4 Reserved = 0;
2552 */ 2535 */
2553 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); 2536 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2554 2537
2555 /* Set all entries in DA filter other multicast 2538 /* Set all entries in DA filter other multicast
2556 * table (Ex_dFOMT) 2539 * table (Ex_dFOMT)
@@ -2560,7 +2543,7 @@ static void eth_port_set_multicast_list(struct net_device *dev)
2560 * 3-1 Queue ETH_Q0=0 2543 * 3-1 Queue ETH_Q0=0
2561 * 7-4 Reserved = 0; 2544 * 7-4 Reserved = 0;
2562 */ 2545 */
2563 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); 2546 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2564 } 2547 }
2565 return; 2548 return;
2566 } 2549 }
@@ -2570,11 +2553,11 @@ static void eth_port_set_multicast_list(struct net_device *dev)
2570 */ 2553 */
2571 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 2554 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2572 /* Clear DA filter special multicast table (Ex_dFSMT) */ 2555 /* Clear DA filter special multicast table (Ex_dFSMT) */
2573 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE 2556 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2574 (eth_port_num) + table_index, 0); 2557 (eth_port_num) + table_index, 0);
2575 2558
2576 /* Clear DA filter other multicast table (Ex_dFOMT) */ 2559 /* Clear DA filter other multicast table (Ex_dFOMT) */
2577 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE 2560 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2578 (eth_port_num) + table_index, 0); 2561 (eth_port_num) + table_index, 0);
2579 } 2562 }
2580 2563
@@ -2583,7 +2566,7 @@ static void eth_port_set_multicast_list(struct net_device *dev)
2583 (i < 256) && (mc_list != NULL) && (i < dev->mc_count); 2566 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2584 i++, mc_list = mc_list->next) 2567 i++, mc_list = mc_list->next)
2585 if (mc_list->dmi_addrlen == 6) 2568 if (mc_list->dmi_addrlen == 6)
2586 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr); 2569 eth_port_mc_addr(mp, mc_list->dmi_addr);
2587} 2570}
2588 2571
2589/* 2572/*
@@ -2594,7 +2577,7 @@ static void eth_port_set_multicast_list(struct net_device *dev)
2594 * Other Multicast) and set each entry to 0. 2577 * Other Multicast) and set each entry to 0.
2595 * 2578 *
2596 * INPUT: 2579 * INPUT:
2597 * unsigned int eth_port_num Ethernet Port number. 2580 * struct mv643xx_private *mp Ethernet Port.
2598 * 2581 *
2599 * OUTPUT: 2582 * OUTPUT:
2600 * Multicast and Unicast packets are rejected. 2583 * Multicast and Unicast packets are rejected.
@@ -2602,22 +2585,23 @@ static void eth_port_set_multicast_list(struct net_device *dev)
2602 * RETURN: 2585 * RETURN:
2603 * None. 2586 * None.
2604 */ 2587 */
2605static void eth_port_init_mac_tables(unsigned int eth_port_num) 2588static void eth_port_init_mac_tables(struct mv643xx_private *mp)
2606{ 2589{
2590 unsigned int port_num = mp->port_num;
2607 int table_index; 2591 int table_index;
2608 2592
2609 /* Clear DA filter unicast table (Ex_dFUT) */ 2593 /* Clear DA filter unicast table (Ex_dFUT) */
2610 for (table_index = 0; table_index <= 0xC; table_index += 4) 2594 for (table_index = 0; table_index <= 0xC; table_index += 4)
2611 mv_write(DA_FILTER_UNICAST_TABLE_BASE 2595 wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
2612 (eth_port_num) + table_index, 0); 2596 table_index, 0);
2613 2597
2614 for (table_index = 0; table_index <= 0xFC; table_index += 4) { 2598 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2615 /* Clear DA filter special multicast table (Ex_dFSMT) */ 2599 /* Clear DA filter special multicast table (Ex_dFSMT) */
2616 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE 2600 wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
2617 (eth_port_num) + table_index, 0); 2601 table_index, 0);
2618 /* Clear DA filter other multicast table (Ex_dFOMT) */ 2602 /* Clear DA filter other multicast table (Ex_dFOMT) */
2619 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE 2603 wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
2620 (eth_port_num) + table_index, 0); 2604 table_index, 0);
2621 } 2605 }
2622} 2606}
2623 2607
@@ -2629,7 +2613,7 @@ static void eth_port_init_mac_tables(unsigned int eth_port_num)
2629 * A read from the MIB counter will reset the counter. 2613 * A read from the MIB counter will reset the counter.
2630 * 2614 *
2631 * INPUT: 2615 * INPUT:
2632 * unsigned int eth_port_num Ethernet Port number. 2616 * struct mv643xx_private *mp Ethernet Port.
2633 * 2617 *
2634 * OUTPUT: 2618 * OUTPUT:
2635 * After reading all MIB counters, the counters resets. 2619 * After reading all MIB counters, the counters resets.
@@ -2638,19 +2622,20 @@ static void eth_port_init_mac_tables(unsigned int eth_port_num)
2638 * MIB counter value. 2622 * MIB counter value.
2639 * 2623 *
2640 */ 2624 */
2641static void eth_clear_mib_counters(unsigned int eth_port_num) 2625static void eth_clear_mib_counters(struct mv643xx_private *mp)
2642{ 2626{
2627 unsigned int port_num = mp->port_num;
2643 int i; 2628 int i;
2644 2629
2645 /* Perform dummy reads from MIB counters */ 2630 /* Perform dummy reads from MIB counters */
2646 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; 2631 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2647 i += 4) 2632 i += 4)
2648 mv_read(MIB_COUNTERS_BASE(eth_port_num) + i); 2633 rdl(mp, MIB_COUNTERS_BASE(port_num) + i);
2649} 2634}
2650 2635
2651static inline u32 read_mib(struct mv643xx_private *mp, int offset) 2636static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2652{ 2637{
2653 return mv_read(MIB_COUNTERS_BASE(mp->port_num) + offset); 2638 return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset);
2654} 2639}
2655 2640
2656static void eth_update_mib_counters(struct mv643xx_private *mp) 2641static void eth_update_mib_counters(struct mv643xx_private *mp)
@@ -2686,7 +2671,7 @@ static void eth_update_mib_counters(struct mv643xx_private *mp)
2686 * the specified port. 2671 * the specified port.
2687 * 2672 *
2688 * INPUT: 2673 * INPUT:
2689 * unsigned int eth_port_num Ethernet Port number. 2674 * struct mv643xx_private *mp Ethernet Port.
2690 * 2675 *
2691 * OUTPUT: 2676 * OUTPUT:
2692 * None 2677 * None
@@ -2696,22 +2681,22 @@ static void eth_update_mib_counters(struct mv643xx_private *mp)
2696 * -ENODEV on failure 2681 * -ENODEV on failure
2697 * 2682 *
2698 */ 2683 */
2699static int ethernet_phy_detect(unsigned int port_num) 2684static int ethernet_phy_detect(struct mv643xx_private *mp)
2700{ 2685{
2701 unsigned int phy_reg_data0; 2686 unsigned int phy_reg_data0;
2702 int auto_neg; 2687 int auto_neg;
2703 2688
2704 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); 2689 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2705 auto_neg = phy_reg_data0 & 0x1000; 2690 auto_neg = phy_reg_data0 & 0x1000;
2706 phy_reg_data0 ^= 0x1000; /* invert auto_neg */ 2691 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2707 eth_port_write_smi_reg(port_num, 0, phy_reg_data0); 2692 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2708 2693
2709 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); 2694 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2710 if ((phy_reg_data0 & 0x1000) == auto_neg) 2695 if ((phy_reg_data0 & 0x1000) == auto_neg)
2711 return -ENODEV; /* change didn't take */ 2696 return -ENODEV; /* change didn't take */
2712 2697
2713 phy_reg_data0 ^= 0x1000; 2698 phy_reg_data0 ^= 0x1000;
2714 eth_port_write_smi_reg(port_num, 0, phy_reg_data0); 2699 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2715 return 0; 2700 return 0;
2716} 2701}
2717 2702
@@ -2722,7 +2707,7 @@ static int ethernet_phy_detect(unsigned int port_num)
2722 * This routine returns the given ethernet port PHY address. 2707 * This routine returns the given ethernet port PHY address.
2723 * 2708 *
2724 * INPUT: 2709 * INPUT:
2725 * unsigned int eth_port_num Ethernet Port number. 2710 * struct mv643xx_private *mp Ethernet Port.
2726 * 2711 *
2727 * OUTPUT: 2712 * OUTPUT:
2728 * None. 2713 * None.
@@ -2731,13 +2716,13 @@ static int ethernet_phy_detect(unsigned int port_num)
2731 * PHY address. 2716 * PHY address.
2732 * 2717 *
2733 */ 2718 */
2734static int ethernet_phy_get(unsigned int eth_port_num) 2719static int ethernet_phy_get(struct mv643xx_private *mp)
2735{ 2720{
2736 unsigned int reg_data; 2721 unsigned int reg_data;
2737 2722
2738 reg_data = mv_read(PHY_ADDR_REG); 2723 reg_data = rdl(mp, PHY_ADDR_REG);
2739 2724
2740 return ((reg_data >> (5 * eth_port_num)) & 0x1f); 2725 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2741} 2726}
2742 2727
2743/* 2728/*
@@ -2747,7 +2732,7 @@ static int ethernet_phy_get(unsigned int eth_port_num)
2747 * This routine sets the given ethernet port PHY address. 2732 * This routine sets the given ethernet port PHY address.
2748 * 2733 *
2749 * INPUT: 2734 * INPUT:
2750 * unsigned int eth_port_num Ethernet Port number. 2735 * struct mv643xx_private *mp Ethernet Port.
2751 * int phy_addr PHY address. 2736 * int phy_addr PHY address.
2752 * 2737 *
2753 * OUTPUT: 2738 * OUTPUT:
@@ -2757,15 +2742,15 @@ static int ethernet_phy_get(unsigned int eth_port_num)
2757 * None. 2742 * None.
2758 * 2743 *
2759 */ 2744 */
2760static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) 2745static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2761{ 2746{
2762 u32 reg_data; 2747 u32 reg_data;
2763 int addr_shift = 5 * eth_port_num; 2748 int addr_shift = 5 * mp->port_num;
2764 2749
2765 reg_data = mv_read(PHY_ADDR_REG); 2750 reg_data = rdl(mp, PHY_ADDR_REG);
2766 reg_data &= ~(0x1f << addr_shift); 2751 reg_data &= ~(0x1f << addr_shift);
2767 reg_data |= (phy_addr & 0x1f) << addr_shift; 2752 reg_data |= (phy_addr & 0x1f) << addr_shift;
2768 mv_write(PHY_ADDR_REG, reg_data); 2753 wrl(mp, PHY_ADDR_REG, reg_data);
2769} 2754}
2770 2755
2771/* 2756/*
@@ -2775,7 +2760,7 @@ static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2775 * This routine utilizes the SMI interface to reset the ethernet port PHY. 2760 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2776 * 2761 *
2777 * INPUT: 2762 * INPUT:
2778 * unsigned int eth_port_num Ethernet Port number. 2763 * struct mv643xx_private *mp Ethernet Port.
2779 * 2764 *
2780 * OUTPUT: 2765 * OUTPUT:
2781 * The PHY is reset. 2766 * The PHY is reset.
@@ -2784,51 +2769,52 @@ static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2784 * None. 2769 * None.
2785 * 2770 *
2786 */ 2771 */
2787static void ethernet_phy_reset(unsigned int eth_port_num) 2772static void ethernet_phy_reset(struct mv643xx_private *mp)
2788{ 2773{
2789 unsigned int phy_reg_data; 2774 unsigned int phy_reg_data;
2790 2775
2791 /* Reset the PHY */ 2776 /* Reset the PHY */
2792 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); 2777 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2793 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ 2778 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2794 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data); 2779 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2795 2780
2796 /* wait for PHY to come out of reset */ 2781 /* wait for PHY to come out of reset */
2797 do { 2782 do {
2798 udelay(1); 2783 udelay(1);
2799 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); 2784 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2800 } while (phy_reg_data & 0x8000); 2785 } while (phy_reg_data & 0x8000);
2801} 2786}
2802 2787
2803static void mv643xx_eth_port_enable_tx(unsigned int port_num, 2788static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
2804 unsigned int queues) 2789 unsigned int queues)
2805{ 2790{
2806 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), queues); 2791 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues);
2807} 2792}
2808 2793
2809static void mv643xx_eth_port_enable_rx(unsigned int port_num, 2794static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
2810 unsigned int queues) 2795 unsigned int queues)
2811{ 2796{
2812 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), queues); 2797 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
2813} 2798}
2814 2799
2815static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num) 2800static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
2816{ 2801{
2802 unsigned int port_num = mp->port_num;
2817 u32 queues; 2803 u32 queues;
2818 2804
2819 /* Stop Tx port activity. Check port Tx activity. */ 2805 /* Stop Tx port activity. Check port Tx activity. */
2820 queues = mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2806 queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2821 if (queues) { 2807 if (queues) {
2822 /* Issue stop command for active queues only */ 2808 /* Issue stop command for active queues only */
2823 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2809 wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
2824 2810
2825 /* Wait for all Tx activity to terminate. */ 2811 /* Wait for all Tx activity to terminate. */
2826 /* Check port cause register that all Tx queues are stopped */ 2812 /* Check port cause register that all Tx queues are stopped */
2827 while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF) 2813 while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2828 udelay(PHY_WAIT_MICRO_SECONDS); 2814 udelay(PHY_WAIT_MICRO_SECONDS);
2829 2815
2830 /* Wait for Tx FIFO to empty */ 2816 /* Wait for Tx FIFO to empty */
2831 while (mv_read(PORT_STATUS_REG(port_num)) & 2817 while (rdl(mp, PORT_STATUS_REG(port_num)) &
2832 ETH_PORT_TX_FIFO_EMPTY) 2818 ETH_PORT_TX_FIFO_EMPTY)
2833 udelay(PHY_WAIT_MICRO_SECONDS); 2819 udelay(PHY_WAIT_MICRO_SECONDS);
2834 } 2820 }
@@ -2836,19 +2822,20 @@ static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2836 return queues; 2822 return queues;
2837} 2823}
2838 2824
2839static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num) 2825static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
2840{ 2826{
2827 unsigned int port_num = mp->port_num;
2841 u32 queues; 2828 u32 queues;
2842 2829
2843 /* Stop Rx port activity. Check port Rx activity. */ 2830 /* Stop Rx port activity. Check port Rx activity. */
2844 queues = mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; 2831 queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2845 if (queues) { 2832 if (queues) {
2846 /* Issue stop command for active queues only */ 2833 /* Issue stop command for active queues only */
2847 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); 2834 wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
2848 2835
2849 /* Wait for all Rx activity to terminate. */ 2836 /* Wait for all Rx activity to terminate. */
2850 /* Check port cause register that all Rx queues are stopped */ 2837 /* Check port cause register that all Rx queues are stopped */
2851 while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF) 2838 while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2852 udelay(PHY_WAIT_MICRO_SECONDS); 2839 udelay(PHY_WAIT_MICRO_SECONDS);
2853 } 2840 }
2854 2841
@@ -2864,7 +2851,7 @@ static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2864 * idle state after this command is performed and the port is disabled. 2851 * idle state after this command is performed and the port is disabled.
2865 * 2852 *
2866 * INPUT: 2853 * INPUT:
2867 * unsigned int eth_port_num Ethernet Port number. 2854 * struct mv643xx_private *mp Ethernet Port.
2868 * 2855 *
2869 * OUTPUT: 2856 * OUTPUT:
2870 * Channel activity is halted. 2857 * Channel activity is halted.
@@ -2873,22 +2860,23 @@ static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2873 * None. 2860 * None.
2874 * 2861 *
2875 */ 2862 */
2876static void eth_port_reset(unsigned int port_num) 2863static void eth_port_reset(struct mv643xx_private *mp)
2877{ 2864{
2865 unsigned int port_num = mp->port_num;
2878 unsigned int reg_data; 2866 unsigned int reg_data;
2879 2867
2880 mv643xx_eth_port_disable_tx(port_num); 2868 mv643xx_eth_port_disable_tx(mp);
2881 mv643xx_eth_port_disable_rx(port_num); 2869 mv643xx_eth_port_disable_rx(mp);
2882 2870
2883 /* Clear all MIB counters */ 2871 /* Clear all MIB counters */
2884 eth_clear_mib_counters(port_num); 2872 eth_clear_mib_counters(mp);
2885 2873
2886 /* Reset the Enable bit in the Configuration Register */ 2874 /* Reset the Enable bit in the Configuration Register */
2887 reg_data = mv_read(PORT_SERIAL_CONTROL_REG(port_num)); 2875 reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
2888 reg_data &= ~(SERIAL_PORT_ENABLE | 2876 reg_data &= ~(SERIAL_PORT_ENABLE |
2889 DO_NOT_FORCE_LINK_FAIL | 2877 DO_NOT_FORCE_LINK_FAIL |
2890 FORCE_LINK_PASS); 2878 FORCE_LINK_PASS);
2891 mv_write(PORT_SERIAL_CONTROL_REG(port_num), reg_data); 2879 wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2892} 2880}
2893 2881
2894 2882
@@ -2900,7 +2888,7 @@ static void eth_port_reset(unsigned int port_num)
2900 * order to perform PHY register read. 2888 * order to perform PHY register read.
2901 * 2889 *
2902 * INPUT: 2890 * INPUT:
2903 * unsigned int port_num Ethernet Port number. 2891 * struct mv643xx_private *mp Ethernet Port.
2904 * unsigned int phy_reg PHY register address offset. 2892 * unsigned int phy_reg PHY register address offset.
2905 * unsigned int *value Register value buffer. 2893 * unsigned int *value Register value buffer.
2906 * 2894 *
@@ -2912,10 +2900,10 @@ static void eth_port_reset(unsigned int port_num)
2912 * true otherwise. 2900 * true otherwise.
2913 * 2901 *
2914 */ 2902 */
2915static void eth_port_read_smi_reg(unsigned int port_num, 2903static void eth_port_read_smi_reg(struct mv643xx_private *mp,
2916 unsigned int phy_reg, unsigned int *value) 2904 unsigned int phy_reg, unsigned int *value)
2917{ 2905{
2918 int phy_addr = ethernet_phy_get(port_num); 2906 int phy_addr = ethernet_phy_get(mp);
2919 unsigned long flags; 2907 unsigned long flags;
2920 int i; 2908 int i;
2921 2909
@@ -2923,27 +2911,27 @@ static void eth_port_read_smi_reg(unsigned int port_num,
2923 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); 2911 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2924 2912
2925 /* wait for the SMI register to become available */ 2913 /* wait for the SMI register to become available */
2926 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) { 2914 for (i = 0; rdl(mp, SMI_REG) & ETH_SMI_BUSY; i++) {
2927 if (i == PHY_WAIT_ITERATIONS) { 2915 if (i == PHY_WAIT_ITERATIONS) {
2928 printk("mv643xx PHY busy timeout, port %d\n", port_num); 2916 printk("%s: PHY busy timeout\n", mp->dev->name);
2929 goto out; 2917 goto out;
2930 } 2918 }
2931 udelay(PHY_WAIT_MICRO_SECONDS); 2919 udelay(PHY_WAIT_MICRO_SECONDS);
2932 } 2920 }
2933 2921
2934 mv_write(SMI_REG, 2922 wrl(mp, SMI_REG,
2935 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); 2923 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2936 2924
2937 /* now wait for the data to be valid */ 2925 /* now wait for the data to be valid */
2938 for (i = 0; !(mv_read(SMI_REG) & ETH_SMI_READ_VALID); i++) { 2926 for (i = 0; !(rdl(mp, SMI_REG) & ETH_SMI_READ_VALID); i++) {
2939 if (i == PHY_WAIT_ITERATIONS) { 2927 if (i == PHY_WAIT_ITERATIONS) {
2940 printk("mv643xx PHY read timeout, port %d\n", port_num); 2928 printk("%s: PHY read timeout\n", mp->dev->name);
2941 goto out; 2929 goto out;
2942 } 2930 }
2943 udelay(PHY_WAIT_MICRO_SECONDS); 2931 udelay(PHY_WAIT_MICRO_SECONDS);
2944 } 2932 }
2945 2933
2946 *value = mv_read(SMI_REG) & 0xffff; 2934 *value = rdl(mp, SMI_REG) & 0xffff;
2947out: 2935out:
2948 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); 2936 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2949} 2937}
@@ -2956,7 +2944,7 @@ out:
2956 * order to perform writes to PHY registers. 2944 * order to perform writes to PHY registers.
2957 * 2945 *
2958 * INPUT: 2946 * INPUT:
2959 * unsigned int eth_port_num Ethernet Port number. 2947 * struct mv643xx_private *mp Ethernet Port.
2960 * unsigned int phy_reg PHY register address offset. 2948 * unsigned int phy_reg PHY register address offset.
2961 * unsigned int value Register value. 2949 * unsigned int value Register value.
2962 * 2950 *
@@ -2968,29 +2956,28 @@ out:
2968 * true otherwise. 2956 * true otherwise.
2969 * 2957 *
2970 */ 2958 */
2971static void eth_port_write_smi_reg(unsigned int eth_port_num, 2959static void eth_port_write_smi_reg(struct mv643xx_private *mp,
2972 unsigned int phy_reg, unsigned int value) 2960 unsigned int phy_reg, unsigned int value)
2973{ 2961{
2974 int phy_addr; 2962 int phy_addr;
2975 int i; 2963 int i;
2976 unsigned long flags; 2964 unsigned long flags;
2977 2965
2978 phy_addr = ethernet_phy_get(eth_port_num); 2966 phy_addr = ethernet_phy_get(mp);
2979 2967
2980 /* the SMI register is a shared resource */ 2968 /* the SMI register is a shared resource */
2981 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); 2969 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2982 2970
2983 /* wait for the SMI register to become available */ 2971 /* wait for the SMI register to become available */
2984 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) { 2972 for (i = 0; rdl(mp, SMI_REG) & ETH_SMI_BUSY; i++) {
2985 if (i == PHY_WAIT_ITERATIONS) { 2973 if (i == PHY_WAIT_ITERATIONS) {
2986 printk("mv643xx PHY busy timeout, port %d\n", 2974 printk("%s: PHY busy timeout\n", mp->dev->name);
2987 eth_port_num);
2988 goto out; 2975 goto out;
2989 } 2976 }
2990 udelay(PHY_WAIT_MICRO_SECONDS); 2977 udelay(PHY_WAIT_MICRO_SECONDS);
2991 } 2978 }
2992 2979
2993 mv_write(SMI_REG, (phy_addr << 16) | (phy_reg << 21) | 2980 wrl(mp, SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2994 ETH_SMI_OPCODE_WRITE | (value & 0xffff)); 2981 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2995out: 2982out:
2996 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); 2983 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
@@ -3001,17 +2988,17 @@ out:
3001 */ 2988 */
3002static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) 2989static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
3003{ 2990{
3004 int val;
3005 struct mv643xx_private *mp = netdev_priv(dev); 2991 struct mv643xx_private *mp = netdev_priv(dev);
2992 int val;
3006 2993
3007 eth_port_read_smi_reg(mp->port_num, location, &val); 2994 eth_port_read_smi_reg(mp, location, &val);
3008 return val; 2995 return val;
3009} 2996}
3010 2997
3011static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) 2998static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
3012{ 2999{
3013 struct mv643xx_private *mp = netdev_priv(dev); 3000 struct mv643xx_private *mp = netdev_priv(dev);
3014 eth_port_write_smi_reg(mp->port_num, location, val); 3001 eth_port_write_smi_reg(mp, location, val);
3015} 3002}
3016 3003
3017/* 3004/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 04:33:07 -0500