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-rw-r--r--drivers/net/mlx4/mlx4_en.h561
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diff --git a/drivers/net/mlx4/mlx4_en.h b/drivers/net/mlx4/mlx4_en.h
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1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/compiler.h>
38#include <linux/list.h>
39#include <linux/mutex.h>
40#include <linux/netdevice.h>
41#include <linux/inet_lro.h>
42
43#include <linux/mlx4/device.h>
44#include <linux/mlx4/qp.h>
45#include <linux/mlx4/cq.h>
46#include <linux/mlx4/srq.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "en_port.h"
50
51#define DRV_NAME "mlx4_en"
52#define DRV_VERSION "1.4.0"
53#define DRV_RELDATE "Sep 2008"
54
55
56#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
57
58#define mlx4_dbg(mlevel, priv, format, arg...) \
59 if (NETIF_MSG_##mlevel & priv->msg_enable) \
60 printk(KERN_DEBUG "%s %s: " format , DRV_NAME ,\
61 (&priv->mdev->pdev->dev)->bus_id , ## arg)
62
63#define mlx4_err(mdev, format, arg...) \
64 printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
65 (&mdev->pdev->dev)->bus_id , ## arg)
66#define mlx4_info(mdev, format, arg...) \
67 printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
68 (&mdev->pdev->dev)->bus_id , ## arg)
69#define mlx4_warn(mdev, format, arg...) \
70 printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
71 (&mdev->pdev->dev)->bus_id , ## arg)
72
73/*
74 * Device constants
75 */
76
77
78#define MLX4_EN_PAGE_SHIFT 12
79#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
80#define MAX_TX_RINGS 16
81#define MAX_RX_RINGS 16
82#define MAX_RSS_MAP_SIZE 64
83#define RSS_FACTOR 2
84#define TXBB_SIZE 64
85#define HEADROOM (2048 / TXBB_SIZE + 1)
86#define MAX_LSO_HDR_SIZE 92
87#define STAMP_STRIDE 64
88#define STAMP_DWORDS (STAMP_STRIDE / 4)
89#define STAMP_SHIFT 31
90#define STAMP_VAL 0x7fffffff
91#define STATS_DELAY (HZ / 4)
92
93/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
94#define MAX_DESC_SIZE 512
95#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
96
97/*
98 * OS related constants and tunables
99 */
100
101#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102
103#define MLX4_EN_ALLOC_ORDER 2
104#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
105
106#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
107
108/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
109 * and 4K allocations) */
110enum {
111 FRAG_SZ0 = 512 - NET_IP_ALIGN,
112 FRAG_SZ1 = 1024,
113 FRAG_SZ2 = 4096,
114 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
115};
116#define MLX4_EN_MAX_RX_FRAGS 4
117
118/* Minimum ring size for our page-allocation sceme to work */
119#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
120#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
121
122#define MLX4_EN_TX_RING_NUM 9
123#define MLX4_EN_DEF_TX_RING_SIZE 1024
124#define MLX4_EN_DEF_RX_RING_SIZE 1024
125
126/* Target number of bytes to coalesce with interrupt moderation */
127#define MLX4_EN_RX_COAL_TARGET 0x20000
128#define MLX4_EN_RX_COAL_TIME 0x10
129
130#define MLX4_EN_TX_COAL_PKTS 5
131#define MLX4_EN_TX_COAL_TIME 0x80
132
133#define MLX4_EN_RX_RATE_LOW 400000
134#define MLX4_EN_RX_COAL_TIME_LOW 0
135#define MLX4_EN_RX_RATE_HIGH 450000
136#define MLX4_EN_RX_COAL_TIME_HIGH 128
137#define MLX4_EN_RX_SIZE_THRESH 1024
138#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
139#define MLX4_EN_SAMPLE_INTERVAL 0
140
141#define MLX4_EN_AUTO_CONF 0xffff
142
143#define MLX4_EN_DEF_RX_PAUSE 1
144#define MLX4_EN_DEF_TX_PAUSE 1
145
146/* Interval between sucessive polls in the Tx routine when polling is used
147 instead of interrupts (in per-core Tx rings) - should be power of 2 */
148#define MLX4_EN_TX_POLL_MODER 16
149#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
150
151#define ETH_LLC_SNAP_SIZE 8
152
153#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
154#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
155
156#define MLX4_EN_MIN_MTU 46
157#define ETH_BCAST 0xffffffffffffULL
158
159#ifdef MLX4_EN_PERF_STAT
160/* Number of samples to 'average' */
161#define AVG_SIZE 128
162#define AVG_FACTOR 1024
163#define NUM_PERF_STATS NUM_PERF_COUNTERS
164
165#define INC_PERF_COUNTER(cnt) (++(cnt))
166#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
167#define AVG_PERF_COUNTER(cnt, sample) \
168 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
169#define GET_PERF_COUNTER(cnt) (cnt)
170#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
171
172#else
173
174#define NUM_PERF_STATS 0
175#define INC_PERF_COUNTER(cnt) do {} while (0)
176#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
177#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
178#define GET_PERF_COUNTER(cnt) (0)
179#define GET_AVG_PERF_COUNTER(cnt) (0)
180#endif /* MLX4_EN_PERF_STAT */
181
182/*
183 * Configurables
184 */
185
186enum cq_type {
187 RX = 0,
188 TX = 1,
189};
190
191
192/*
193 * Useful macros
194 */
195#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
196#define XNOR(x, y) (!(x) == !(y))
197#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
198
199
200struct mlx4_en_tx_info {
201 struct sk_buff *skb;
202 u32 nr_txbb;
203 u8 linear;
204 u8 data_offset;
205};
206
207
208#define MLX4_EN_BIT_DESC_OWN 0x80000000
209#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
210#define MLX4_EN_MEMTYPE_PAD 0x100
211#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
212
213
214struct mlx4_en_tx_desc {
215 struct mlx4_wqe_ctrl_seg ctrl;
216 union {
217 struct mlx4_wqe_data_seg data; /* at least one data segment */
218 struct mlx4_wqe_lso_seg lso;
219 struct mlx4_wqe_inline_seg inl;
220 };
221};
222
223#define MLX4_EN_USE_SRQ 0x01000000
224
225struct mlx4_en_rx_alloc {
226 struct page *page;
227 u16 offset;
228};
229
230struct mlx4_en_tx_ring {
231 struct mlx4_hwq_resources wqres;
232 u32 size ; /* number of TXBBs */
233 u32 size_mask;
234 u16 stride;
235 u16 cqn; /* index of port CQ associated with this ring */
236 u32 prod;
237 u32 cons;
238 u32 buf_size;
239 u32 doorbell_qpn;
240 void *buf;
241 u16 poll_cnt;
242 int blocked;
243 struct mlx4_en_tx_info *tx_info;
244 u8 *bounce_buf;
245 u32 last_nr_txbb;
246 struct mlx4_qp qp;
247 struct mlx4_qp_context context;
248 int qpn;
249 enum mlx4_qp_state qp_state;
250 struct mlx4_srq dummy;
251 unsigned long bytes;
252 unsigned long packets;
253 spinlock_t comp_lock;
254};
255
256struct mlx4_en_rx_desc {
257 struct mlx4_wqe_srq_next_seg next;
258 /* actual number of entries depends on rx ring stride */
259 struct mlx4_wqe_data_seg data[0];
260};
261
262struct mlx4_en_rx_ring {
263 struct mlx4_srq srq;
264 struct mlx4_hwq_resources wqres;
265 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
266 struct net_lro_mgr lro;
267 u32 size ; /* number of Rx descs*/
268 u32 actual_size;
269 u32 size_mask;
270 u16 stride;
271 u16 log_stride;
272 u16 cqn; /* index of port CQ associated with this ring */
273 u32 prod;
274 u32 cons;
275 u32 buf_size;
276 int need_refill;
277 int full;
278 void *buf;
279 void *rx_info;
280 unsigned long bytes;
281 unsigned long packets;
282};
283
284
285static inline int mlx4_en_can_lro(__be16 status)
286{
287 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
288 MLX4_CQE_STATUS_IPV4F |
289 MLX4_CQE_STATUS_IPV6 |
290 MLX4_CQE_STATUS_IPV4OPT |
291 MLX4_CQE_STATUS_TCP |
292 MLX4_CQE_STATUS_UDP |
293 MLX4_CQE_STATUS_IPOK)) ==
294 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
295 MLX4_CQE_STATUS_IPOK |
296 MLX4_CQE_STATUS_TCP);
297}
298
299struct mlx4_en_cq {
300 struct mlx4_cq mcq;
301 struct mlx4_hwq_resources wqres;
302 int ring;
303 spinlock_t lock;
304 struct net_device *dev;
305 struct napi_struct napi;
306 /* Per-core Tx cq processing support */
307 struct timer_list timer;
308 int size;
309 int buf_size;
310 unsigned vector;
311 enum cq_type is_tx;
312 u16 moder_time;
313 u16 moder_cnt;
314 int armed;
315 struct mlx4_cqe *buf;
316#define MLX4_EN_OPCODE_ERROR 0x1e
317};
318
319struct mlx4_en_port_profile {
320 u32 flags;
321 u32 tx_ring_num;
322 u32 rx_ring_num;
323 u32 tx_ring_size;
324 u32 rx_ring_size;
325};
326
327struct mlx4_en_profile {
328 int rss_xor;
329 int num_lro;
330 u8 rss_mask;
331 u32 active_ports;
332 u32 small_pkt_int;
333 int rx_moder_cnt;
334 int rx_moder_time;
335 int auto_moder;
336 u8 rx_pause;
337 u8 rx_ppp;
338 u8 tx_pause;
339 u8 tx_ppp;
340 u8 no_reset;
341 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
342};
343
344struct mlx4_en_dev {
345 struct mlx4_dev *dev;
346 struct pci_dev *pdev;
347 struct mutex state_lock;
348 struct net_device *pndev[MLX4_MAX_PORTS + 1];
349 u32 port_cnt;
350 bool device_up;
351 struct mlx4_en_profile profile;
352 u32 LSO_support;
353 struct workqueue_struct *workqueue;
354 struct device *dma_device;
355 void __iomem *uar_map;
356 struct mlx4_uar priv_uar;
357 struct mlx4_mr mr;
358 u32 priv_pdn;
359 spinlock_t uar_lock;
360};
361
362
363struct mlx4_en_rss_map {
364 int size;
365 int base_qpn;
366 u16 map[MAX_RSS_MAP_SIZE];
367 struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
368 enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
369 struct mlx4_qp indir_qp;
370 enum mlx4_qp_state indir_state;
371};
372
373struct mlx4_en_rss_context {
374 __be32 base_qpn;
375 __be32 default_qpn;
376 u16 reserved;
377 u8 hash_fn;
378 u8 flags;
379 __be32 rss_key[10];
380};
381
382struct mlx4_en_pkt_stats {
383 unsigned long broadcast;
384 unsigned long rx_prio[8];
385 unsigned long tx_prio[8];
386#define NUM_PKT_STATS 17
387};
388
389struct mlx4_en_port_stats {
390 unsigned long lro_aggregated;
391 unsigned long lro_flushed;
392 unsigned long lro_no_desc;
393 unsigned long tso_packets;
394 unsigned long queue_stopped;
395 unsigned long wake_queue;
396 unsigned long tx_timeout;
397 unsigned long rx_alloc_failed;
398 unsigned long rx_chksum_good;
399 unsigned long rx_chksum_none;
400 unsigned long tx_chksum_offload;
401#define NUM_PORT_STATS 11
402};
403
404struct mlx4_en_perf_stats {
405 u32 tx_poll;
406 u64 tx_pktsz_avg;
407 u32 inflight_avg;
408 u16 tx_coal_avg;
409 u16 rx_coal_avg;
410 u32 napi_quota;
411#define NUM_PERF_COUNTERS 6
412};
413
414struct mlx4_en_frag_info {
415 u16 frag_size;
416 u16 frag_prefix_size;
417 u16 frag_stride;
418 u16 frag_align;
419 u16 last_offset;
420
421};
422
423struct mlx4_en_priv {
424 struct mlx4_en_dev *mdev;
425 struct mlx4_en_port_profile *prof;
426 struct net_device *dev;
427 struct vlan_group *vlgrp;
428 struct net_device_stats stats;
429 struct net_device_stats ret_stats;
430 spinlock_t stats_lock;
431
432 unsigned long last_moder_packets;
433 unsigned long last_moder_tx_packets;
434 unsigned long last_moder_bytes;
435 unsigned long last_moder_jiffies;
436 int last_moder_time;
437 u16 rx_usecs;
438 u16 rx_frames;
439 u16 tx_usecs;
440 u16 tx_frames;
441 u32 pkt_rate_low;
442 u16 rx_usecs_low;
443 u32 pkt_rate_high;
444 u16 rx_usecs_high;
445 u16 sample_interval;
446 u16 adaptive_rx_coal;
447 u32 msg_enable;
448
449 struct mlx4_hwq_resources res;
450 int link_state;
451 int last_link_state;
452 bool port_up;
453 int port;
454 int registered;
455 int allocated;
456 int stride;
457 int rx_csum;
458 u64 mac;
459 int mac_index;
460 unsigned max_mtu;
461 int base_qpn;
462
463 struct mlx4_en_rss_map rss_map;
464 u16 tx_prio_map[8];
465 u32 flags;
466#define MLX4_EN_FLAG_PROMISC 0x1
467 u32 tx_ring_num;
468 u32 rx_ring_num;
469 u32 rx_skb_size;
470 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
471 u16 num_frags;
472 u16 log_rx_info;
473
474 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
475 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
476 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
477 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
478 struct work_struct mcast_task;
479 struct work_struct mac_task;
480 struct delayed_work refill_task;
481 struct work_struct watchdog_task;
482 struct work_struct linkstate_task;
483 struct delayed_work stats_task;
484 struct mlx4_en_perf_stats pstats;
485 struct mlx4_en_pkt_stats pkstats;
486 struct mlx4_en_port_stats port_stats;
487 struct dev_mc_list *mc_list;
488 struct mlx4_en_stat_out_mbox hw_stats;
489};
490
491
492void mlx4_en_destroy_netdev(struct net_device *dev);
493int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
494 struct mlx4_en_port_profile *prof);
495
496int mlx4_en_get_profile(struct mlx4_en_dev *mdev);
497
498int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
499 int entries, int ring, enum cq_type mode);
500void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
501int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
502void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
503int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
504int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
505
506void mlx4_en_poll_tx_cq(unsigned long data);
507void mlx4_en_tx_irq(struct mlx4_cq *mcq);
508int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
509
510int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
511 u32 size, u16 stride);
512void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
513int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
514 struct mlx4_en_tx_ring *ring,
515 int cq, int srqn);
516void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
517 struct mlx4_en_tx_ring *ring);
518
519int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
520 struct mlx4_en_rx_ring *ring,
521 u32 size, u16 stride);
522void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
523 struct mlx4_en_rx_ring *ring);
524int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
525void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
526 struct mlx4_en_rx_ring *ring);
527int mlx4_en_process_rx_cq(struct net_device *dev,
528 struct mlx4_en_cq *cq,
529 int budget);
530int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
531void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
532 int is_tx, int rss, int qpn, int cqn, int srqn,
533 struct mlx4_qp_context *context);
534int mlx4_en_map_buffer(struct mlx4_buf *buf);
535void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
536
537void mlx4_en_calc_rx_buf(struct net_device *dev);
538void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
539 struct mlx4_en_rss_map *rss_map,
540 int num_entries, int num_rings);
541void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num);
542int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
543void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
544int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
545void mlx4_en_rx_refill(struct work_struct *work);
546void mlx4_en_rx_irq(struct mlx4_cq *mcq);
547
548int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
549int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
550int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
551 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
552int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
553 u8 promisc);
554
555int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
556
557/*
558 * Globals
559 */
560extern const struct ethtool_ops mlx4_en_ethtool_ops;
561#endif
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