diff options
Diffstat (limited to 'drivers/net/mlx4/fw.c')
-rw-r--r-- | drivers/net/mlx4/fw.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c index 7e32955da982..be09fdb79cb8 100644 --- a/drivers/net/mlx4/fw.c +++ b/drivers/net/mlx4/fw.c | |||
@@ -88,6 +88,7 @@ static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags) | |||
88 | [ 8] = "P_Key violation counter", | 88 | [ 8] = "P_Key violation counter", |
89 | [ 9] = "Q_Key violation counter", | 89 | [ 9] = "Q_Key violation counter", |
90 | [10] = "VMM", | 90 | [10] = "VMM", |
91 | [12] = "DPDP", | ||
91 | [16] = "MW support", | 92 | [16] = "MW support", |
92 | [17] = "APM support", | 93 | [17] = "APM support", |
93 | [18] = "Atomic ops support", | 94 | [18] = "Atomic ops support", |
@@ -346,7 +347,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
346 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); | 347 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
347 | dev_cap->max_vl[i] = field >> 4; | 348 | dev_cap->max_vl[i] = field >> 4; |
348 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); | 349 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); |
349 | dev_cap->max_mtu[i] = field >> 4; | 350 | dev_cap->ib_mtu[i] = field >> 4; |
350 | dev_cap->max_port_width[i] = field & 0xf; | 351 | dev_cap->max_port_width[i] = field & 0xf; |
351 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); | 352 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); |
352 | dev_cap->max_gids[i] = 1 << (field & 0xf); | 353 | dev_cap->max_gids[i] = 1 << (field & 0xf); |
@@ -354,9 +355,13 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
354 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | 355 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
355 | } | 356 | } |
356 | } else { | 357 | } else { |
358 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 | ||
357 | #define QUERY_PORT_MTU_OFFSET 0x01 | 359 | #define QUERY_PORT_MTU_OFFSET 0x01 |
360 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 | ||
358 | #define QUERY_PORT_WIDTH_OFFSET 0x06 | 361 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
359 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 | 362 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 |
363 | #define QUERY_PORT_MAC_OFFSET 0x08 | ||
364 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a | ||
360 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b | 365 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
361 | 366 | ||
362 | for (i = 1; i <= dev_cap->num_ports; ++i) { | 367 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
@@ -365,8 +370,10 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
365 | if (err) | 370 | if (err) |
366 | goto out; | 371 | goto out; |
367 | 372 | ||
373 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); | ||
374 | dev_cap->supported_port_types[i] = field & 3; | ||
368 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); | 375 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
369 | dev_cap->max_mtu[i] = field & 0xf; | 376 | dev_cap->ib_mtu[i] = field & 0xf; |
370 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); | 377 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
371 | dev_cap->max_port_width[i] = field & 0xf; | 378 | dev_cap->max_port_width[i] = field & 0xf; |
372 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); | 379 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); |
@@ -374,6 +381,11 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
374 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | 381 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
375 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); | 382 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); |
376 | dev_cap->max_vl[i] = field & 0xf; | 383 | dev_cap->max_vl[i] = field & 0xf; |
384 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); | ||
385 | dev_cap->log_max_macs[i] = field & 0xf; | ||
386 | dev_cap->log_max_vlans[i] = field >> 4; | ||
387 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); | ||
388 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); | ||
377 | } | 389 | } |
378 | } | 390 | } |
379 | 391 | ||
@@ -407,7 +419,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |||
407 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | 419 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
408 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); | 420 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); |
409 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", | 421 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", |
410 | dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1], | 422 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
411 | dev_cap->max_port_width[1]); | 423 | dev_cap->max_port_width[1]); |
412 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", | 424 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
413 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); | 425 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); |
@@ -819,7 +831,7 @@ int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) | |||
819 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; | 831 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; |
820 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); | 832 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); |
821 | 833 | ||
822 | field = 128 << dev->caps.mtu_cap[port]; | 834 | field = 128 << dev->caps.ib_mtu_cap[port]; |
823 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); | 835 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
824 | field = dev->caps.gid_table_len[port]; | 836 | field = dev->caps.gid_table_len[port]; |
825 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); | 837 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); |