diff options
Diffstat (limited to 'drivers/net/mipsnet.h')
-rw-r--r-- | drivers/net/mipsnet.h | 83 |
1 files changed, 44 insertions, 39 deletions
diff --git a/drivers/net/mipsnet.h b/drivers/net/mipsnet.h index 026c732024c9..0132c6714a40 100644 --- a/drivers/net/mipsnet.h +++ b/drivers/net/mipsnet.h | |||
@@ -9,32 +9,34 @@ | |||
9 | /* | 9 | /* |
10 | * Id of this Net device, as seen by the core. | 10 | * Id of this Net device, as seen by the core. |
11 | */ | 11 | */ |
12 | #define MIPS_NET_DEV_ID ((uint64_t) \ | 12 | #define MIPS_NET_DEV_ID ((uint64_t) \ |
13 | ((uint64_t)'M'<< 0)| \ | 13 | ((uint64_t) 'M' << 0)| \ |
14 | ((uint64_t)'I'<< 8)| \ | 14 | ((uint64_t) 'I' << 8)| \ |
15 | ((uint64_t)'P'<<16)| \ | 15 | ((uint64_t) 'P' << 16)| \ |
16 | ((uint64_t)'S'<<24)| \ | 16 | ((uint64_t) 'S' << 24)| \ |
17 | ((uint64_t)'N'<<32)| \ | 17 | ((uint64_t) 'N' << 32)| \ |
18 | ((uint64_t)'E'<<40)| \ | 18 | ((uint64_t) 'E' << 40)| \ |
19 | ((uint64_t)'T'<<48)| \ | 19 | ((uint64_t) 'T' << 48)| \ |
20 | ((uint64_t)'0'<<56)) | 20 | ((uint64_t) '0' << 56)) |
21 | 21 | ||
22 | /* | 22 | /* |
23 | * Net status/control block as seen by sw in the core. | 23 | * Net status/control block as seen by sw in the core. |
24 | * (Why not use bit fields? can't be bothered with cross-platform struct | 24 | * (Why not use bit fields? can't be bothered with cross-platform struct |
25 | * packing.) | 25 | * packing.) |
26 | */ | 26 | */ |
27 | typedef struct _net_control_block { | 27 | struct net_control_block { |
28 | /// dev info for probing | 28 | /* |
29 | /// reads as MIPSNET%d where %d is some form of version | 29 | * dev info for probing |
30 | uint64_t devId; /*0x00 */ | 30 | * reads as MIPSNET%d where %d is some form of version |
31 | */ | ||
32 | uint64_t devId; /* 0x00 */ | ||
31 | 33 | ||
32 | /* | 34 | /* |
33 | * read only busy flag. | 35 | * read only busy flag. |
34 | * Set and cleared by the Net Device to indicate that an rx or a tx | 36 | * Set and cleared by the Net Device to indicate that an rx or a tx |
35 | * is in progress. | 37 | * is in progress. |
36 | */ | 38 | */ |
37 | uint32_t busy; /*0x08 */ | 39 | uint32_t busy; /* 0x08 */ |
38 | 40 | ||
39 | /* | 41 | /* |
40 | * Set by the Net Device. | 42 | * Set by the Net Device. |
@@ -43,16 +45,16 @@ typedef struct _net_control_block { | |||
43 | * rxDataBuffer. The value will decrease till 0 until all the data | 45 | * rxDataBuffer. The value will decrease till 0 until all the data |
44 | * from rxDataBuffer has been read. | 46 | * from rxDataBuffer has been read. |
45 | */ | 47 | */ |
46 | uint32_t rxDataCount; /*0x0c */ | 48 | uint32_t rxDataCount; /* 0x0c */ |
47 | #define MIPSNET_MAX_RXTX_DATACOUNT (1<<16) | 49 | #define MIPSNET_MAX_RXTX_DATACOUNT (1<<16) |
48 | 50 | ||
49 | /* | 51 | /* |
50 | * Settable from the MIPS core, cleared by the Net Device. | 52 | * Settable from the MIPS core, cleared by the Net Device. The core |
51 | * The core should set the number of bytes it wants to send, | 53 | * should set the number of bytes it wants to send, then it should |
52 | * then it should write those bytes of data to txDataBuffer. | 54 | * write those bytes of data to txDataBuffer. The device will clear |
53 | * The device will clear txDataCount has been processed (not necessarily sent). | 55 | * txDataCount has been processed (not necessarily sent). |
54 | */ | 56 | */ |
55 | uint32_t txDataCount; /*0x10 */ | 57 | uint32_t txDataCount; /* 0x10 */ |
56 | 58 | ||
57 | /* | 59 | /* |
58 | * Interrupt control | 60 | * Interrupt control |
@@ -69,39 +71,42 @@ typedef struct _net_control_block { | |||
69 | * To clear the test interrupt, write 0 to this register. | 71 | * To clear the test interrupt, write 0 to this register. |
70 | */ | 72 | */ |
71 | uint32_t interruptControl; /*0x14 */ | 73 | uint32_t interruptControl; /*0x14 */ |
72 | #define MIPSNET_INTCTL_TXDONE ((uint32_t)(1<< 0)) | 74 | #define MIPSNET_INTCTL_TXDONE ((uint32_t)(1 << 0)) |
73 | #define MIPSNET_INTCTL_RXDONE ((uint32_t)(1<< 1)) | 75 | #define MIPSNET_INTCTL_RXDONE ((uint32_t)(1 << 1)) |
74 | #define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1<<31)) | 76 | #define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1 << 31)) |
75 | #define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE|MIPSNET_INTCTL_RXDONE|MIPSNET_INTCTL_TESTBIT) | 77 | #define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE | \ |
78 | MIPSNET_INTCTL_RXDONE | \ | ||
79 | MIPSNET_INTCTL_TESTBIT) | ||
76 | 80 | ||
77 | /* | 81 | /* |
78 | * Readonly core-specific interrupt info for the device to signal the core. | 82 | * Readonly core-specific interrupt info for the device to signal the |
79 | * The meaning of the contents of this field might change. | 83 | * core. The meaning of the contents of this field might change. |
80 | */ | 84 | * |
81 | /*###\todo: the whole memIntf interrupt scheme is messy: the device should have | 85 | * TODO: the whole memIntf interrupt scheme is messy: the device should |
82 | * no control what so ever of what VPE/register set is being used. | 86 | * have no control what so ever of what VPE/register set is being |
83 | * The MemIntf should only expose interrupt lines, and something in the | 87 | * used. The MemIntf should only expose interrupt lines, and |
84 | * config should be responsible for the line<->core/vpe bindings. | 88 | * something in the config should be responsible for the |
89 | * line<->core/vpe bindings. | ||
85 | */ | 90 | */ |
86 | uint32_t interruptInfo; /*0x18 */ | 91 | uint32_t interruptInfo; /* 0x18 */ |
87 | 92 | ||
88 | /* | 93 | /* |
89 | * This is where the received data is read out. | 94 | * This is where the received data is read out. |
90 | * There is more data to read until rxDataReady is 0. | 95 | * There is more data to read until rxDataReady is 0. |
91 | * Only 1 byte at this regs offset is used. | 96 | * Only 1 byte at this regs offset is used. |
92 | */ | 97 | */ |
93 | uint32_t rxDataBuffer; /*0x1c */ | 98 | uint32_t rxDataBuffer; /* 0x1c */ |
94 | 99 | ||
95 | /* | 100 | /* |
96 | * This is where the data to transmit is written. | 101 | * This is where the data to transmit is written. Data should be |
97 | * Data should be written for the amount specified in the txDataCount register. | 102 | * written for the amount specified in the txDataCount register. Only |
98 | * Only 1 byte at this regs offset is used. | 103 | * 1 byte at this regs offset is used. |
99 | */ | 104 | */ |
100 | uint32_t txDataBuffer; /*0x20 */ | 105 | uint32_t txDataBuffer; /* 0x20 */ |
101 | } MIPS_T_NetControl; | 106 | }; |
102 | 107 | ||
103 | #define MIPSNET_IO_EXTENT 0x40 /* being generous */ | 108 | #define MIPSNET_IO_EXTENT 0x40 /* being generous */ |
104 | 109 | ||
105 | #define field_offset(field) ((int)&((MIPS_T_NetControl*)(0))->field) | 110 | #define field_offset(field) (offsetof(struct net_control_block, field)) |
106 | 111 | ||
107 | #endif /* __MIPSNET_H */ | 112 | #endif /* __MIPSNET_H */ |