aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ks8851.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/ks8851.h')
-rw-r--r--drivers/net/ks8851.h296
1 files changed, 296 insertions, 0 deletions
diff --git a/drivers/net/ks8851.h b/drivers/net/ks8851.h
new file mode 100644
index 000000000000..85abe147afbf
--- /dev/null
+++ b/drivers/net/ks8851.h
@@ -0,0 +1,296 @@
1/* drivers/net/ks8851.h
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * KS8851 register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#define KS_CCR 0x08
14#define CCR_EEPROM (1 << 9)
15#define CCR_SPI (1 << 8)
16#define CCR_32PIN (1 << 0)
17
18/* MAC address registers */
19#define KS_MARL 0x10
20#define KS_MARM 0x12
21#define KS_MARH 0x14
22
23#define KS_OBCR 0x20
24#define OBCR_ODS_16mA (1 << 6)
25
26#define KS_EEPCR 0x22
27#define EEPCR_EESA (1 << 4)
28#define EEPCR_EESB (1 << 3)
29#define EEPCR_EEDO (1 << 2)
30#define EEPCR_EESCK (1 << 1)
31#define EEPCR_EECS (1 << 0)
32
33#define KS_MBIR 0x24
34#define MBIR_TXMBF (1 << 12)
35#define MBIR_TXMBFA (1 << 11)
36#define MBIR_RXMBF (1 << 4)
37#define MBIR_RXMBFA (1 << 3)
38
39#define KS_GRR 0x26
40#define GRR_QMU (1 << 1)
41#define GRR_GSR (1 << 0)
42
43#define KS_WFCR 0x2A
44#define WFCR_MPRXE (1 << 7)
45#define WFCR_WF3E (1 << 3)
46#define WFCR_WF2E (1 << 2)
47#define WFCR_WF1E (1 << 1)
48#define WFCR_WF0E (1 << 0)
49
50#define KS_WF0CRC0 0x30
51#define KS_WF0CRC1 0x32
52#define KS_WF0BM0 0x34
53#define KS_WF0BM1 0x36
54#define KS_WF0BM2 0x38
55#define KS_WF0BM3 0x3A
56
57#define KS_WF1CRC0 0x40
58#define KS_WF1CRC1 0x42
59#define KS_WF1BM0 0x44
60#define KS_WF1BM1 0x46
61#define KS_WF1BM2 0x48
62#define KS_WF1BM3 0x4A
63
64#define KS_WF2CRC0 0x50
65#define KS_WF2CRC1 0x52
66#define KS_WF2BM0 0x54
67#define KS_WF2BM1 0x56
68#define KS_WF2BM2 0x58
69#define KS_WF2BM3 0x5A
70
71#define KS_WF3CRC0 0x60
72#define KS_WF3CRC1 0x62
73#define KS_WF3BM0 0x64
74#define KS_WF3BM1 0x66
75#define KS_WF3BM2 0x68
76#define KS_WF3BM3 0x6A
77
78#define KS_TXCR 0x70
79#define TXCR_TCGICMP (1 << 8)
80#define TXCR_TCGUDP (1 << 7)
81#define TXCR_TCGTCP (1 << 6)
82#define TXCR_TCGIP (1 << 5)
83#define TXCR_FTXQ (1 << 4)
84#define TXCR_TXFCE (1 << 3)
85#define TXCR_TXPE (1 << 2)
86#define TXCR_TXCRC (1 << 1)
87#define TXCR_TXE (1 << 0)
88
89#define KS_TXSR 0x72
90#define TXSR_TXLC (1 << 13)
91#define TXSR_TXMC (1 << 12)
92#define TXSR_TXFID_MASK (0x3f << 0)
93#define TXSR_TXFID_SHIFT (0)
94#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
95
96#define KS_RXCR1 0x74
97#define RXCR1_FRXQ (1 << 15)
98#define RXCR1_RXUDPFCC (1 << 14)
99#define RXCR1_RXTCPFCC (1 << 13)
100#define RXCR1_RXIPFCC (1 << 12)
101#define RXCR1_RXPAFMA (1 << 11)
102#define RXCR1_RXFCE (1 << 10)
103#define RXCR1_RXEFE (1 << 9)
104#define RXCR1_RXMAFMA (1 << 8)
105#define RXCR1_RXBE (1 << 7)
106#define RXCR1_RXME (1 << 6)
107#define RXCR1_RXUE (1 << 5)
108#define RXCR1_RXAE (1 << 4)
109#define RXCR1_RXINVF (1 << 1)
110#define RXCR1_RXE (1 << 0)
111
112#define KS_RXCR2 0x76
113#define RXCR2_SRDBL_MASK (0x7 << 5)
114#define RXCR2_SRDBL_SHIFT (5)
115#define RXCR2_SRDBL_4B (0x0 << 5)
116#define RXCR2_SRDBL_8B (0x1 << 5)
117#define RXCR2_SRDBL_16B (0x2 << 5)
118#define RXCR2_SRDBL_32B (0x3 << 5)
119#define RXCR2_SRDBL_FRAME (0x4 << 5)
120#define RXCR2_IUFFP (1 << 4)
121#define RXCR2_RXIUFCEZ (1 << 3)
122#define RXCR2_UDPLFE (1 << 2)
123#define RXCR2_RXICMPFCC (1 << 1)
124#define RXCR2_RXSAF (1 << 0)
125
126#define KS_TXMIR 0x78
127
128#define KS_RXFHSR 0x7C
129#define RXFSHR_RXFV (1 << 15)
130#define RXFSHR_RXICMPFCS (1 << 13)
131#define RXFSHR_RXIPFCS (1 << 12)
132#define RXFSHR_RXTCPFCS (1 << 11)
133#define RXFSHR_RXUDPFCS (1 << 10)
134#define RXFSHR_RXBF (1 << 7)
135#define RXFSHR_RXMF (1 << 6)
136#define RXFSHR_RXUF (1 << 5)
137#define RXFSHR_RXMR (1 << 4)
138#define RXFSHR_RXFT (1 << 3)
139#define RXFSHR_RXFTL (1 << 2)
140#define RXFSHR_RXRF (1 << 1)
141#define RXFSHR_RXCE (1 << 0)
142
143#define KS_RXFHBCR 0x7E
144#define KS_TXQCR 0x80
145#define TXQCR_AETFE (1 << 2)
146#define TXQCR_TXQMAM (1 << 1)
147#define TXQCR_METFE (1 << 0)
148
149#define KS_RXQCR 0x82
150#define RXQCR_RXDTTS (1 << 12)
151#define RXQCR_RXDBCTS (1 << 11)
152#define RXQCR_RXFCTS (1 << 10)
153#define RXQCR_RXIPHTOE (1 << 9)
154#define RXQCR_RXDTTE (1 << 7)
155#define RXQCR_RXDBCTE (1 << 6)
156#define RXQCR_RXFCTE (1 << 5)
157#define RXQCR_ADRFE (1 << 4)
158#define RXQCR_SDA (1 << 3)
159#define RXQCR_RRXEF (1 << 0)
160
161#define KS_TXFDPR 0x84
162#define TXFDPR_TXFPAI (1 << 14)
163#define TXFDPR_TXFP_MASK (0x7ff << 0)
164#define TXFDPR_TXFP_SHIFT (0)
165
166#define KS_RXFDPR 0x86
167#define RXFDPR_RXFPAI (1 << 14)
168
169#define KS_RXDTTR 0x8C
170#define KS_RXDBCTR 0x8E
171
172#define KS_IER 0x90
173#define KS_ISR 0x92
174#define IRQ_LCI (1 << 15)
175#define IRQ_TXI (1 << 14)
176#define IRQ_RXI (1 << 13)
177#define IRQ_RXOI (1 << 11)
178#define IRQ_TXPSI (1 << 9)
179#define IRQ_RXPSI (1 << 8)
180#define IRQ_TXSAI (1 << 6)
181#define IRQ_RXWFDI (1 << 5)
182#define IRQ_RXMPDI (1 << 4)
183#define IRQ_LDI (1 << 3)
184#define IRQ_EDI (1 << 2)
185#define IRQ_SPIBEI (1 << 1)
186#define IRQ_DEDI (1 << 0)
187
188#define KS_RXFCTR 0x9C
189#define KS_RXFC 0x9D
190#define RXFCTR_RXFC_MASK (0xff << 8)
191#define RXFCTR_RXFC_SHIFT (8)
192#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
193#define RXFCTR_RXFCT_MASK (0xff << 0)
194#define RXFCTR_RXFCT_SHIFT (0)
195
196#define KS_TXNTFSR 0x9E
197
198#define KS_MAHTR0 0xA0
199#define KS_MAHTR1 0xA2
200#define KS_MAHTR2 0xA4
201#define KS_MAHTR3 0xA6
202
203#define KS_FCLWR 0xB0
204#define KS_FCHWR 0xB2
205#define KS_FCOWR 0xB4
206
207#define KS_CIDER 0xC0
208#define CIDER_ID 0x8870
209#define CIDER_REV_MASK (0x7 << 1)
210#define CIDER_REV_SHIFT (1)
211#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
212
213#define KS_CGCR 0xC6
214
215#define KS_IACR 0xC8
216#define IACR_RDEN (1 << 12)
217#define IACR_TSEL_MASK (0x3 << 10)
218#define IACR_TSEL_SHIFT (10)
219#define IACR_TSEL_MIB (0x3 << 10)
220#define IACR_ADDR_MASK (0x1f << 0)
221#define IACR_ADDR_SHIFT (0)
222
223#define KS_IADLR 0xD0
224#define KS_IAHDR 0xD2
225
226#define KS_PMECR 0xD4
227#define PMECR_PME_DELAY (1 << 14)
228#define PMECR_PME_POL (1 << 12)
229#define PMECR_WOL_WAKEUP (1 << 11)
230#define PMECR_WOL_MAGICPKT (1 << 10)
231#define PMECR_WOL_LINKUP (1 << 9)
232#define PMECR_WOL_ENERGY (1 << 8)
233#define PMECR_AUTO_WAKE_EN (1 << 7)
234#define PMECR_WAKEUP_NORMAL (1 << 6)
235#define PMECR_WKEVT_MASK (0xf << 2)
236#define PMECR_WKEVT_SHIFT (2)
237#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
238#define PMECR_WKEVT_ENERGY (0x1 << 2)
239#define PMECR_WKEVT_LINK (0x2 << 2)
240#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
241#define PMECR_WKEVT_FRAME (0x8 << 2)
242#define PMECR_PM_MASK (0x3 << 0)
243#define PMECR_PM_SHIFT (0)
244#define PMECR_PM_NORMAL (0x0 << 0)
245#define PMECR_PM_ENERGY (0x1 << 0)
246#define PMECR_PM_SOFTDOWN (0x2 << 0)
247#define PMECR_PM_POWERSAVE (0x3 << 0)
248
249/* Standard MII PHY data */
250#define KS_P1MBCR 0xE4
251#define KS_P1MBSR 0xE6
252#define KS_PHY1ILR 0xE8
253#define KS_PHY1IHR 0xEA
254#define KS_P1ANAR 0xEC
255#define KS_P1ANLPR 0xEE
256
257#define KS_P1SCLMD 0xF4
258#define P1SCLMD_LEDOFF (1 << 15)
259#define P1SCLMD_TXIDS (1 << 14)
260#define P1SCLMD_RESTARTAN (1 << 13)
261#define P1SCLMD_DISAUTOMDIX (1 << 10)
262#define P1SCLMD_FORCEMDIX (1 << 9)
263#define P1SCLMD_AUTONEGEN (1 << 7)
264#define P1SCLMD_FORCE100 (1 << 6)
265#define P1SCLMD_FORCEFDX (1 << 5)
266#define P1SCLMD_ADV_FLOW (1 << 4)
267#define P1SCLMD_ADV_100BT_FDX (1 << 3)
268#define P1SCLMD_ADV_100BT_HDX (1 << 2)
269#define P1SCLMD_ADV_10BT_FDX (1 << 1)
270#define P1SCLMD_ADV_10BT_HDX (1 << 0)
271
272#define KS_P1CR 0xF6
273#define P1CR_HP_MDIX (1 << 15)
274#define P1CR_REV_POL (1 << 13)
275#define P1CR_OP_100M (1 << 10)
276#define P1CR_OP_FDX (1 << 9)
277#define P1CR_OP_MDI (1 << 7)
278#define P1CR_AN_DONE (1 << 6)
279#define P1CR_LINK_GOOD (1 << 5)
280#define P1CR_PNTR_FLOW (1 << 4)
281#define P1CR_PNTR_100BT_FDX (1 << 3)
282#define P1CR_PNTR_100BT_HDX (1 << 2)
283#define P1CR_PNTR_10BT_FDX (1 << 1)
284#define P1CR_PNTR_10BT_HDX (1 << 0)
285
286/* TX Frame control */
287
288#define TXFR_TXIC (1 << 15)
289#define TXFR_TXFID_MASK (0x3f << 0)
290#define TXFR_TXFID_SHIFT (0)
291
292/* SPI frame opcodes */
293#define KS_SPIOP_RD (0x00)
294#define KS_SPIOP_WR (0x40)
295#define KS_SPIOP_RXFIFO (0x80)
296#define KS_SPIOP_TXFIFO (0xC0)