diff options
Diffstat (limited to 'drivers/net/ixp2000/caleb.c')
| -rw-r--r-- | drivers/net/ixp2000/caleb.c | 137 |
1 files changed, 137 insertions, 0 deletions
diff --git a/drivers/net/ixp2000/caleb.c b/drivers/net/ixp2000/caleb.c new file mode 100644 index 000000000000..3595e107df22 --- /dev/null +++ b/drivers/net/ixp2000/caleb.c | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | /* | ||
| 2 | * Helper functions for the SPI-3 bridge FPGA on the Radisys ENP2611 | ||
| 3 | * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 4 | * Dedicated to Marija Kulikova. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/config.h> | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/delay.h> | ||
| 15 | #include <asm/io.h> | ||
| 16 | #include "caleb.h" | ||
| 17 | |||
| 18 | #define CALEB_IDLO 0x00 | ||
| 19 | #define CALEB_IDHI 0x01 | ||
| 20 | #define CALEB_RID 0x02 | ||
| 21 | #define CALEB_RESET 0x03 | ||
| 22 | #define CALEB_INTREN0 0x04 | ||
| 23 | #define CALEB_INTREN1 0x05 | ||
| 24 | #define CALEB_INTRSTAT0 0x06 | ||
| 25 | #define CALEB_INTRSTAT1 0x07 | ||
| 26 | #define CALEB_PORTEN 0x08 | ||
| 27 | #define CALEB_BURST 0x09 | ||
| 28 | #define CALEB_PORTPAUS 0x0A | ||
| 29 | #define CALEB_PORTPAUSD 0x0B | ||
| 30 | #define CALEB_PHY0RX 0x10 | ||
| 31 | #define CALEB_PHY1RX 0x11 | ||
| 32 | #define CALEB_PHY0TX 0x12 | ||
| 33 | #define CALEB_PHY1TX 0x13 | ||
| 34 | #define CALEB_IXPRX_HI_CNTR 0x15 | ||
| 35 | #define CALEB_PHY0RX_HI_CNTR 0x16 | ||
| 36 | #define CALEB_PHY1RX_HI_CNTR 0x17 | ||
| 37 | #define CALEB_IXPRX_CNTR 0x18 | ||
| 38 | #define CALEB_PHY0RX_CNTR 0x19 | ||
| 39 | #define CALEB_PHY1RX_CNTR 0x1A | ||
| 40 | #define CALEB_IXPTX_CNTR 0x1B | ||
| 41 | #define CALEB_PHY0TX_CNTR 0x1C | ||
| 42 | #define CALEB_PHY1TX_CNTR 0x1D | ||
| 43 | #define CALEB_DEBUG0 0x1E | ||
| 44 | #define CALEB_DEBUG1 0x1F | ||
| 45 | |||
| 46 | |||
| 47 | static u8 caleb_reg_read(int reg) | ||
| 48 | { | ||
| 49 | u8 value; | ||
| 50 | |||
| 51 | value = *((volatile u8 *)(ENP2611_CALEB_VIRT_BASE + reg)); | ||
| 52 | |||
| 53 | // printk(KERN_INFO "caleb_reg_read(%d) = %.2x\n", reg, value); | ||
| 54 | |||
| 55 | return value; | ||
| 56 | } | ||
| 57 | |||
| 58 | static void caleb_reg_write(int reg, u8 value) | ||
| 59 | { | ||
| 60 | u8 dummy; | ||
| 61 | |||
| 62 | // printk(KERN_INFO "caleb_reg_write(%d, %.2x)\n", reg, value); | ||
| 63 | |||
| 64 | *((volatile u8 *)(ENP2611_CALEB_VIRT_BASE + reg)) = value; | ||
| 65 | |||
| 66 | dummy = *((volatile u8 *)ENP2611_CALEB_VIRT_BASE); | ||
| 67 | __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); | ||
| 68 | } | ||
| 69 | |||
| 70 | |||
| 71 | void caleb_reset(void) | ||
| 72 | { | ||
| 73 | /* | ||
| 74 | * Perform a chip reset. | ||
| 75 | */ | ||
| 76 | caleb_reg_write(CALEB_RESET, 0x02); | ||
| 77 | udelay(1); | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Enable all interrupt sources. This is needed to get | ||
| 81 | * meaningful results out of the status bits (register 6 | ||
| 82 | * and 7.) | ||
| 83 | */ | ||
| 84 | caleb_reg_write(CALEB_INTREN0, 0xff); | ||
| 85 | caleb_reg_write(CALEB_INTREN1, 0x07); | ||
| 86 | |||
| 87 | /* | ||
| 88 | * Set RX and TX FIFO thresholds to 1.5kb. | ||
| 89 | */ | ||
| 90 | caleb_reg_write(CALEB_PHY0RX, 0x11); | ||
| 91 | caleb_reg_write(CALEB_PHY1RX, 0x11); | ||
| 92 | caleb_reg_write(CALEB_PHY0TX, 0x11); | ||
| 93 | caleb_reg_write(CALEB_PHY1TX, 0x11); | ||
| 94 | |||
| 95 | /* | ||
| 96 | * Program SPI-3 burst size. | ||
| 97 | */ | ||
| 98 | caleb_reg_write(CALEB_BURST, 0); // 64-byte RBUF mpackets | ||
| 99 | // caleb_reg_write(CALEB_BURST, 1); // 128-byte RBUF mpackets | ||
| 100 | // caleb_reg_write(CALEB_BURST, 2); // 256-byte RBUF mpackets | ||
| 101 | } | ||
| 102 | |||
| 103 | void caleb_enable_rx(int port) | ||
| 104 | { | ||
| 105 | u8 temp; | ||
| 106 | |||
| 107 | temp = caleb_reg_read(CALEB_PORTEN); | ||
| 108 | temp |= 1 << port; | ||
| 109 | caleb_reg_write(CALEB_PORTEN, temp); | ||
| 110 | } | ||
| 111 | |||
| 112 | void caleb_disable_rx(int port) | ||
| 113 | { | ||
| 114 | u8 temp; | ||
| 115 | |||
| 116 | temp = caleb_reg_read(CALEB_PORTEN); | ||
| 117 | temp &= ~(1 << port); | ||
| 118 | caleb_reg_write(CALEB_PORTEN, temp); | ||
| 119 | } | ||
| 120 | |||
| 121 | void caleb_enable_tx(int port) | ||
| 122 | { | ||
| 123 | u8 temp; | ||
| 124 | |||
| 125 | temp = caleb_reg_read(CALEB_PORTEN); | ||
| 126 | temp |= 1 << (port + 4); | ||
| 127 | caleb_reg_write(CALEB_PORTEN, temp); | ||
| 128 | } | ||
| 129 | |||
| 130 | void caleb_disable_tx(int port) | ||
| 131 | { | ||
| 132 | u8 temp; | ||
| 133 | |||
| 134 | temp = caleb_reg_read(CALEB_PORTEN); | ||
| 135 | temp &= ~(1 << (port + 4)); | ||
| 136 | caleb_reg_write(CALEB_PORTEN, temp); | ||
| 137 | } | ||
