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-rw-r--r--drivers/net/ixgbe/ixgbe_main.c23
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index c407bd9de0dd..fe5273665836 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -1885,12 +1885,29 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1885 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); 1885 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1886 adapter->tx_ring[i].head = IXGBE_TDH(j); 1886 adapter->tx_ring[i].head = IXGBE_TDH(j);
1887 adapter->tx_ring[i].tail = IXGBE_TDT(j); 1887 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1888 /* Disable Tx Head Writeback RO bit, since this hoses 1888 /*
1889 * Disable Tx Head Writeback RO bit, since this hoses
1889 * bookkeeping if things aren't delivered in order. 1890 * bookkeeping if things aren't delivered in order.
1890 */ 1891 */
1891 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 1892 switch (hw->mac.type) {
1893 case ixgbe_mac_82598EB:
1894 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1895 break;
1896 case ixgbe_mac_82599EB:
1897 default:
1898 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1899 break;
1900 }
1892 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 1901 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1893 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 1902 switch (hw->mac.type) {
1903 case ixgbe_mac_82598EB:
1904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1905 break;
1906 case ixgbe_mac_82599EB:
1907 default:
1908 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1909 break;
1910 }
1894 } 1911 }
1895 if (hw->mac.type == ixgbe_mac_82599EB) { 1912 if (hw->mac.type == ixgbe_mac_82599EB) {
1896 /* We enable 8 traffic classes, DCB only */ 1913 /* We enable 8 traffic classes, DCB only */