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-rw-r--r--drivers/net/ixgbe/ixgbe.h4
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c67
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c38
-rw-r--r--drivers/net/ixgbe/ixgbe_fcoe.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c115
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h8
6 files changed, 154 insertions, 80 deletions
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 1b12c7ba275f..2c4dc8221dcd 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -96,6 +96,8 @@
96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98 98
99#define IXGBE_MAX_RSC_INT_RATE 162760
100
99/* wrapper around a pointer to a socket buffer, 101/* wrapper around a pointer to a socket buffer,
100 * so a DMA handle can be stored along with the buffer */ 102 * so a DMA handle can be stored along with the buffer */
101struct ixgbe_tx_buffer { 103struct ixgbe_tx_buffer {
@@ -134,6 +136,8 @@ struct ixgbe_ring {
134 136
135 u8 queue_index; /* needed for multiqueue queue management */ 137 u8 queue_index; /* needed for multiqueue queue management */
136 138
139#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
140 u8 flags; /* per ring feature flags */
137 u16 head; 141 u16 head;
138 u16 tail; 142 u16 tail;
139 143
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index b9923047ce11..522c03bc1dad 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -50,6 +50,51 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data); 50 u8 *eeprom_data);
51 51
52/** 52/**
53 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
54 * @hw: pointer to the HW structure
55 *
56 * The defaults for 82598 should be in the range of 50us to 50ms,
57 * however the hardware default for these parts is 500us to 1ms which is less
58 * than the 10ms recommended by the pci-e spec. To address this we need to
59 * increase the value to either 10ms to 250ms for capability version 1 config,
60 * or 16ms to 55ms for version 2.
61 **/
62void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
63{
64 struct ixgbe_adapter *adapter = hw->back;
65 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
66 u16 pcie_devctl2;
67
68 /* only take action if timeout value is defaulted to 0 */
69 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
70 goto out;
71
72 /*
73 * if capababilities version is type 1 we can write the
74 * timeout of 10ms to 250ms through the GCR register
75 */
76 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
77 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
78 goto out;
79 }
80
81 /*
82 * for version 2 capabilities we need to write the config space
83 * directly in order to set the completion timeout value for
84 * 16ms to 55ms
85 */
86 pci_read_config_word(adapter->pdev,
87 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
88 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
89 pci_write_config_word(adapter->pdev,
90 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
91out:
92 /* disable completion timeout resend */
93 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
94 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
95}
96
97/**
53 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 98 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
54 * @hw: pointer to hardware structure 99 * @hw: pointer to hardware structure
55 * 100 *
@@ -153,6 +198,26 @@ out:
153} 198}
154 199
155/** 200/**
201 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
202 * @hw: pointer to hardware structure
203 *
204 * Starts the hardware using the generic start_hw function.
205 * Then set pcie completion timeout
206 **/
207s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
208{
209 s32 ret_val = 0;
210
211 ret_val = ixgbe_start_hw_generic(hw);
212
213 /* set the completion timeout for interface */
214 if (ret_val == 0)
215 ixgbe_set_pcie_completion_timeout(hw);
216
217 return ret_val;
218}
219
220/**
156 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 221 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
157 * @hw: pointer to hardware structure 222 * @hw: pointer to hardware structure
158 * @speed: pointer to link speed 223 * @speed: pointer to link speed
@@ -1085,7 +1150,7 @@ out:
1085static struct ixgbe_mac_operations mac_ops_82598 = { 1150static struct ixgbe_mac_operations mac_ops_82598 = {
1086 .init_hw = &ixgbe_init_hw_generic, 1151 .init_hw = &ixgbe_init_hw_generic,
1087 .reset_hw = &ixgbe_reset_hw_82598, 1152 .reset_hw = &ixgbe_reset_hw_82598,
1088 .start_hw = &ixgbe_start_hw_generic, 1153 .start_hw = &ixgbe_start_hw_82598,
1089 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1154 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1090 .get_media_type = &ixgbe_get_media_type_82598, 1155 .get_media_type = &ixgbe_get_media_type_82598,
1091 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, 1156 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 2a978008fd6e..dff8dfac7ed9 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -1948,6 +1948,7 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
1948 struct ethtool_coalesce *ec) 1948 struct ethtool_coalesce *ec)
1949{ 1949{
1950 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1950 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1951 struct ixgbe_q_vector *q_vector;
1951 int i; 1952 int i;
1952 1953
1953 if (ec->tx_max_coalesced_frames_irq) 1954 if (ec->tx_max_coalesced_frames_irq)
@@ -1975,18 +1976,31 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
1975 * any other value means disable eitr, which is best 1976 * any other value means disable eitr, which is best
1976 * served by setting the interrupt rate very high 1977 * served by setting the interrupt rate very high
1977 */ 1978 */
1978 adapter->eitr_param = IXGBE_MAX_INT_RATE; 1979 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
1980 adapter->eitr_param = IXGBE_MAX_RSC_INT_RATE;
1981 else
1982 adapter->eitr_param = IXGBE_MAX_INT_RATE;
1979 adapter->itr_setting = 0; 1983 adapter->itr_setting = 0;
1980 } 1984 }
1981 1985
1982 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { 1986 /* MSI/MSIx Interrupt Mode */
1983 struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; 1987 if (adapter->flags &
1984 if (q_vector->txr_count && !q_vector->rxr_count) 1988 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
1985 /* tx vector gets half the rate */ 1989 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1986 q_vector->eitr = (adapter->eitr_param >> 1); 1990 for (i = 0; i < num_vectors; i++) {
1987 else 1991 q_vector = adapter->q_vector[i];
1988 /* rx only or mixed */ 1992 if (q_vector->txr_count && !q_vector->rxr_count)
1989 q_vector->eitr = adapter->eitr_param; 1993 /* tx vector gets half the rate */
1994 q_vector->eitr = (adapter->eitr_param >> 1);
1995 else
1996 /* rx only or mixed */
1997 q_vector->eitr = adapter->eitr_param;
1998 ixgbe_write_eitr(q_vector);
1999 }
2000 /* Legacy Interrupt Mode */
2001 } else {
2002 q_vector = adapter->q_vector[0];
2003 q_vector->eitr = adapter->eitr_param;
1990 ixgbe_write_eitr(q_vector); 2004 ixgbe_write_eitr(q_vector);
1991 } 2005 }
1992 2006
@@ -1999,13 +2013,13 @@ static int ixgbe_set_flags(struct net_device *netdev, u32 data)
1999 2013
2000 ethtool_op_set_flags(netdev, data); 2014 ethtool_op_set_flags(netdev, data);
2001 2015
2002 if (!(adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)) 2016 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2003 return 0; 2017 return 0;
2004 2018
2005 /* if state changes we need to update adapter->flags and reset */ 2019 /* if state changes we need to update adapter->flags and reset */
2006 if ((!!(data & ETH_FLAG_LRO)) != 2020 if ((!!(data & ETH_FLAG_LRO)) !=
2007 (!!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED))) { 2021 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2008 adapter->flags ^= IXGBE_FLAG2_RSC_ENABLED; 2022 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2009 if (netif_running(netdev)) 2023 if (netif_running(netdev))
2010 ixgbe_reinit_locked(adapter); 2024 ixgbe_reinit_locked(adapter);
2011 else 2025 else
diff --git a/drivers/net/ixgbe/ixgbe_fcoe.c b/drivers/net/ixgbe/ixgbe_fcoe.c
index fa9f24e23683..28cf104e36cc 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ixgbe/ixgbe_fcoe.c
@@ -336,7 +336,7 @@ int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
336 /* return 0 to bypass going to ULD for DDPed data */ 336 /* return 0 to bypass going to ULD for DDPed data */
337 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP) 337 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP)
338 rc = 0; 338 rc = 0;
339 else 339 else if (ddp->len)
340 rc = ddp->len; 340 rc = ddp->len;
341 } 341 }
342 342
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 200454f30f6a..77b0381a2b5c 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -492,12 +492,12 @@ static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
492 492
493 skb_record_rx_queue(skb, ring->queue_index); 493 skb_record_rx_queue(skb, ring->queue_index);
494 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { 494 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
495 if (adapter->vlgrp && is_vlan && (tag != 0)) 495 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
496 vlan_gro_receive(napi, adapter->vlgrp, tag, skb); 496 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
497 else 497 else
498 napi_gro_receive(napi, skb); 498 napi_gro_receive(napi, skb);
499 } else { 499 } else {
500 if (adapter->vlgrp && is_vlan && (tag != 0)) 500 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
501 vlan_hwaccel_rx(skb, adapter->vlgrp, tag); 501 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
502 else 502 else
503 netif_rx(skb); 503 netif_rx(skb);
@@ -585,7 +585,7 @@ static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
585 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); 585 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
586 586
587 if (!bi->page_dma && 587 if (!bi->page_dma &&
588 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { 588 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
589 if (!bi->page) { 589 if (!bi->page) {
590 bi->page = alloc_page(GFP_ATOMIC); 590 bi->page = alloc_page(GFP_ATOMIC);
591 if (!bi->page) { 591 if (!bi->page) {
@@ -629,7 +629,7 @@ static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
629 } 629 }
630 /* Refresh the desc even if buffer_addrs didn't change because 630 /* Refresh the desc even if buffer_addrs didn't change because
631 * each write-back erases this info. */ 631 * each write-back erases this info. */
632 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { 632 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
633 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); 633 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
634 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); 634 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
635 } else { 635 } else {
@@ -726,7 +726,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
726 break; 726 break;
727 (*work_done)++; 727 (*work_done)++;
728 728
729 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { 729 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
730 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); 730 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
731 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> 731 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
732 IXGBE_RXDADV_HDRBUFLEN_SHIFT; 732 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
@@ -780,7 +780,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
780 prefetch(next_rxd); 780 prefetch(next_rxd);
781 cleaned_count++; 781 cleaned_count++;
782 782
783 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE) 783 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
784 rsc_count = ixgbe_get_rsc_count(rx_desc); 784 rsc_count = ixgbe_get_rsc_count(rx_desc);
785 785
786 if (rsc_count) { 786 if (rsc_count) {
@@ -798,7 +798,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
798 rx_ring->stats.packets++; 798 rx_ring->stats.packets++;
799 rx_ring->stats.bytes += skb->len; 799 rx_ring->stats.bytes += skb->len;
800 } else { 800 } else {
801 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { 801 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
802 rx_buffer_info->skb = next_buffer->skb; 802 rx_buffer_info->skb = next_buffer->skb;
803 rx_buffer_info->dma = next_buffer->dma; 803 rx_buffer_info->dma = next_buffer->dma;
804 next_buffer->skb = skb; 804 next_buffer->skb = skb;
@@ -1898,46 +1898,19 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1898 1898
1899#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 1899#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1900 1900
1901static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) 1901static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1902 struct ixgbe_ring *rx_ring)
1902{ 1903{
1903 struct ixgbe_ring *rx_ring;
1904 u32 srrctl; 1904 u32 srrctl;
1905 int queue0 = 0; 1905 int index;
1906 unsigned long mask;
1907 struct ixgbe_ring_feature *feature = adapter->ring_feature; 1906 struct ixgbe_ring_feature *feature = adapter->ring_feature;
1908 1907
1909 if (adapter->hw.mac.type == ixgbe_mac_82599EB) { 1908 index = rx_ring->reg_idx;
1910 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { 1909 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1911 int dcb_i = feature[RING_F_DCB].indices; 1910 unsigned long mask;
1912 if (dcb_i == 8)
1913 queue0 = index >> 4;
1914 else if (dcb_i == 4)
1915 queue0 = index >> 5;
1916 else
1917 dev_err(&adapter->pdev->dev, "Invalid DCB "
1918 "configuration\n");
1919#ifdef IXGBE_FCOE
1920 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1921 struct ixgbe_ring_feature *f;
1922
1923 rx_ring = &adapter->rx_ring[queue0];
1924 f = &adapter->ring_feature[RING_F_FCOE];
1925 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1926 queue0 = f->mask + index -
1927 rx_ring->reg_idx - 1;
1928 }
1929#endif /* IXGBE_FCOE */
1930 } else {
1931 queue0 = index;
1932 }
1933 } else {
1934 mask = (unsigned long) feature[RING_F_RSS].mask; 1911 mask = (unsigned long) feature[RING_F_RSS].mask;
1935 queue0 = index & mask;
1936 index = index & mask; 1912 index = index & mask;
1937 } 1913 }
1938
1939 rx_ring = &adapter->rx_ring[queue0];
1940
1941 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); 1914 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1942 1915
1943 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; 1916 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
@@ -1946,7 +1919,7 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1946 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & 1919 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1947 IXGBE_SRRCTL_BSIZEHDR_MASK; 1920 IXGBE_SRRCTL_BSIZEHDR_MASK;
1948 1921
1949 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { 1922 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1950#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER 1923#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1951 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 1924 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1952#else 1925#else
@@ -2002,6 +1975,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2002{ 1975{
2003 u64 rdba; 1976 u64 rdba;
2004 struct ixgbe_hw *hw = &adapter->hw; 1977 struct ixgbe_hw *hw = &adapter->hw;
1978 struct ixgbe_ring *rx_ring;
2005 struct net_device *netdev = adapter->netdev; 1979 struct net_device *netdev = adapter->netdev;
2006 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 1980 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2007 int i, j; 1981 int i, j;
@@ -2018,11 +1992,6 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2018 /* Decide whether to use packet split mode or not */ 1992 /* Decide whether to use packet split mode or not */
2019 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; 1993 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2020 1994
2021#ifdef IXGBE_FCOE
2022 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2023 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2024#endif /* IXGBE_FCOE */
2025
2026 /* Set the RX buffer length according to the mode */ 1995 /* Set the RX buffer length according to the mode */
2027 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { 1996 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2028 rx_buf_len = IXGBE_RX_HDR_SIZE; 1997 rx_buf_len = IXGBE_RX_HDR_SIZE;
@@ -2036,7 +2005,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2036 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); 2005 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2037 } 2006 }
2038 } else { 2007 } else {
2039 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) && 2008 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2040 (netdev->mtu <= ETH_DATA_LEN)) 2009 (netdev->mtu <= ETH_DATA_LEN))
2041 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; 2010 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2042 else 2011 else
@@ -2070,29 +2039,35 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2070 * the Base and Length of the Rx Descriptor Ring 2039 * the Base and Length of the Rx Descriptor Ring
2071 */ 2040 */
2072 for (i = 0; i < adapter->num_rx_queues; i++) { 2041 for (i = 0; i < adapter->num_rx_queues; i++) {
2073 rdba = adapter->rx_ring[i].dma; 2042 rx_ring = &adapter->rx_ring[i];
2074 j = adapter->rx_ring[i].reg_idx; 2043 rdba = rx_ring->dma;
2044 j = rx_ring->reg_idx;
2075 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); 2045 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2076 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); 2046 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2077 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); 2047 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2078 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); 2048 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2079 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); 2049 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2080 adapter->rx_ring[i].head = IXGBE_RDH(j); 2050 rx_ring->head = IXGBE_RDH(j);
2081 adapter->rx_ring[i].tail = IXGBE_RDT(j); 2051 rx_ring->tail = IXGBE_RDT(j);
2082 adapter->rx_ring[i].rx_buf_len = rx_buf_len; 2052 rx_ring->rx_buf_len = rx_buf_len;
2053
2054 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2055 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2083 2056
2084#ifdef IXGBE_FCOE 2057#ifdef IXGBE_FCOE
2085 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 2058 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2086 struct ixgbe_ring_feature *f; 2059 struct ixgbe_ring_feature *f;
2087 f = &adapter->ring_feature[RING_F_FCOE]; 2060 f = &adapter->ring_feature[RING_F_FCOE];
2088 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 2061 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2089 (i >= f->mask) && (i < f->mask + f->indices)) 2062 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2090 adapter->rx_ring[i].rx_buf_len = 2063 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2091 IXGBE_FCOE_JUMBO_FRAME_SIZE; 2064 rx_ring->rx_buf_len =
2065 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2066 }
2092 } 2067 }
2093 2068
2094#endif /* IXGBE_FCOE */ 2069#endif /* IXGBE_FCOE */
2095 ixgbe_configure_srrctl(adapter, j); 2070 ixgbe_configure_srrctl(adapter, rx_ring);
2096 } 2071 }
2097 2072
2098 if (hw->mac.type == ixgbe_mac_82598EB) { 2073 if (hw->mac.type == ixgbe_mac_82598EB) {
@@ -2165,10 +2140,11 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2165 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 2140 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2166 } 2141 }
2167 2142
2168 if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) { 2143 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2169 /* Enable 82599 HW-RSC */ 2144 /* Enable 82599 HW-RSC */
2170 for (i = 0; i < adapter->num_rx_queues; i++) { 2145 for (i = 0; i < adapter->num_rx_queues; i++) {
2171 j = adapter->rx_ring[i].reg_idx; 2146 rx_ring = &adapter->rx_ring[i];
2147 j = rx_ring->reg_idx;
2172 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); 2148 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2173 rscctrl |= IXGBE_RSCCTL_RSCEN; 2149 rscctrl |= IXGBE_RSCCTL_RSCEN;
2174 /* 2150 /*
@@ -2176,7 +2152,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2176 * total size of max desc * buf_len is not greater 2152 * total size of max desc * buf_len is not greater
2177 * than 65535 2153 * than 65535
2178 */ 2154 */
2179 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { 2155 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2180#if (MAX_SKB_FRAGS > 16) 2156#if (MAX_SKB_FRAGS > 16)
2181 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 2157 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2182#elif (MAX_SKB_FRAGS > 8) 2158#elif (MAX_SKB_FRAGS > 8)
@@ -3812,8 +3788,8 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3812 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; 3788 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3813 } else if (hw->mac.type == ixgbe_mac_82599EB) { 3789 } else if (hw->mac.type == ixgbe_mac_82599EB) {
3814 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; 3790 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3815 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE; 3791 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3816 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED; 3792 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3817 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 3793 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3818 adapter->ring_feature[RING_F_FDIR].indices = 3794 adapter->ring_feature[RING_F_FDIR].indices =
3819 IXGBE_MAX_FDIR_INDICES; 3795 IXGBE_MAX_FDIR_INDICES;
@@ -5360,12 +5336,19 @@ static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5360static void ixgbe_netpoll(struct net_device *netdev) 5336static void ixgbe_netpoll(struct net_device *netdev)
5361{ 5337{
5362 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5339 int i;
5363 5340
5364 disable_irq(adapter->pdev->irq);
5365 adapter->flags |= IXGBE_FLAG_IN_NETPOLL; 5341 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5366 ixgbe_intr(adapter->pdev->irq, netdev); 5342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5343 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5344 for (i = 0; i < num_q_vectors; i++) {
5345 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5346 ixgbe_msix_clean_many(0, q_vector);
5347 }
5348 } else {
5349 ixgbe_intr(adapter->pdev->irq, netdev);
5350 }
5367 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; 5351 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5368 enable_irq(adapter->pdev->irq);
5369} 5352}
5370#endif 5353#endif
5371 5354
@@ -5611,7 +5594,7 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
5611 if (pci_using_dac) 5594 if (pci_using_dac)
5612 netdev->features |= NETIF_F_HIGHDMA; 5595 netdev->features |= NETIF_F_HIGHDMA;
5613 5596
5614 if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) 5597 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5615 netdev->features |= NETIF_F_LRO; 5598 netdev->features |= NETIF_F_LRO;
5616 5599
5617 /* make sure the EEPROM is good */ 5600 /* make sure the EEPROM is good */
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index fa87309dc087..be90eb4575f6 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -718,6 +718,12 @@
718#define IXGBE_ECC_STATUS_82599 0x110E0 718#define IXGBE_ECC_STATUS_82599 0x110E0
719#define IXGBE_BAR_CTRL_82599 0x110F4 719#define IXGBE_BAR_CTRL_82599 0x110F4
720 720
721/* PCI Express Control */
722#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
723#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
724#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
725#define IXGBE_GCR_CAP_VER2 0x00040000
726
721/* Time Sync Registers */ 727/* Time Sync Registers */
722#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 728#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
723#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 729#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
@@ -1521,6 +1527,7 @@
1521 1527
1522/* PCI Bus Info */ 1528/* PCI Bus Info */
1523#define IXGBE_PCI_LINK_STATUS 0xB2 1529#define IXGBE_PCI_LINK_STATUS 0xB2
1530#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1524#define IXGBE_PCI_LINK_WIDTH 0x3F0 1531#define IXGBE_PCI_LINK_WIDTH 0x3F0
1525#define IXGBE_PCI_LINK_WIDTH_1 0x10 1532#define IXGBE_PCI_LINK_WIDTH_1 0x10
1526#define IXGBE_PCI_LINK_WIDTH_2 0x20 1533#define IXGBE_PCI_LINK_WIDTH_2 0x20
@@ -1531,6 +1538,7 @@
1531#define IXGBE_PCI_LINK_SPEED_5000 0x2 1538#define IXGBE_PCI_LINK_SPEED_5000 0x2
1532#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1539#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1533#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1540#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1541#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1534 1542
1535/* Number of 100 microseconds we wait for PCI Express master disable */ 1543/* Number of 100 microseconds we wait for PCI Express master disable */
1536#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1544#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800