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path: root/drivers/net/ixgbe/ixgbe_main.c
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Diffstat (limited to 'drivers/net/ixgbe/ixgbe_main.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c73
1 files changed, 40 insertions, 33 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 5d90f699fa78..c4e42075335a 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -2424,6 +2424,45 @@ static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2424 e_info(hw, "Legacy interrupt IVAR setup done\n"); 2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
2425} 2425}
2426 2426
2427static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2428{
2429 struct ixgbe_hw *hw = &adapter->hw;
2430 u32 rttdcs;
2431 u32 mask;
2432
2433 if (hw->mac.type == ixgbe_mac_82598EB)
2434 return;
2435
2436 /* disable the arbiter while setting MTQC */
2437 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441 /* set transmit pool layout */
2442 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2443 switch (adapter->flags & mask) {
2444
2445 case (IXGBE_FLAG_SRIOV_ENABLED):
2446 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2447 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2448 break;
2449
2450 case (IXGBE_FLAG_DCB_ENABLED):
2451 /* We enable 8 traffic classes, DCB only */
2452 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2453 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2454 break;
2455
2456 default:
2457 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2458 break;
2459 }
2460
2461 /* re-enable the arbiter */
2462 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2463 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2464}
2465
2427/** 2466/**
2428 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 2467 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2429 * @adapter: board private structure 2468 * @adapter: board private structure
@@ -2475,39 +2514,7 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2475 } 2514 }
2476 } 2515 }
2477 2516
2478 if (hw->mac.type == ixgbe_mac_82599EB) { 2517 ixgbe_setup_mtqc(adapter);
2479 u32 rttdcs;
2480 u32 mask;
2481
2482 /* disable the arbiter while setting MTQC */
2483 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2484 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2485 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2486
2487 /* set transmit pool layout */
2488 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2489 switch (adapter->flags & mask) {
2490
2491 case (IXGBE_FLAG_SRIOV_ENABLED):
2492 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2493 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2494 break;
2495
2496 case (IXGBE_FLAG_DCB_ENABLED):
2497 /* We enable 8 traffic classes, DCB only */
2498 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2499 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2500 break;
2501
2502 default:
2503 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2504 break;
2505 }
2506
2507 /* re-eable the arbiter */
2508 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2509 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2510 }
2511} 2518}
2512 2519
2513#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 2520#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2