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path: root/drivers/net/ixgbe/ixgbe_dcb_82598.c
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Diffstat (limited to 'drivers/net/ixgbe/ixgbe_dcb_82598.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.c44
1 files changed, 21 insertions, 23 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index c97cf9160dc0..1bc57e52cee3 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -233,21 +233,27 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
233 u32 reg, rx_pba_size; 233 u32 reg, rx_pba_size;
234 u8 i; 234 u8 i;
235 235
236 if (!pfc_en) 236 if (pfc_en) {
237 goto out; 237 /* Enable Transmit Priority Flow Control */
238 238 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
239 /* Enable Transmit Priority Flow Control */ 239 reg &= ~IXGBE_RMCS_TFCE_802_3X;
240 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 240 /* correct the reporting of our flow control status */
241 reg &= ~IXGBE_RMCS_TFCE_802_3X; 241 reg |= IXGBE_RMCS_TFCE_PRIORITY;
242 /* correct the reporting of our flow control status */ 242 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
243 reg |= IXGBE_RMCS_TFCE_PRIORITY; 243
244 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 244 /* Enable Receive Priority Flow Control */
245 245 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
246 /* Enable Receive Priority Flow Control */ 246 reg &= ~IXGBE_FCTRL_RFCE;
247 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 247 reg |= IXGBE_FCTRL_RPFCE;
248 reg &= ~IXGBE_FCTRL_RFCE; 248 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
249 reg |= IXGBE_FCTRL_RPFCE; 249
250 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 250 /* Configure pause time */
251 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
252 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
253
254 /* Configure flow control refresh threshold value */
255 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
256 }
251 257
252 /* 258 /*
253 * Configure flow control thresholds and enable priority flow control 259 * Configure flow control thresholds and enable priority flow control
@@ -273,14 +279,6 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
273 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 279 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
274 } 280 }
275 281
276 /* Configure pause time */
277 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
278 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
279
280 /* Configure flow control refresh threshold value */
281 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
282
283out:
284 return 0; 282 return 0;
285} 283}
286 284