diff options
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_common.c')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_common.c | 972 |
1 files changed, 637 insertions, 335 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index 9c0d0a1964eb..f67c68404bb3 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | 3 | Intel 10 Gigabit PCI Express Linux driver |
4 | Copyright(c) 1999 - 2007 Intel Corporation. | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms and conditions of the GNU General Public License, | 7 | under the terms and conditions of the GNU General Public License, |
@@ -20,7 +20,6 @@ | |||
20 | the file called "COPYING". | 20 | the file called "COPYING". |
21 | 21 | ||
22 | Contact Information: | 22 | Contact Information: |
23 | Linux NICS <linux.nics@intel.com> | ||
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
26 | 25 | ||
@@ -33,20 +32,28 @@ | |||
33 | #include "ixgbe_common.h" | 32 | #include "ixgbe_common.h" |
34 | #include "ixgbe_phy.h" | 33 | #include "ixgbe_phy.h" |
35 | 34 | ||
36 | static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw); | ||
37 | |||
38 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); | 35 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); |
36 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); | ||
39 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); | 37 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); |
40 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); | 38 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); |
39 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); | ||
40 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); | ||
41 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | ||
42 | u16 count); | ||
43 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); | ||
44 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | ||
45 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | ||
46 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw); | ||
41 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); | 47 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); |
42 | 48 | ||
43 | static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw); | 49 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); |
44 | static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw); | 50 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); |
45 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); | 51 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); |
46 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); | 52 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); |
53 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); | ||
47 | 54 | ||
48 | /** | 55 | /** |
49 | * ixgbe_start_hw - Prepare hardware for TX/RX | 56 | * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx |
50 | * @hw: pointer to hardware structure | 57 | * @hw: pointer to hardware structure |
51 | * | 58 | * |
52 | * Starts the hardware by filling the bus info structure and media type, clears | 59 | * Starts the hardware by filling the bus info structure and media type, clears |
@@ -54,7 +61,7 @@ static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); | |||
54 | * table, VLAN filter table, calls routine to set up link and flow control | 61 | * table, VLAN filter table, calls routine to set up link and flow control |
55 | * settings, and leaves transmit and receive units disabled and uninitialized | 62 | * settings, and leaves transmit and receive units disabled and uninitialized |
56 | **/ | 63 | **/ |
57 | s32 ixgbe_start_hw(struct ixgbe_hw *hw) | 64 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) |
58 | { | 65 | { |
59 | u32 ctrl_ext; | 66 | u32 ctrl_ext; |
60 | 67 | ||
@@ -62,22 +69,22 @@ s32 ixgbe_start_hw(struct ixgbe_hw *hw) | |||
62 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); | 69 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); |
63 | 70 | ||
64 | /* Identify the PHY */ | 71 | /* Identify the PHY */ |
65 | ixgbe_identify_phy(hw); | 72 | hw->phy.ops.identify(hw); |
66 | 73 | ||
67 | /* | 74 | /* |
68 | * Store MAC address from RAR0, clear receive address registers, and | 75 | * Store MAC address from RAR0, clear receive address registers, and |
69 | * clear the multicast table | 76 | * clear the multicast table |
70 | */ | 77 | */ |
71 | ixgbe_init_rx_addrs(hw); | 78 | hw->mac.ops.init_rx_addrs(hw); |
72 | 79 | ||
73 | /* Clear the VLAN filter table */ | 80 | /* Clear the VLAN filter table */ |
74 | ixgbe_clear_vfta(hw); | 81 | hw->mac.ops.clear_vfta(hw); |
75 | 82 | ||
76 | /* Set up link */ | 83 | /* Set up link */ |
77 | hw->mac.ops.setup_link(hw); | 84 | hw->mac.ops.setup_link(hw); |
78 | 85 | ||
79 | /* Clear statistics registers */ | 86 | /* Clear statistics registers */ |
80 | ixgbe_clear_hw_cntrs(hw); | 87 | hw->mac.ops.clear_hw_cntrs(hw); |
81 | 88 | ||
82 | /* Set No Snoop Disable */ | 89 | /* Set No Snoop Disable */ |
83 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | 90 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); |
@@ -92,34 +99,34 @@ s32 ixgbe_start_hw(struct ixgbe_hw *hw) | |||
92 | } | 99 | } |
93 | 100 | ||
94 | /** | 101 | /** |
95 | * ixgbe_init_hw - Generic hardware initialization | 102 | * ixgbe_init_hw_generic - Generic hardware initialization |
96 | * @hw: pointer to hardware structure | 103 | * @hw: pointer to hardware structure |
97 | * | 104 | * |
98 | * Initialize the hardware by reseting the hardware, filling the bus info | 105 | * Initialize the hardware by resetting the hardware, filling the bus info |
99 | * structure and media type, clears all on chip counters, initializes receive | 106 | * structure and media type, clears all on chip counters, initializes receive |
100 | * address registers, multicast table, VLAN filter table, calls routine to set | 107 | * address registers, multicast table, VLAN filter table, calls routine to set |
101 | * up link and flow control settings, and leaves transmit and receive units | 108 | * up link and flow control settings, and leaves transmit and receive units |
102 | * disabled and uninitialized | 109 | * disabled and uninitialized |
103 | **/ | 110 | **/ |
104 | s32 ixgbe_init_hw(struct ixgbe_hw *hw) | 111 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) |
105 | { | 112 | { |
106 | /* Reset the hardware */ | 113 | /* Reset the hardware */ |
107 | hw->mac.ops.reset(hw); | 114 | hw->mac.ops.reset_hw(hw); |
108 | 115 | ||
109 | /* Start the HW */ | 116 | /* Start the HW */ |
110 | ixgbe_start_hw(hw); | 117 | hw->mac.ops.start_hw(hw); |
111 | 118 | ||
112 | return 0; | 119 | return 0; |
113 | } | 120 | } |
114 | 121 | ||
115 | /** | 122 | /** |
116 | * ixgbe_clear_hw_cntrs - Generic clear hardware counters | 123 | * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters |
117 | * @hw: pointer to hardware structure | 124 | * @hw: pointer to hardware structure |
118 | * | 125 | * |
119 | * Clears all hardware statistics counters by reading them from the hardware | 126 | * Clears all hardware statistics counters by reading them from the hardware |
120 | * Statistics counters are clear on read. | 127 | * Statistics counters are clear on read. |
121 | **/ | 128 | **/ |
122 | static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) | 129 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) |
123 | { | 130 | { |
124 | u16 i = 0; | 131 | u16 i = 0; |
125 | 132 | ||
@@ -191,7 +198,36 @@ static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) | |||
191 | } | 198 | } |
192 | 199 | ||
193 | /** | 200 | /** |
194 | * ixgbe_get_mac_addr - Generic get MAC address | 201 | * ixgbe_read_pba_num_generic - Reads part number from EEPROM |
202 | * @hw: pointer to hardware structure | ||
203 | * @pba_num: stores the part number from the EEPROM | ||
204 | * | ||
205 | * Reads the part number from the EEPROM. | ||
206 | **/ | ||
207 | s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) | ||
208 | { | ||
209 | s32 ret_val; | ||
210 | u16 data; | ||
211 | |||
212 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); | ||
213 | if (ret_val) { | ||
214 | hw_dbg(hw, "NVM Read Error\n"); | ||
215 | return ret_val; | ||
216 | } | ||
217 | *pba_num = (u32)(data << 16); | ||
218 | |||
219 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); | ||
220 | if (ret_val) { | ||
221 | hw_dbg(hw, "NVM Read Error\n"); | ||
222 | return ret_val; | ||
223 | } | ||
224 | *pba_num |= data; | ||
225 | |||
226 | return 0; | ||
227 | } | ||
228 | |||
229 | /** | ||
230 | * ixgbe_get_mac_addr_generic - Generic get MAC address | ||
195 | * @hw: pointer to hardware structure | 231 | * @hw: pointer to hardware structure |
196 | * @mac_addr: Adapter MAC address | 232 | * @mac_addr: Adapter MAC address |
197 | * | 233 | * |
@@ -199,7 +235,7 @@ static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) | |||
199 | * A reset of the adapter must be performed prior to calling this function | 235 | * A reset of the adapter must be performed prior to calling this function |
200 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 | 236 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 |
201 | **/ | 237 | **/ |
202 | s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) | 238 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) |
203 | { | 239 | { |
204 | u32 rar_high; | 240 | u32 rar_high; |
205 | u32 rar_low; | 241 | u32 rar_low; |
@@ -217,30 +253,8 @@ s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) | |||
217 | return 0; | 253 | return 0; |
218 | } | 254 | } |
219 | 255 | ||
220 | s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num) | ||
221 | { | ||
222 | s32 ret_val; | ||
223 | u16 data; | ||
224 | |||
225 | ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM0_PTR, &data); | ||
226 | if (ret_val) { | ||
227 | hw_dbg(hw, "NVM Read Error\n"); | ||
228 | return ret_val; | ||
229 | } | ||
230 | *part_num = (u32)(data << 16); | ||
231 | |||
232 | ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM1_PTR, &data); | ||
233 | if (ret_val) { | ||
234 | hw_dbg(hw, "NVM Read Error\n"); | ||
235 | return ret_val; | ||
236 | } | ||
237 | *part_num |= data; | ||
238 | |||
239 | return 0; | ||
240 | } | ||
241 | |||
242 | /** | 256 | /** |
243 | * ixgbe_stop_adapter - Generic stop TX/RX units | 257 | * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units |
244 | * @hw: pointer to hardware structure | 258 | * @hw: pointer to hardware structure |
245 | * | 259 | * |
246 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, | 260 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, |
@@ -248,7 +262,7 @@ s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num) | |||
248 | * the shared code and drivers to determine if the adapter is in a stopped | 262 | * the shared code and drivers to determine if the adapter is in a stopped |
249 | * state and should not touch the hardware. | 263 | * state and should not touch the hardware. |
250 | **/ | 264 | **/ |
251 | s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) | 265 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) |
252 | { | 266 | { |
253 | u32 number_of_queues; | 267 | u32 number_of_queues; |
254 | u32 reg_val; | 268 | u32 reg_val; |
@@ -264,6 +278,7 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) | |||
264 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | 278 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
265 | reg_val &= ~(IXGBE_RXCTRL_RXEN); | 279 | reg_val &= ~(IXGBE_RXCTRL_RXEN); |
266 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); | 280 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); |
281 | IXGBE_WRITE_FLUSH(hw); | ||
267 | msleep(2); | 282 | msleep(2); |
268 | 283 | ||
269 | /* Clear interrupt mask to stop from interrupts being generated */ | 284 | /* Clear interrupt mask to stop from interrupts being generated */ |
@@ -273,7 +288,7 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) | |||
273 | IXGBE_READ_REG(hw, IXGBE_EICR); | 288 | IXGBE_READ_REG(hw, IXGBE_EICR); |
274 | 289 | ||
275 | /* Disable the transmit unit. Each queue must be disabled. */ | 290 | /* Disable the transmit unit. Each queue must be disabled. */ |
276 | number_of_queues = hw->mac.num_tx_queues; | 291 | number_of_queues = hw->mac.max_tx_queues; |
277 | for (i = 0; i < number_of_queues; i++) { | 292 | for (i = 0; i < number_of_queues; i++) { |
278 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | 293 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); |
279 | if (reg_val & IXGBE_TXDCTL_ENABLE) { | 294 | if (reg_val & IXGBE_TXDCTL_ENABLE) { |
@@ -282,15 +297,22 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) | |||
282 | } | 297 | } |
283 | } | 298 | } |
284 | 299 | ||
300 | /* | ||
301 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | ||
302 | * access and verify no pending requests | ||
303 | */ | ||
304 | if (ixgbe_disable_pcie_master(hw) != 0) | ||
305 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | ||
306 | |||
285 | return 0; | 307 | return 0; |
286 | } | 308 | } |
287 | 309 | ||
288 | /** | 310 | /** |
289 | * ixgbe_led_on - Turns on the software controllable LEDs. | 311 | * ixgbe_led_on_generic - Turns on the software controllable LEDs. |
290 | * @hw: pointer to hardware structure | 312 | * @hw: pointer to hardware structure |
291 | * @index: led number to turn on | 313 | * @index: led number to turn on |
292 | **/ | 314 | **/ |
293 | s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) | 315 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) |
294 | { | 316 | { |
295 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | 317 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
296 | 318 | ||
@@ -304,11 +326,11 @@ s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) | |||
304 | } | 326 | } |
305 | 327 | ||
306 | /** | 328 | /** |
307 | * ixgbe_led_off - Turns off the software controllable LEDs. | 329 | * ixgbe_led_off_generic - Turns off the software controllable LEDs. |
308 | * @hw: pointer to hardware structure | 330 | * @hw: pointer to hardware structure |
309 | * @index: led number to turn off | 331 | * @index: led number to turn off |
310 | **/ | 332 | **/ |
311 | s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) | 333 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) |
312 | { | 334 | { |
313 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | 335 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
314 | 336 | ||
@@ -321,15 +343,14 @@ s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) | |||
321 | return 0; | 343 | return 0; |
322 | } | 344 | } |
323 | 345 | ||
324 | |||
325 | /** | 346 | /** |
326 | * ixgbe_init_eeprom - Initialize EEPROM params | 347 | * ixgbe_init_eeprom_params_generic - Initialize EEPROM params |
327 | * @hw: pointer to hardware structure | 348 | * @hw: pointer to hardware structure |
328 | * | 349 | * |
329 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | 350 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the |
330 | * ixgbe_hw struct in order to set up EEPROM access. | 351 | * ixgbe_hw struct in order to set up EEPROM access. |
331 | **/ | 352 | **/ |
332 | s32 ixgbe_init_eeprom(struct ixgbe_hw *hw) | 353 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) |
333 | { | 354 | { |
334 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | 355 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; |
335 | u32 eec; | 356 | u32 eec; |
@@ -337,6 +358,9 @@ s32 ixgbe_init_eeprom(struct ixgbe_hw *hw) | |||
337 | 358 | ||
338 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | 359 | if (eeprom->type == ixgbe_eeprom_uninitialized) { |
339 | eeprom->type = ixgbe_eeprom_none; | 360 | eeprom->type = ixgbe_eeprom_none; |
361 | /* Set default semaphore delay to 10ms which is a well | ||
362 | * tested value */ | ||
363 | eeprom->semaphore_delay = 10; | ||
340 | 364 | ||
341 | /* | 365 | /* |
342 | * Check for EEPROM present first. | 366 | * Check for EEPROM present first. |
@@ -369,18 +393,85 @@ s32 ixgbe_init_eeprom(struct ixgbe_hw *hw) | |||
369 | } | 393 | } |
370 | 394 | ||
371 | /** | 395 | /** |
372 | * ixgbe_read_eeprom - Read EEPROM word using EERD | 396 | * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang |
397 | * @hw: pointer to hardware structure | ||
398 | * @offset: offset within the EEPROM to be read | ||
399 | * @data: read 16 bit value from EEPROM | ||
400 | * | ||
401 | * Reads 16 bit value from EEPROM through bit-bang method | ||
402 | **/ | ||
403 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, | ||
404 | u16 *data) | ||
405 | { | ||
406 | s32 status; | ||
407 | u16 word_in; | ||
408 | u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; | ||
409 | |||
410 | hw->eeprom.ops.init_params(hw); | ||
411 | |||
412 | if (offset >= hw->eeprom.word_size) { | ||
413 | status = IXGBE_ERR_EEPROM; | ||
414 | goto out; | ||
415 | } | ||
416 | |||
417 | /* Prepare the EEPROM for reading */ | ||
418 | status = ixgbe_acquire_eeprom(hw); | ||
419 | |||
420 | if (status == 0) { | ||
421 | if (ixgbe_ready_eeprom(hw) != 0) { | ||
422 | ixgbe_release_eeprom(hw); | ||
423 | status = IXGBE_ERR_EEPROM; | ||
424 | } | ||
425 | } | ||
426 | |||
427 | if (status == 0) { | ||
428 | ixgbe_standby_eeprom(hw); | ||
429 | |||
430 | /* | ||
431 | * Some SPI eeproms use the 8th address bit embedded in the | ||
432 | * opcode | ||
433 | */ | ||
434 | if ((hw->eeprom.address_bits == 8) && (offset >= 128)) | ||
435 | read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | ||
436 | |||
437 | /* Send the READ command (opcode + addr) */ | ||
438 | ixgbe_shift_out_eeprom_bits(hw, read_opcode, | ||
439 | IXGBE_EEPROM_OPCODE_BITS); | ||
440 | ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), | ||
441 | hw->eeprom.address_bits); | ||
442 | |||
443 | /* Read the data. */ | ||
444 | word_in = ixgbe_shift_in_eeprom_bits(hw, 16); | ||
445 | *data = (word_in >> 8) | (word_in << 8); | ||
446 | |||
447 | /* End this read operation */ | ||
448 | ixgbe_release_eeprom(hw); | ||
449 | } | ||
450 | |||
451 | out: | ||
452 | return status; | ||
453 | } | ||
454 | |||
455 | /** | ||
456 | * ixgbe_read_eeprom_generic - Read EEPROM word using EERD | ||
373 | * @hw: pointer to hardware structure | 457 | * @hw: pointer to hardware structure |
374 | * @offset: offset of word in the EEPROM to read | 458 | * @offset: offset of word in the EEPROM to read |
375 | * @data: word read from the EEPROM | 459 | * @data: word read from the EEPROM |
376 | * | 460 | * |
377 | * Reads a 16 bit word from the EEPROM using the EERD register. | 461 | * Reads a 16 bit word from the EEPROM using the EERD register. |
378 | **/ | 462 | **/ |
379 | s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) | 463 | s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) |
380 | { | 464 | { |
381 | u32 eerd; | 465 | u32 eerd; |
382 | s32 status; | 466 | s32 status; |
383 | 467 | ||
468 | hw->eeprom.ops.init_params(hw); | ||
469 | |||
470 | if (offset >= hw->eeprom.word_size) { | ||
471 | status = IXGBE_ERR_EEPROM; | ||
472 | goto out; | ||
473 | } | ||
474 | |||
384 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + | 475 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + |
385 | IXGBE_EEPROM_READ_REG_START; | 476 | IXGBE_EEPROM_READ_REG_START; |
386 | 477 | ||
@@ -389,10 +480,11 @@ s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) | |||
389 | 480 | ||
390 | if (status == 0) | 481 | if (status == 0) |
391 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> | 482 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> |
392 | IXGBE_EEPROM_READ_REG_DATA); | 483 | IXGBE_EEPROM_READ_REG_DATA); |
393 | else | 484 | else |
394 | hw_dbg(hw, "Eeprom read timed out\n"); | 485 | hw_dbg(hw, "Eeprom read timed out\n"); |
395 | 486 | ||
487 | out: | ||
396 | return status; | 488 | return status; |
397 | } | 489 | } |
398 | 490 | ||
@@ -420,6 +512,58 @@ static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) | |||
420 | } | 512 | } |
421 | 513 | ||
422 | /** | 514 | /** |
515 | * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang | ||
516 | * @hw: pointer to hardware structure | ||
517 | * | ||
518 | * Prepares EEPROM for access using bit-bang method. This function should | ||
519 | * be called before issuing a command to the EEPROM. | ||
520 | **/ | ||
521 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) | ||
522 | { | ||
523 | s32 status = 0; | ||
524 | u32 eec; | ||
525 | u32 i; | ||
526 | |||
527 | if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) | ||
528 | status = IXGBE_ERR_SWFW_SYNC; | ||
529 | |||
530 | if (status == 0) { | ||
531 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
532 | |||
533 | /* Request EEPROM Access */ | ||
534 | eec |= IXGBE_EEC_REQ; | ||
535 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
536 | |||
537 | for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { | ||
538 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
539 | if (eec & IXGBE_EEC_GNT) | ||
540 | break; | ||
541 | udelay(5); | ||
542 | } | ||
543 | |||
544 | /* Release if grant not acquired */ | ||
545 | if (!(eec & IXGBE_EEC_GNT)) { | ||
546 | eec &= ~IXGBE_EEC_REQ; | ||
547 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
548 | hw_dbg(hw, "Could not acquire EEPROM grant\n"); | ||
549 | |||
550 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | ||
551 | status = IXGBE_ERR_EEPROM; | ||
552 | } | ||
553 | } | ||
554 | |||
555 | /* Setup EEPROM for Read/Write */ | ||
556 | if (status == 0) { | ||
557 | /* Clear CS and SK */ | ||
558 | eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); | ||
559 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
560 | IXGBE_WRITE_FLUSH(hw); | ||
561 | udelay(1); | ||
562 | } | ||
563 | return status; | ||
564 | } | ||
565 | |||
566 | /** | ||
423 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore | 567 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore |
424 | * @hw: pointer to hardware structure | 568 | * @hw: pointer to hardware structure |
425 | * | 569 | * |
@@ -475,7 +619,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) | |||
475 | */ | 619 | */ |
476 | if (i >= timeout) { | 620 | if (i >= timeout) { |
477 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " | 621 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " |
478 | "not granted.\n"); | 622 | "not granted.\n"); |
479 | ixgbe_release_eeprom_semaphore(hw); | 623 | ixgbe_release_eeprom_semaphore(hw); |
480 | status = IXGBE_ERR_EEPROM; | 624 | status = IXGBE_ERR_EEPROM; |
481 | } | 625 | } |
@@ -503,6 +647,217 @@ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) | |||
503 | } | 647 | } |
504 | 648 | ||
505 | /** | 649 | /** |
650 | * ixgbe_ready_eeprom - Polls for EEPROM ready | ||
651 | * @hw: pointer to hardware structure | ||
652 | **/ | ||
653 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) | ||
654 | { | ||
655 | s32 status = 0; | ||
656 | u16 i; | ||
657 | u8 spi_stat_reg; | ||
658 | |||
659 | /* | ||
660 | * Read "Status Register" repeatedly until the LSB is cleared. The | ||
661 | * EEPROM will signal that the command has been completed by clearing | ||
662 | * bit 0 of the internal status register. If it's not cleared within | ||
663 | * 5 milliseconds, then error out. | ||
664 | */ | ||
665 | for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { | ||
666 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, | ||
667 | IXGBE_EEPROM_OPCODE_BITS); | ||
668 | spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); | ||
669 | if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) | ||
670 | break; | ||
671 | |||
672 | udelay(5); | ||
673 | ixgbe_standby_eeprom(hw); | ||
674 | }; | ||
675 | |||
676 | /* | ||
677 | * On some parts, SPI write time could vary from 0-20mSec on 3.3V | ||
678 | * devices (and only 0-5mSec on 5V devices) | ||
679 | */ | ||
680 | if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { | ||
681 | hw_dbg(hw, "SPI EEPROM Status error\n"); | ||
682 | status = IXGBE_ERR_EEPROM; | ||
683 | } | ||
684 | |||
685 | return status; | ||
686 | } | ||
687 | |||
688 | /** | ||
689 | * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state | ||
690 | * @hw: pointer to hardware structure | ||
691 | **/ | ||
692 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) | ||
693 | { | ||
694 | u32 eec; | ||
695 | |||
696 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
697 | |||
698 | /* Toggle CS to flush commands */ | ||
699 | eec |= IXGBE_EEC_CS; | ||
700 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
701 | IXGBE_WRITE_FLUSH(hw); | ||
702 | udelay(1); | ||
703 | eec &= ~IXGBE_EEC_CS; | ||
704 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
705 | IXGBE_WRITE_FLUSH(hw); | ||
706 | udelay(1); | ||
707 | } | ||
708 | |||
709 | /** | ||
710 | * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. | ||
711 | * @hw: pointer to hardware structure | ||
712 | * @data: data to send to the EEPROM | ||
713 | * @count: number of bits to shift out | ||
714 | **/ | ||
715 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | ||
716 | u16 count) | ||
717 | { | ||
718 | u32 eec; | ||
719 | u32 mask; | ||
720 | u32 i; | ||
721 | |||
722 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
723 | |||
724 | /* | ||
725 | * Mask is used to shift "count" bits of "data" out to the EEPROM | ||
726 | * one bit at a time. Determine the starting bit based on count | ||
727 | */ | ||
728 | mask = 0x01 << (count - 1); | ||
729 | |||
730 | for (i = 0; i < count; i++) { | ||
731 | /* | ||
732 | * A "1" is shifted out to the EEPROM by setting bit "DI" to a | ||
733 | * "1", and then raising and then lowering the clock (the SK | ||
734 | * bit controls the clock input to the EEPROM). A "0" is | ||
735 | * shifted out to the EEPROM by setting "DI" to "0" and then | ||
736 | * raising and then lowering the clock. | ||
737 | */ | ||
738 | if (data & mask) | ||
739 | eec |= IXGBE_EEC_DI; | ||
740 | else | ||
741 | eec &= ~IXGBE_EEC_DI; | ||
742 | |||
743 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
744 | IXGBE_WRITE_FLUSH(hw); | ||
745 | |||
746 | udelay(1); | ||
747 | |||
748 | ixgbe_raise_eeprom_clk(hw, &eec); | ||
749 | ixgbe_lower_eeprom_clk(hw, &eec); | ||
750 | |||
751 | /* | ||
752 | * Shift mask to signify next bit of data to shift in to the | ||
753 | * EEPROM | ||
754 | */ | ||
755 | mask = mask >> 1; | ||
756 | }; | ||
757 | |||
758 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | ||
759 | eec &= ~IXGBE_EEC_DI; | ||
760 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
761 | IXGBE_WRITE_FLUSH(hw); | ||
762 | } | ||
763 | |||
764 | /** | ||
765 | * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM | ||
766 | * @hw: pointer to hardware structure | ||
767 | **/ | ||
768 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) | ||
769 | { | ||
770 | u32 eec; | ||
771 | u32 i; | ||
772 | u16 data = 0; | ||
773 | |||
774 | /* | ||
775 | * In order to read a register from the EEPROM, we need to shift | ||
776 | * 'count' bits in from the EEPROM. Bits are "shifted in" by raising | ||
777 | * the clock input to the EEPROM (setting the SK bit), and then reading | ||
778 | * the value of the "DO" bit. During this "shifting in" process the | ||
779 | * "DI" bit should always be clear. | ||
780 | */ | ||
781 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
782 | |||
783 | eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); | ||
784 | |||
785 | for (i = 0; i < count; i++) { | ||
786 | data = data << 1; | ||
787 | ixgbe_raise_eeprom_clk(hw, &eec); | ||
788 | |||
789 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
790 | |||
791 | eec &= ~(IXGBE_EEC_DI); | ||
792 | if (eec & IXGBE_EEC_DO) | ||
793 | data |= 1; | ||
794 | |||
795 | ixgbe_lower_eeprom_clk(hw, &eec); | ||
796 | } | ||
797 | |||
798 | return data; | ||
799 | } | ||
800 | |||
801 | /** | ||
802 | * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. | ||
803 | * @hw: pointer to hardware structure | ||
804 | * @eec: EEC register's current value | ||
805 | **/ | ||
806 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | ||
807 | { | ||
808 | /* | ||
809 | * Raise the clock input to the EEPROM | ||
810 | * (setting the SK bit), then delay | ||
811 | */ | ||
812 | *eec = *eec | IXGBE_EEC_SK; | ||
813 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | ||
814 | IXGBE_WRITE_FLUSH(hw); | ||
815 | udelay(1); | ||
816 | } | ||
817 | |||
818 | /** | ||
819 | * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. | ||
820 | * @hw: pointer to hardware structure | ||
821 | * @eecd: EECD's current value | ||
822 | **/ | ||
823 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | ||
824 | { | ||
825 | /* | ||
826 | * Lower the clock input to the EEPROM (clearing the SK bit), then | ||
827 | * delay | ||
828 | */ | ||
829 | *eec = *eec & ~IXGBE_EEC_SK; | ||
830 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | ||
831 | IXGBE_WRITE_FLUSH(hw); | ||
832 | udelay(1); | ||
833 | } | ||
834 | |||
835 | /** | ||
836 | * ixgbe_release_eeprom - Release EEPROM, release semaphores | ||
837 | * @hw: pointer to hardware structure | ||
838 | **/ | ||
839 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw) | ||
840 | { | ||
841 | u32 eec; | ||
842 | |||
843 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | ||
844 | |||
845 | eec |= IXGBE_EEC_CS; /* Pull CS high */ | ||
846 | eec &= ~IXGBE_EEC_SK; /* Lower SCK */ | ||
847 | |||
848 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
849 | IXGBE_WRITE_FLUSH(hw); | ||
850 | |||
851 | udelay(1); | ||
852 | |||
853 | /* Stop requesting EEPROM access */ | ||
854 | eec &= ~IXGBE_EEC_REQ; | ||
855 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | ||
856 | |||
857 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | ||
858 | } | ||
859 | |||
860 | /** | ||
506 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum | 861 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum |
507 | * @hw: pointer to hardware structure | 862 | * @hw: pointer to hardware structure |
508 | **/ | 863 | **/ |
@@ -517,7 +872,7 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) | |||
517 | 872 | ||
518 | /* Include 0x0-0x3F in the checksum */ | 873 | /* Include 0x0-0x3F in the checksum */ |
519 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | 874 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { |
520 | if (ixgbe_read_eeprom(hw, i, &word) != 0) { | 875 | if (hw->eeprom.ops.read(hw, i, &word) != 0) { |
521 | hw_dbg(hw, "EEPROM read failed\n"); | 876 | hw_dbg(hw, "EEPROM read failed\n"); |
522 | break; | 877 | break; |
523 | } | 878 | } |
@@ -526,15 +881,15 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) | |||
526 | 881 | ||
527 | /* Include all data from pointers except for the fw pointer */ | 882 | /* Include all data from pointers except for the fw pointer */ |
528 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | 883 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { |
529 | ixgbe_read_eeprom(hw, i, &pointer); | 884 | hw->eeprom.ops.read(hw, i, &pointer); |
530 | 885 | ||
531 | /* Make sure the pointer seems valid */ | 886 | /* Make sure the pointer seems valid */ |
532 | if (pointer != 0xFFFF && pointer != 0) { | 887 | if (pointer != 0xFFFF && pointer != 0) { |
533 | ixgbe_read_eeprom(hw, pointer, &length); | 888 | hw->eeprom.ops.read(hw, pointer, &length); |
534 | 889 | ||
535 | if (length != 0xFFFF && length != 0) { | 890 | if (length != 0xFFFF && length != 0) { |
536 | for (j = pointer+1; j <= pointer+length; j++) { | 891 | for (j = pointer+1; j <= pointer+length; j++) { |
537 | ixgbe_read_eeprom(hw, j, &word); | 892 | hw->eeprom.ops.read(hw, j, &word); |
538 | checksum += word; | 893 | checksum += word; |
539 | } | 894 | } |
540 | } | 895 | } |
@@ -547,14 +902,15 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) | |||
547 | } | 902 | } |
548 | 903 | ||
549 | /** | 904 | /** |
550 | * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum | 905 | * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum |
551 | * @hw: pointer to hardware structure | 906 | * @hw: pointer to hardware structure |
552 | * @checksum_val: calculated checksum | 907 | * @checksum_val: calculated checksum |
553 | * | 908 | * |
554 | * Performs checksum calculation and validates the EEPROM checksum. If the | 909 | * Performs checksum calculation and validates the EEPROM checksum. If the |
555 | * caller does not need checksum_val, the value can be NULL. | 910 | * caller does not need checksum_val, the value can be NULL. |
556 | **/ | 911 | **/ |
557 | s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) | 912 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
913 | u16 *checksum_val) | ||
558 | { | 914 | { |
559 | s32 status; | 915 | s32 status; |
560 | u16 checksum; | 916 | u16 checksum; |
@@ -565,12 +921,12 @@ s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) | |||
565 | * not continue or we could be in for a very long wait while every | 921 | * not continue or we could be in for a very long wait while every |
566 | * EEPROM read fails | 922 | * EEPROM read fails |
567 | */ | 923 | */ |
568 | status = ixgbe_read_eeprom(hw, 0, &checksum); | 924 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
569 | 925 | ||
570 | if (status == 0) { | 926 | if (status == 0) { |
571 | checksum = ixgbe_calc_eeprom_checksum(hw); | 927 | checksum = ixgbe_calc_eeprom_checksum(hw); |
572 | 928 | ||
573 | ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); | 929 | hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); |
574 | 930 | ||
575 | /* | 931 | /* |
576 | * Verify read checksum from EEPROM is the same as | 932 | * Verify read checksum from EEPROM is the same as |
@@ -590,6 +946,33 @@ s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) | |||
590 | } | 946 | } |
591 | 947 | ||
592 | /** | 948 | /** |
949 | * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum | ||
950 | * @hw: pointer to hardware structure | ||
951 | **/ | ||
952 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) | ||
953 | { | ||
954 | s32 status; | ||
955 | u16 checksum; | ||
956 | |||
957 | /* | ||
958 | * Read the first word from the EEPROM. If this times out or fails, do | ||
959 | * not continue or we could be in for a very long wait while every | ||
960 | * EEPROM read fails | ||
961 | */ | ||
962 | status = hw->eeprom.ops.read(hw, 0, &checksum); | ||
963 | |||
964 | if (status == 0) { | ||
965 | checksum = ixgbe_calc_eeprom_checksum(hw); | ||
966 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, | ||
967 | checksum); | ||
968 | } else { | ||
969 | hw_dbg(hw, "EEPROM read failed\n"); | ||
970 | } | ||
971 | |||
972 | return status; | ||
973 | } | ||
974 | |||
975 | /** | ||
593 | * ixgbe_validate_mac_addr - Validate MAC address | 976 | * ixgbe_validate_mac_addr - Validate MAC address |
594 | * @mac_addr: pointer to MAC address. | 977 | * @mac_addr: pointer to MAC address. |
595 | * | 978 | * |
@@ -607,58 +990,137 @@ s32 ixgbe_validate_mac_addr(u8 *mac_addr) | |||
607 | status = IXGBE_ERR_INVALID_MAC_ADDR; | 990 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
608 | /* Reject the zero address */ | 991 | /* Reject the zero address */ |
609 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && | 992 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && |
610 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) | 993 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) |
611 | status = IXGBE_ERR_INVALID_MAC_ADDR; | 994 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
612 | 995 | ||
613 | return status; | 996 | return status; |
614 | } | 997 | } |
615 | 998 | ||
616 | /** | 999 | /** |
617 | * ixgbe_set_rar - Set RX address register | 1000 | * ixgbe_set_rar_generic - Set Rx address register |
618 | * @hw: pointer to hardware structure | 1001 | * @hw: pointer to hardware structure |
619 | * @addr: Address to put into receive address register | ||
620 | * @index: Receive address register to write | 1002 | * @index: Receive address register to write |
621 | * @vind: Vind to set RAR to | 1003 | * @addr: Address to put into receive address register |
1004 | * @vmdq: VMDq "set" or "pool" index | ||
622 | * @enable_addr: set flag that address is active | 1005 | * @enable_addr: set flag that address is active |
623 | * | 1006 | * |
624 | * Puts an ethernet address into a receive address register. | 1007 | * Puts an ethernet address into a receive address register. |
625 | **/ | 1008 | **/ |
626 | s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind, | 1009 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, |
627 | u32 enable_addr) | 1010 | u32 enable_addr) |
628 | { | 1011 | { |
629 | u32 rar_low, rar_high; | 1012 | u32 rar_low, rar_high; |
1013 | u32 rar_entries = hw->mac.num_rar_entries; | ||
630 | 1014 | ||
631 | /* | 1015 | /* setup VMDq pool selection before this RAR gets enabled */ |
632 | * HW expects these in little endian so we reverse the byte order from | 1016 | hw->mac.ops.set_vmdq(hw, index, vmdq); |
633 | * network order (big endian) to little endian | ||
634 | */ | ||
635 | rar_low = ((u32)addr[0] | | ||
636 | ((u32)addr[1] << 8) | | ||
637 | ((u32)addr[2] << 16) | | ||
638 | ((u32)addr[3] << 24)); | ||
639 | 1017 | ||
640 | rar_high = ((u32)addr[4] | | 1018 | /* Make sure we are using a valid rar index range */ |
641 | ((u32)addr[5] << 8) | | 1019 | if (index < rar_entries) { |
642 | ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK)); | 1020 | /* |
1021 | * HW expects these in little endian so we reverse the byte | ||
1022 | * order from network order (big endian) to little endian | ||
1023 | */ | ||
1024 | rar_low = ((u32)addr[0] | | ||
1025 | ((u32)addr[1] << 8) | | ||
1026 | ((u32)addr[2] << 16) | | ||
1027 | ((u32)addr[3] << 24)); | ||
1028 | /* | ||
1029 | * Some parts put the VMDq setting in the extra RAH bits, | ||
1030 | * so save everything except the lower 16 bits that hold part | ||
1031 | * of the address and the address valid bit. | ||
1032 | */ | ||
1033 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | ||
1034 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | ||
1035 | rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); | ||
643 | 1036 | ||
644 | if (enable_addr != 0) | 1037 | if (enable_addr != 0) |
645 | rar_high |= IXGBE_RAH_AV; | 1038 | rar_high |= IXGBE_RAH_AV; |
646 | 1039 | ||
647 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); | 1040 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); |
648 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | 1041 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); |
1042 | } else { | ||
1043 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | ||
1044 | } | ||
649 | 1045 | ||
650 | return 0; | 1046 | return 0; |
651 | } | 1047 | } |
652 | 1048 | ||
653 | /** | 1049 | /** |
654 | * ixgbe_init_rx_addrs - Initializes receive address filters. | 1050 | * ixgbe_clear_rar_generic - Remove Rx address register |
1051 | * @hw: pointer to hardware structure | ||
1052 | * @index: Receive address register to write | ||
1053 | * | ||
1054 | * Clears an ethernet address from a receive address register. | ||
1055 | **/ | ||
1056 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) | ||
1057 | { | ||
1058 | u32 rar_high; | ||
1059 | u32 rar_entries = hw->mac.num_rar_entries; | ||
1060 | |||
1061 | /* Make sure we are using a valid rar index range */ | ||
1062 | if (index < rar_entries) { | ||
1063 | /* | ||
1064 | * Some parts put the VMDq setting in the extra RAH bits, | ||
1065 | * so save everything except the lower 16 bits that hold part | ||
1066 | * of the address and the address valid bit. | ||
1067 | */ | ||
1068 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | ||
1069 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | ||
1070 | |||
1071 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); | ||
1072 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | ||
1073 | } else { | ||
1074 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | ||
1075 | } | ||
1076 | |||
1077 | /* clear VMDq pool/queue selection for this RAR */ | ||
1078 | hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); | ||
1079 | |||
1080 | return 0; | ||
1081 | } | ||
1082 | |||
1083 | /** | ||
1084 | * ixgbe_enable_rar - Enable Rx address register | ||
1085 | * @hw: pointer to hardware structure | ||
1086 | * @index: index into the RAR table | ||
1087 | * | ||
1088 | * Enables the select receive address register. | ||
1089 | **/ | ||
1090 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) | ||
1091 | { | ||
1092 | u32 rar_high; | ||
1093 | |||
1094 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | ||
1095 | rar_high |= IXGBE_RAH_AV; | ||
1096 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | ||
1097 | } | ||
1098 | |||
1099 | /** | ||
1100 | * ixgbe_disable_rar - Disable Rx address register | ||
1101 | * @hw: pointer to hardware structure | ||
1102 | * @index: index into the RAR table | ||
1103 | * | ||
1104 | * Disables the select receive address register. | ||
1105 | **/ | ||
1106 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) | ||
1107 | { | ||
1108 | u32 rar_high; | ||
1109 | |||
1110 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | ||
1111 | rar_high &= (~IXGBE_RAH_AV); | ||
1112 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | ||
1113 | } | ||
1114 | |||
1115 | /** | ||
1116 | * ixgbe_init_rx_addrs_generic - Initializes receive address filters. | ||
655 | * @hw: pointer to hardware structure | 1117 | * @hw: pointer to hardware structure |
656 | * | 1118 | * |
657 | * Places the MAC address in receive address register 0 and clears the rest | 1119 | * Places the MAC address in receive address register 0 and clears the rest |
658 | * of the receive addresss registers. Clears the multicast table. Assumes | 1120 | * of the receive address registers. Clears the multicast table. Assumes |
659 | * the receiver is in reset when the routine is called. | 1121 | * the receiver is in reset when the routine is called. |
660 | **/ | 1122 | **/ |
661 | static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) | 1123 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) |
662 | { | 1124 | { |
663 | u32 i; | 1125 | u32 i; |
664 | u32 rar_entries = hw->mac.num_rar_entries; | 1126 | u32 rar_entries = hw->mac.num_rar_entries; |
@@ -671,29 +1133,30 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) | |||
671 | if (ixgbe_validate_mac_addr(hw->mac.addr) == | 1133 | if (ixgbe_validate_mac_addr(hw->mac.addr) == |
672 | IXGBE_ERR_INVALID_MAC_ADDR) { | 1134 | IXGBE_ERR_INVALID_MAC_ADDR) { |
673 | /* Get the MAC address from the RAR0 for later reference */ | 1135 | /* Get the MAC address from the RAR0 for later reference */ |
674 | ixgbe_get_mac_addr(hw, hw->mac.addr); | 1136 | hw->mac.ops.get_mac_addr(hw, hw->mac.addr); |
675 | 1137 | ||
676 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", | 1138 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", |
677 | hw->mac.addr[0], hw->mac.addr[1], | 1139 | hw->mac.addr[0], hw->mac.addr[1], |
678 | hw->mac.addr[2]); | 1140 | hw->mac.addr[2]); |
679 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], | 1141 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
680 | hw->mac.addr[4], hw->mac.addr[5]); | 1142 | hw->mac.addr[4], hw->mac.addr[5]); |
681 | } else { | 1143 | } else { |
682 | /* Setup the receive address. */ | 1144 | /* Setup the receive address. */ |
683 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); | 1145 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); |
684 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", | 1146 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", |
685 | hw->mac.addr[0], hw->mac.addr[1], | 1147 | hw->mac.addr[0], hw->mac.addr[1], |
686 | hw->mac.addr[2]); | 1148 | hw->mac.addr[2]); |
687 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], | 1149 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
688 | hw->mac.addr[4], hw->mac.addr[5]); | 1150 | hw->mac.addr[4], hw->mac.addr[5]); |
689 | 1151 | ||
690 | ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); | 1152 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
691 | } | 1153 | } |
1154 | hw->addr_ctrl.overflow_promisc = 0; | ||
692 | 1155 | ||
693 | hw->addr_ctrl.rar_used_count = 1; | 1156 | hw->addr_ctrl.rar_used_count = 1; |
694 | 1157 | ||
695 | /* Zero out the other receive addresses. */ | 1158 | /* Zero out the other receive addresses. */ |
696 | hw_dbg(hw, "Clearing RAR[1-15]\n"); | 1159 | hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); |
697 | for (i = 1; i < rar_entries; i++) { | 1160 | for (i = 1; i < rar_entries; i++) { |
698 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | 1161 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
699 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | 1162 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
@@ -708,6 +1171,9 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) | |||
708 | for (i = 0; i < hw->mac.mcft_size; i++) | 1171 | for (i = 0; i < hw->mac.mcft_size; i++) |
709 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); | 1172 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
710 | 1173 | ||
1174 | if (hw->mac.ops.init_uta_tables) | ||
1175 | hw->mac.ops.init_uta_tables(hw); | ||
1176 | |||
711 | return 0; | 1177 | return 0; |
712 | } | 1178 | } |
713 | 1179 | ||
@@ -718,7 +1184,7 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) | |||
718 | * | 1184 | * |
719 | * Adds it to unused receive address register or goes into promiscuous mode. | 1185 | * Adds it to unused receive address register or goes into promiscuous mode. |
720 | **/ | 1186 | **/ |
721 | void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr) | 1187 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) |
722 | { | 1188 | { |
723 | u32 rar_entries = hw->mac.num_rar_entries; | 1189 | u32 rar_entries = hw->mac.num_rar_entries; |
724 | u32 rar; | 1190 | u32 rar; |
@@ -733,7 +1199,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr) | |||
733 | if (hw->addr_ctrl.rar_used_count < rar_entries) { | 1199 | if (hw->addr_ctrl.rar_used_count < rar_entries) { |
734 | rar = hw->addr_ctrl.rar_used_count - | 1200 | rar = hw->addr_ctrl.rar_used_count - |
735 | hw->addr_ctrl.mc_addr_in_rar_count; | 1201 | hw->addr_ctrl.mc_addr_in_rar_count; |
736 | ixgbe_set_rar(hw, rar, addr, 0, IXGBE_RAH_AV); | 1202 | hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); |
737 | hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); | 1203 | hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); |
738 | hw->addr_ctrl.rar_used_count++; | 1204 | hw->addr_ctrl.rar_used_count++; |
739 | } else { | 1205 | } else { |
@@ -744,7 +1210,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr) | |||
744 | } | 1210 | } |
745 | 1211 | ||
746 | /** | 1212 | /** |
747 | * ixgbe_update_uc_addr_list - Updates MAC list of secondary addresses | 1213 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses |
748 | * @hw: pointer to hardware structure | 1214 | * @hw: pointer to hardware structure |
749 | * @addr_list: the list of new addresses | 1215 | * @addr_list: the list of new addresses |
750 | * @addr_count: number of addresses | 1216 | * @addr_count: number of addresses |
@@ -757,7 +1223,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr) | |||
757 | * Drivers using secondary unicast addresses must set user_set_promisc when | 1223 | * Drivers using secondary unicast addresses must set user_set_promisc when |
758 | * manually putting the device into promiscuous mode. | 1224 | * manually putting the device into promiscuous mode. |
759 | **/ | 1225 | **/ |
760 | s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, | 1226 | s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, |
761 | u32 addr_count, ixgbe_mc_addr_itr next) | 1227 | u32 addr_count, ixgbe_mc_addr_itr next) |
762 | { | 1228 | { |
763 | u8 *addr; | 1229 | u8 *addr; |
@@ -787,7 +1253,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, | |||
787 | for (i = 0; i < addr_count; i++) { | 1253 | for (i = 0; i < addr_count; i++) { |
788 | hw_dbg(hw, " Adding the secondary addresses:\n"); | 1254 | hw_dbg(hw, " Adding the secondary addresses:\n"); |
789 | addr = next(hw, &addr_list, &vmdq); | 1255 | addr = next(hw, &addr_list, &vmdq); |
790 | ixgbe_add_uc_addr(hw, addr); | 1256 | ixgbe_add_uc_addr(hw, addr, vmdq); |
791 | } | 1257 | } |
792 | 1258 | ||
793 | if (hw->addr_ctrl.overflow_promisc) { | 1259 | if (hw->addr_ctrl.overflow_promisc) { |
@@ -808,7 +1274,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, | |||
808 | } | 1274 | } |
809 | } | 1275 | } |
810 | 1276 | ||
811 | hw_dbg(hw, "ixgbe_update_uc_addr_list Complete\n"); | 1277 | hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n"); |
812 | return 0; | 1278 | return 0; |
813 | } | 1279 | } |
814 | 1280 | ||
@@ -821,7 +1287,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, | |||
821 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from | 1287 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from |
822 | * incoming rx multicast addresses, to determine the bit-vector to check in | 1288 | * incoming rx multicast addresses, to determine the bit-vector to check in |
823 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set | 1289 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set |
824 | * by the MO field of the MCSTCTRL. The MO field is set during initalization | 1290 | * by the MO field of the MCSTCTRL. The MO field is set during initialization |
825 | * to mc_filter_type. | 1291 | * to mc_filter_type. |
826 | **/ | 1292 | **/ |
827 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) | 1293 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) |
@@ -829,19 +1295,19 @@ static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) | |||
829 | u32 vector = 0; | 1295 | u32 vector = 0; |
830 | 1296 | ||
831 | switch (hw->mac.mc_filter_type) { | 1297 | switch (hw->mac.mc_filter_type) { |
832 | case 0: /* use bits [47:36] of the address */ | 1298 | case 0: /* use bits [47:36] of the address */ |
833 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); | 1299 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
834 | break; | 1300 | break; |
835 | case 1: /* use bits [46:35] of the address */ | 1301 | case 1: /* use bits [46:35] of the address */ |
836 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); | 1302 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
837 | break; | 1303 | break; |
838 | case 2: /* use bits [45:34] of the address */ | 1304 | case 2: /* use bits [45:34] of the address */ |
839 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); | 1305 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
840 | break; | 1306 | break; |
841 | case 3: /* use bits [43:32] of the address */ | 1307 | case 3: /* use bits [43:32] of the address */ |
842 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); | 1308 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
843 | break; | 1309 | break; |
844 | default: /* Invalid mc_filter_type */ | 1310 | default: /* Invalid mc_filter_type */ |
845 | hw_dbg(hw, "MC filter type param set incorrectly\n"); | 1311 | hw_dbg(hw, "MC filter type param set incorrectly\n"); |
846 | break; | 1312 | break; |
847 | } | 1313 | } |
@@ -896,20 +1362,21 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) | |||
896 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) | 1362 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) |
897 | { | 1363 | { |
898 | u32 rar_entries = hw->mac.num_rar_entries; | 1364 | u32 rar_entries = hw->mac.num_rar_entries; |
1365 | u32 rar; | ||
899 | 1366 | ||
900 | hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", | 1367 | hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", |
901 | mc_addr[0], mc_addr[1], mc_addr[2], | 1368 | mc_addr[0], mc_addr[1], mc_addr[2], |
902 | mc_addr[3], mc_addr[4], mc_addr[5]); | 1369 | mc_addr[3], mc_addr[4], mc_addr[5]); |
903 | 1370 | ||
904 | /* | 1371 | /* |
905 | * Place this multicast address in the RAR if there is room, | 1372 | * Place this multicast address in the RAR if there is room, |
906 | * else put it in the MTA | 1373 | * else put it in the MTA |
907 | */ | 1374 | */ |
908 | if (hw->addr_ctrl.rar_used_count < rar_entries) { | 1375 | if (hw->addr_ctrl.rar_used_count < rar_entries) { |
909 | ixgbe_set_rar(hw, hw->addr_ctrl.rar_used_count, | 1376 | /* use RAR from the end up for multicast */ |
910 | mc_addr, 0, IXGBE_RAH_AV); | 1377 | rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; |
911 | hw_dbg(hw, "Added a multicast address to RAR[%d]\n", | 1378 | hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); |
912 | hw->addr_ctrl.rar_used_count); | 1379 | hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar); |
913 | hw->addr_ctrl.rar_used_count++; | 1380 | hw->addr_ctrl.rar_used_count++; |
914 | hw->addr_ctrl.mc_addr_in_rar_count++; | 1381 | hw->addr_ctrl.mc_addr_in_rar_count++; |
915 | } else { | 1382 | } else { |
@@ -920,19 +1387,19 @@ static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) | |||
920 | } | 1387 | } |
921 | 1388 | ||
922 | /** | 1389 | /** |
923 | * ixgbe_update_mc_addr_list - Updates MAC list of multicast addresses | 1390 | * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses |
924 | * @hw: pointer to hardware structure | 1391 | * @hw: pointer to hardware structure |
925 | * @mc_addr_list: the list of new multicast addresses | 1392 | * @mc_addr_list: the list of new multicast addresses |
926 | * @mc_addr_count: number of addresses | 1393 | * @mc_addr_count: number of addresses |
927 | * @next: iterator function to walk the multicast address list | 1394 | * @next: iterator function to walk the multicast address list |
928 | * | 1395 | * |
929 | * The given list replaces any existing list. Clears the MC addrs from receive | 1396 | * The given list replaces any existing list. Clears the MC addrs from receive |
930 | * address registers and the multicast table. Uses unsed receive address | 1397 | * address registers and the multicast table. Uses unused receive address |
931 | * registers for the first multicast addresses, and hashes the rest into the | 1398 | * registers for the first multicast addresses, and hashes the rest into the |
932 | * multicast table. | 1399 | * multicast table. |
933 | **/ | 1400 | **/ |
934 | s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, | 1401 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, |
935 | u32 mc_addr_count, ixgbe_mc_addr_itr next) | 1402 | u32 mc_addr_count, ixgbe_mc_addr_itr next) |
936 | { | 1403 | { |
937 | u32 i; | 1404 | u32 i; |
938 | u32 rar_entries = hw->mac.num_rar_entries; | 1405 | u32 rar_entries = hw->mac.num_rar_entries; |
@@ -948,7 +1415,8 @@ s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, | |||
948 | hw->addr_ctrl.mta_in_use = 0; | 1415 | hw->addr_ctrl.mta_in_use = 0; |
949 | 1416 | ||
950 | /* Zero out the other receive addresses. */ | 1417 | /* Zero out the other receive addresses. */ |
951 | hw_dbg(hw, "Clearing RAR[1-15]\n"); | 1418 | hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, |
1419 | rar_entries - 1); | ||
952 | for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { | 1420 | for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { |
953 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | 1421 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
954 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | 1422 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
@@ -968,190 +1436,55 @@ s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, | |||
968 | /* Enable mta */ | 1436 | /* Enable mta */ |
969 | if (hw->addr_ctrl.mta_in_use > 0) | 1437 | if (hw->addr_ctrl.mta_in_use > 0) |
970 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, | 1438 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, |
971 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); | 1439 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); |
972 | 1440 | ||
973 | hw_dbg(hw, "ixgbe_update_mc_addr_list Complete\n"); | 1441 | hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); |
974 | return 0; | 1442 | return 0; |
975 | } | 1443 | } |
976 | 1444 | ||
977 | /** | 1445 | /** |
978 | * ixgbe_clear_vfta - Clear VLAN filter table | 1446 | * ixgbe_enable_mc_generic - Enable multicast address in RAR |
979 | * @hw: pointer to hardware structure | 1447 | * @hw: pointer to hardware structure |
980 | * | 1448 | * |
981 | * Clears the VLAN filer table, and the VMDq index associated with the filter | 1449 | * Enables multicast address in RAR and the use of the multicast hash table. |
982 | **/ | 1450 | **/ |
983 | static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) | 1451 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) |
984 | { | 1452 | { |
985 | u32 offset; | 1453 | u32 i; |
986 | u32 vlanbyte; | 1454 | u32 rar_entries = hw->mac.num_rar_entries; |
1455 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; | ||
987 | 1456 | ||
988 | for (offset = 0; offset < hw->mac.vft_size; offset++) | 1457 | if (a->mc_addr_in_rar_count > 0) |
989 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | 1458 | for (i = (rar_entries - a->mc_addr_in_rar_count); |
1459 | i < rar_entries; i++) | ||
1460 | ixgbe_enable_rar(hw, i); | ||
990 | 1461 | ||
991 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | 1462 | if (a->mta_in_use > 0) |
992 | for (offset = 0; offset < hw->mac.vft_size; offset++) | 1463 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | |
993 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | 1464 | hw->mac.mc_filter_type); |
994 | 0); | ||
995 | 1465 | ||
996 | return 0; | 1466 | return 0; |
997 | } | 1467 | } |
998 | 1468 | ||
999 | /** | 1469 | /** |
1000 | * ixgbe_set_vfta - Set VLAN filter table | 1470 | * ixgbe_disable_mc_generic - Disable multicast address in RAR |
1001 | * @hw: pointer to hardware structure | 1471 | * @hw: pointer to hardware structure |
1002 | * @vlan: VLAN id to write to VLAN filter | ||
1003 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | ||
1004 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | ||
1005 | * | 1472 | * |
1006 | * Turn on/off specified VLAN in the VLAN filter table. | 1473 | * Disables multicast address in RAR and the use of the multicast hash table. |
1007 | **/ | 1474 | **/ |
1008 | s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, | 1475 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) |
1009 | bool vlan_on) | ||
1010 | { | 1476 | { |
1011 | u32 VftaIndex; | 1477 | u32 i; |
1012 | u32 BitOffset; | 1478 | u32 rar_entries = hw->mac.num_rar_entries; |
1013 | u32 VftaReg; | 1479 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; |
1014 | u32 VftaByte; | ||
1015 | |||
1016 | /* Determine 32-bit word position in array */ | ||
1017 | VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */ | ||
1018 | |||
1019 | /* Determine the location of the (VMD) queue index */ | ||
1020 | VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | ||
1021 | BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | ||
1022 | |||
1023 | /* Set the nibble for VMD queue index */ | ||
1024 | VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex)); | ||
1025 | VftaReg &= (~(0x0F << BitOffset)); | ||
1026 | VftaReg |= (vind << BitOffset); | ||
1027 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg); | ||
1028 | |||
1029 | /* Determine the location of the bit for this VLAN id */ | ||
1030 | BitOffset = vlan & 0x1F; /* lower five bits */ | ||
1031 | |||
1032 | VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex)); | ||
1033 | if (vlan_on) | ||
1034 | /* Turn on this VLAN id */ | ||
1035 | VftaReg |= (1 << BitOffset); | ||
1036 | else | ||
1037 | /* Turn off this VLAN id */ | ||
1038 | VftaReg &= ~(1 << BitOffset); | ||
1039 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg); | ||
1040 | |||
1041 | return 0; | ||
1042 | } | ||
1043 | |||
1044 | /** | ||
1045 | * ixgbe_setup_fc - Configure flow control settings | ||
1046 | * @hw: pointer to hardware structure | ||
1047 | * @packetbuf_num: packet buffer number (0-7) | ||
1048 | * | ||
1049 | * Configures the flow control settings based on SW configuration. | ||
1050 | * This function is used for 802.3x flow control configuration only. | ||
1051 | **/ | ||
1052 | s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | ||
1053 | { | ||
1054 | u32 frctl_reg; | ||
1055 | u32 rmcs_reg; | ||
1056 | |||
1057 | if (packetbuf_num < 0 || packetbuf_num > 7) | ||
1058 | hw_dbg(hw, "Invalid packet buffer number [%d], expected range " | ||
1059 | "is 0-7\n", packetbuf_num); | ||
1060 | |||
1061 | frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); | ||
1062 | frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | ||
1063 | |||
1064 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | ||
1065 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | ||
1066 | |||
1067 | /* | ||
1068 | * 10 gig parts do not have a word in the EEPROM to determine the | ||
1069 | * default flow control setting, so we explicitly set it to full. | ||
1070 | */ | ||
1071 | if (hw->fc.type == ixgbe_fc_default) | ||
1072 | hw->fc.type = ixgbe_fc_full; | ||
1073 | |||
1074 | /* | ||
1075 | * We want to save off the original Flow Control configuration just in | ||
1076 | * case we get disconnected and then reconnected into a different hub | ||
1077 | * or switch with different Flow Control capabilities. | ||
1078 | */ | ||
1079 | hw->fc.type = hw->fc.original_type; | ||
1080 | |||
1081 | /* | ||
1082 | * The possible values of the "flow_control" parameter are: | ||
1083 | * 0: Flow control is completely disabled | ||
1084 | * 1: Rx flow control is enabled (we can receive pause frames but not | ||
1085 | * send pause frames). | ||
1086 | * 2: Tx flow control is enabled (we can send pause frames but we do not | ||
1087 | * support receiving pause frames) | ||
1088 | * 3: Both Rx and TX flow control (symmetric) are enabled. | ||
1089 | * other: Invalid. | ||
1090 | */ | ||
1091 | switch (hw->fc.type) { | ||
1092 | case ixgbe_fc_none: | ||
1093 | break; | ||
1094 | case ixgbe_fc_rx_pause: | ||
1095 | /* | ||
1096 | * RX Flow control is enabled, | ||
1097 | * and TX Flow control is disabled. | ||
1098 | */ | ||
1099 | frctl_reg |= IXGBE_FCTRL_RFCE; | ||
1100 | break; | ||
1101 | case ixgbe_fc_tx_pause: | ||
1102 | /* | ||
1103 | * TX Flow control is enabled, and RX Flow control is disabled, | ||
1104 | * by a software over-ride. | ||
1105 | */ | ||
1106 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | ||
1107 | break; | ||
1108 | case ixgbe_fc_full: | ||
1109 | /* | ||
1110 | * Flow control (both RX and TX) is enabled by a software | ||
1111 | * over-ride. | ||
1112 | */ | ||
1113 | frctl_reg |= IXGBE_FCTRL_RFCE; | ||
1114 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | ||
1115 | break; | ||
1116 | default: | ||
1117 | /* We should never get here. The value should be 0-3. */ | ||
1118 | hw_dbg(hw, "Flow control param set incorrectly\n"); | ||
1119 | break; | ||
1120 | } | ||
1121 | 1480 | ||
1122 | /* Enable 802.3x based flow control settings. */ | 1481 | if (a->mc_addr_in_rar_count > 0) |
1123 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); | 1482 | for (i = (rar_entries - a->mc_addr_in_rar_count); |
1124 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); | 1483 | i < rar_entries; i++) |
1484 | ixgbe_disable_rar(hw, i); | ||
1125 | 1485 | ||
1126 | /* | 1486 | if (a->mta_in_use > 0) |
1127 | * Check for invalid software configuration, zeros are completely | 1487 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); |
1128 | * invalid for all parameters used past this point, and if we enable | ||
1129 | * flow control with zero water marks, we blast flow control packets. | ||
1130 | */ | ||
1131 | if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { | ||
1132 | hw_dbg(hw, "Flow control structure initialized incorrectly\n"); | ||
1133 | return IXGBE_ERR_INVALID_LINK_SETTINGS; | ||
1134 | } | ||
1135 | |||
1136 | /* | ||
1137 | * We need to set up the Receive Threshold high and low water | ||
1138 | * marks as well as (optionally) enabling the transmission of | ||
1139 | * XON frames. | ||
1140 | */ | ||
1141 | if (hw->fc.type & ixgbe_fc_tx_pause) { | ||
1142 | if (hw->fc.send_xon) { | ||
1143 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | ||
1144 | (hw->fc.low_water | IXGBE_FCRTL_XONE)); | ||
1145 | } else { | ||
1146 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | ||
1147 | hw->fc.low_water); | ||
1148 | } | ||
1149 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), | ||
1150 | (hw->fc.high_water)|IXGBE_FCRTH_FCEN); | ||
1151 | } | ||
1152 | |||
1153 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); | ||
1154 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); | ||
1155 | 1488 | ||
1156 | return 0; | 1489 | return 0; |
1157 | } | 1490 | } |
@@ -1167,13 +1500,24 @@ s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1167 | **/ | 1500 | **/ |
1168 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) | 1501 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) |
1169 | { | 1502 | { |
1170 | u32 ctrl; | 1503 | u32 i; |
1171 | s32 i; | 1504 | u32 reg_val; |
1505 | u32 number_of_queues; | ||
1172 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; | 1506 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
1173 | 1507 | ||
1174 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | 1508 | /* Disable the receive unit by stopping each queue */ |
1175 | ctrl |= IXGBE_CTRL_GIO_DIS; | 1509 | number_of_queues = hw->mac.max_rx_queues; |
1176 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | 1510 | for (i = 0; i < number_of_queues; i++) { |
1511 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | ||
1512 | if (reg_val & IXGBE_RXDCTL_ENABLE) { | ||
1513 | reg_val &= ~IXGBE_RXDCTL_ENABLE; | ||
1514 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); | ||
1515 | } | ||
1516 | } | ||
1517 | |||
1518 | reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); | ||
1519 | reg_val |= IXGBE_CTRL_GIO_DIS; | ||
1520 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); | ||
1177 | 1521 | ||
1178 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { | 1522 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { |
1179 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { | 1523 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { |
@@ -1188,11 +1532,11 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) | |||
1188 | 1532 | ||
1189 | 1533 | ||
1190 | /** | 1534 | /** |
1191 | * ixgbe_acquire_swfw_sync - Aquire SWFW semaphore | 1535 | * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore |
1192 | * @hw: pointer to hardware structure | 1536 | * @hw: pointer to hardware structure |
1193 | * @mask: Mask to specify wich semaphore to acquire | 1537 | * @mask: Mask to specify which semaphore to acquire |
1194 | * | 1538 | * |
1195 | * Aquires the SWFW semaphore throught the GSSR register for the specified | 1539 | * Acquires the SWFW semaphore thought the GSSR register for the specified |
1196 | * function (CSR, PHY0, PHY1, EEPROM, Flash) | 1540 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
1197 | **/ | 1541 | **/ |
1198 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | 1542 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) |
@@ -1234,9 +1578,9 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
1234 | /** | 1578 | /** |
1235 | * ixgbe_release_swfw_sync - Release SWFW semaphore | 1579 | * ixgbe_release_swfw_sync - Release SWFW semaphore |
1236 | * @hw: pointer to hardware structure | 1580 | * @hw: pointer to hardware structure |
1237 | * @mask: Mask to specify wich semaphore to release | 1581 | * @mask: Mask to specify which semaphore to release |
1238 | * | 1582 | * |
1239 | * Releases the SWFW semaphore throught the GSSR register for the specified | 1583 | * Releases the SWFW semaphore thought the GSSR register for the specified |
1240 | * function (CSR, PHY0, PHY1, EEPROM, Flash) | 1584 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
1241 | **/ | 1585 | **/ |
1242 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) | 1586 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) |
@@ -1253,45 +1597,3 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
1253 | ixgbe_release_eeprom_semaphore(hw); | 1597 | ixgbe_release_eeprom_semaphore(hw); |
1254 | } | 1598 | } |
1255 | 1599 | ||
1256 | /** | ||
1257 | * ixgbe_read_analog_reg8 - Reads 8 bit Atlas analog register | ||
1258 | * @hw: pointer to hardware structure | ||
1259 | * @reg: analog register to read | ||
1260 | * @val: read value | ||
1261 | * | ||
1262 | * Performs write operation to analog register specified. | ||
1263 | **/ | ||
1264 | s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) | ||
1265 | { | ||
1266 | u32 atlas_ctl; | ||
1267 | |||
1268 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | ||
1269 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | ||
1270 | IXGBE_WRITE_FLUSH(hw); | ||
1271 | udelay(10); | ||
1272 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | ||
1273 | *val = (u8)atlas_ctl; | ||
1274 | |||
1275 | return 0; | ||
1276 | } | ||
1277 | |||
1278 | /** | ||
1279 | * ixgbe_write_analog_reg8 - Writes 8 bit Atlas analog register | ||
1280 | * @hw: pointer to hardware structure | ||
1281 | * @reg: atlas register to write | ||
1282 | * @val: value to write | ||
1283 | * | ||
1284 | * Performs write operation to Atlas analog register specified. | ||
1285 | **/ | ||
1286 | s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) | ||
1287 | { | ||
1288 | u32 atlas_ctl; | ||
1289 | |||
1290 | atlas_ctl = (reg << 8) | val; | ||
1291 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | ||
1292 | IXGBE_WRITE_FLUSH(hw); | ||
1293 | udelay(10); | ||
1294 | |||
1295 | return 0; | ||
1296 | } | ||
1297 | |||