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-rw-r--r--drivers/net/ixgbe/ixgbe_common.c1175
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diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
new file mode 100644
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+++ b/drivers/net/ixgbe/ixgbe_common.c
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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe_common.h"
34#include "ixgbe_phy.h"
35
36static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
42
43static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
44static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
45static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
46static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
47
48/**
49 * ixgbe_start_hw - Prepare hardware for TX/RX
50 * @hw: pointer to hardware structure
51 *
52 * Starts the hardware by filling the bus info structure and media type, clears
53 * all on chip counters, initializes receive address registers, multicast
54 * table, VLAN filter table, calls routine to set up link and flow control
55 * settings, and leaves transmit and receive units disabled and uninitialized
56 **/
57s32 ixgbe_start_hw(struct ixgbe_hw *hw)
58{
59 u32 ctrl_ext;
60
61 /* Set the media type */
62 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
63
64 /* Identify the PHY */
65 ixgbe_identify_phy(hw);
66
67 /*
68 * Store MAC address from RAR0, clear receive address registers, and
69 * clear the multicast table
70 */
71 ixgbe_init_rx_addrs(hw);
72
73 /* Clear the VLAN filter table */
74 ixgbe_clear_vfta(hw);
75
76 /* Set up link */
77 hw->phy.ops.setup(hw);
78
79 /* Clear statistics registers */
80 ixgbe_clear_hw_cntrs(hw);
81
82 /* Set No Snoop Disable */
83 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
84 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
86
87 /* Clear adapter stopped flag */
88 hw->adapter_stopped = false;
89
90 return 0;
91}
92
93/**
94 * ixgbe_init_hw - Generic hardware initialization
95 * @hw: pointer to hardware structure
96 *
97 * Initialize the hardware by reseting the hardware, filling the bus info
98 * structure and media type, clears all on chip counters, initializes receive
99 * address registers, multicast table, VLAN filter table, calls routine to set
100 * up link and flow control settings, and leaves transmit and receive units
101 * disabled and uninitialized
102 **/
103s32 ixgbe_init_hw(struct ixgbe_hw *hw)
104{
105 /* Reset the hardware */
106 hw->mac.ops.reset(hw);
107
108 /* Start the HW */
109 ixgbe_start_hw(hw);
110
111 return 0;
112}
113
114/**
115 * ixgbe_clear_hw_cntrs - Generic clear hardware counters
116 * @hw: pointer to hardware structure
117 *
118 * Clears all hardware statistics counters by reading them from the hardware
119 * Statistics counters are clear on read.
120 **/
121static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
122{
123 u16 i = 0;
124
125 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
126 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
127 IXGBE_READ_REG(hw, IXGBE_ERRBC);
128 IXGBE_READ_REG(hw, IXGBE_MSPDC);
129 for (i = 0; i < 8; i++)
130 IXGBE_READ_REG(hw, IXGBE_MPC(i));
131
132 IXGBE_READ_REG(hw, IXGBE_MLFC);
133 IXGBE_READ_REG(hw, IXGBE_MRFC);
134 IXGBE_READ_REG(hw, IXGBE_RLEC);
135 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
136 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
137 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
138 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
139
140 for (i = 0; i < 8; i++) {
141 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
142 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
143 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
144 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
145 }
146
147 IXGBE_READ_REG(hw, IXGBE_PRC64);
148 IXGBE_READ_REG(hw, IXGBE_PRC127);
149 IXGBE_READ_REG(hw, IXGBE_PRC255);
150 IXGBE_READ_REG(hw, IXGBE_PRC511);
151 IXGBE_READ_REG(hw, IXGBE_PRC1023);
152 IXGBE_READ_REG(hw, IXGBE_PRC1522);
153 IXGBE_READ_REG(hw, IXGBE_GPRC);
154 IXGBE_READ_REG(hw, IXGBE_BPRC);
155 IXGBE_READ_REG(hw, IXGBE_MPRC);
156 IXGBE_READ_REG(hw, IXGBE_GPTC);
157 IXGBE_READ_REG(hw, IXGBE_GORCL);
158 IXGBE_READ_REG(hw, IXGBE_GORCH);
159 IXGBE_READ_REG(hw, IXGBE_GOTCL);
160 IXGBE_READ_REG(hw, IXGBE_GOTCH);
161 for (i = 0; i < 8; i++)
162 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
163 IXGBE_READ_REG(hw, IXGBE_RUC);
164 IXGBE_READ_REG(hw, IXGBE_RFC);
165 IXGBE_READ_REG(hw, IXGBE_ROC);
166 IXGBE_READ_REG(hw, IXGBE_RJC);
167 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
168 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
169 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
170 IXGBE_READ_REG(hw, IXGBE_TORL);
171 IXGBE_READ_REG(hw, IXGBE_TORH);
172 IXGBE_READ_REG(hw, IXGBE_TPR);
173 IXGBE_READ_REG(hw, IXGBE_TPT);
174 IXGBE_READ_REG(hw, IXGBE_PTC64);
175 IXGBE_READ_REG(hw, IXGBE_PTC127);
176 IXGBE_READ_REG(hw, IXGBE_PTC255);
177 IXGBE_READ_REG(hw, IXGBE_PTC511);
178 IXGBE_READ_REG(hw, IXGBE_PTC1023);
179 IXGBE_READ_REG(hw, IXGBE_PTC1522);
180 IXGBE_READ_REG(hw, IXGBE_MPTC);
181 IXGBE_READ_REG(hw, IXGBE_BPTC);
182 for (i = 0; i < 16; i++) {
183 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
184 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
185 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
186 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
187 }
188
189 return 0;
190}
191
192/**
193 * ixgbe_get_mac_addr - Generic get MAC address
194 * @hw: pointer to hardware structure
195 * @mac_addr: Adapter MAC address
196 *
197 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
198 * A reset of the adapter must be performed prior to calling this function
199 * in order for the MAC address to have been loaded from the EEPROM into RAR0
200 **/
201s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
202{
203 u32 rar_high;
204 u32 rar_low;
205 u16 i;
206
207 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
208 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
209
210 for (i = 0; i < 4; i++)
211 mac_addr[i] = (u8)(rar_low >> (i*8));
212
213 for (i = 0; i < 2; i++)
214 mac_addr[i+4] = (u8)(rar_high >> (i*8));
215
216 return 0;
217}
218
219s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num)
220{
221 s32 ret_val;
222 u16 data;
223
224 ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM0_PTR, &data);
225 if (ret_val) {
226 hw_dbg(hw, "NVM Read Error\n");
227 return ret_val;
228 }
229 *part_num = (u32)(data << 16);
230
231 ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM1_PTR, &data);
232 if (ret_val) {
233 hw_dbg(hw, "NVM Read Error\n");
234 return ret_val;
235 }
236 *part_num |= data;
237
238 return 0;
239}
240
241/**
242 * ixgbe_stop_adapter - Generic stop TX/RX units
243 * @hw: pointer to hardware structure
244 *
245 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
246 * disables transmit and receive units. The adapter_stopped flag is used by
247 * the shared code and drivers to determine if the adapter is in a stopped
248 * state and should not touch the hardware.
249 **/
250s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
251{
252 u32 number_of_queues;
253 u32 reg_val;
254 u16 i;
255
256 /*
257 * Set the adapter_stopped flag so other driver functions stop touching
258 * the hardware
259 */
260 hw->adapter_stopped = true;
261
262 /* Disable the receive unit */
263 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
264 reg_val &= ~(IXGBE_RXCTRL_RXEN);
265 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
266 msleep(2);
267
268 /* Clear interrupt mask to stop from interrupts being generated */
269 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
270
271 /* Clear any pending interrupts */
272 IXGBE_READ_REG(hw, IXGBE_EICR);
273
274 /* Disable the transmit unit. Each queue must be disabled. */
275 number_of_queues = hw->mac.num_tx_queues;
276 for (i = 0; i < number_of_queues; i++) {
277 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
278 if (reg_val & IXGBE_TXDCTL_ENABLE) {
279 reg_val &= ~IXGBE_TXDCTL_ENABLE;
280 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
281 }
282 }
283
284 return 0;
285}
286
287/**
288 * ixgbe_led_on - Turns on the software controllable LEDs.
289 * @hw: pointer to hardware structure
290 * @index: led number to turn on
291 **/
292s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
293{
294 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
295
296 /* To turn on the LED, set mode to ON. */
297 led_reg &= ~IXGBE_LED_MODE_MASK(index);
298 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
299 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
300
301 return 0;
302}
303
304/**
305 * ixgbe_led_off - Turns off the software controllable LEDs.
306 * @hw: pointer to hardware structure
307 * @index: led number to turn off
308 **/
309s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
310{
311 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
312
313 /* To turn off the LED, set mode to OFF. */
314 led_reg &= ~IXGBE_LED_MODE_MASK(index);
315 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
316 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
317
318 return 0;
319}
320
321
322/**
323 * ixgbe_init_eeprom - Initialize EEPROM params
324 * @hw: pointer to hardware structure
325 *
326 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
327 * ixgbe_hw struct in order to set up EEPROM access.
328 **/
329s32 ixgbe_init_eeprom(struct ixgbe_hw *hw)
330{
331 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
332 u32 eec;
333 u16 eeprom_size;
334
335 if (eeprom->type == ixgbe_eeprom_uninitialized) {
336 eeprom->type = ixgbe_eeprom_none;
337
338 /*
339 * Check for EEPROM present first.
340 * If not present leave as none
341 */
342 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
343 if (eec & IXGBE_EEC_PRES) {
344 eeprom->type = ixgbe_eeprom_spi;
345
346 /*
347 * SPI EEPROM is assumed here. This code would need to
348 * change if a future EEPROM is not SPI.
349 */
350 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
351 IXGBE_EEC_SIZE_SHIFT);
352 eeprom->word_size = 1 << (eeprom_size +
353 IXGBE_EEPROM_WORD_SIZE_SHIFT);
354 }
355
356 if (eec & IXGBE_EEC_ADDR_SIZE)
357 eeprom->address_bits = 16;
358 else
359 eeprom->address_bits = 8;
360 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
361 "%d\n", eeprom->type, eeprom->word_size,
362 eeprom->address_bits);
363 }
364
365 return 0;
366}
367
368/**
369 * ixgbe_read_eeprom - Read EEPROM word using EERD
370 * @hw: pointer to hardware structure
371 * @offset: offset of word in the EEPROM to read
372 * @data: word read from the EEPROM
373 *
374 * Reads a 16 bit word from the EEPROM using the EERD register.
375 **/
376s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
377{
378 u32 eerd;
379 s32 status;
380
381 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
382 IXGBE_EEPROM_READ_REG_START;
383
384 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
385 status = ixgbe_poll_eeprom_eerd_done(hw);
386
387 if (status == 0)
388 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
389 IXGBE_EEPROM_READ_REG_DATA);
390 else
391 hw_dbg(hw, "Eeprom read timed out\n");
392
393 return status;
394}
395
396/**
397 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
398 * @hw: pointer to hardware structure
399 *
400 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
401 **/
402static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
403{
404 u32 i;
405 u32 reg;
406 s32 status = IXGBE_ERR_EEPROM;
407
408 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
409 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
410 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
411 status = 0;
412 break;
413 }
414 udelay(5);
415 }
416 return status;
417}
418
419/**
420 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
421 * @hw: pointer to hardware structure
422 *
423 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
424 **/
425static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
426{
427 s32 status = IXGBE_ERR_EEPROM;
428 u32 timeout;
429 u32 i;
430 u32 swsm;
431
432 /* Set timeout value based on size of EEPROM */
433 timeout = hw->eeprom.word_size + 1;
434
435 /* Get SMBI software semaphore between device drivers first */
436 for (i = 0; i < timeout; i++) {
437 /*
438 * If the SMBI bit is 0 when we read it, then the bit will be
439 * set and we have the semaphore
440 */
441 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
442 if (!(swsm & IXGBE_SWSM_SMBI)) {
443 status = 0;
444 break;
445 }
446 msleep(1);
447 }
448
449 /* Now get the semaphore between SW/FW through the SWESMBI bit */
450 if (status == 0) {
451 for (i = 0; i < timeout; i++) {
452 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
453
454 /* Set the SW EEPROM semaphore bit to request access */
455 swsm |= IXGBE_SWSM_SWESMBI;
456 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
457
458 /*
459 * If we set the bit successfully then we got the
460 * semaphore.
461 */
462 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
463 if (swsm & IXGBE_SWSM_SWESMBI)
464 break;
465
466 udelay(50);
467 }
468
469 /*
470 * Release semaphores and return error if SW EEPROM semaphore
471 * was not granted because we don't have access to the EEPROM
472 */
473 if (i >= timeout) {
474 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
475 "not granted.\n");
476 ixgbe_release_eeprom_semaphore(hw);
477 status = IXGBE_ERR_EEPROM;
478 }
479 }
480
481 return status;
482}
483
484/**
485 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
486 * @hw: pointer to hardware structure
487 *
488 * This function clears hardware semaphore bits.
489 **/
490static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
491{
492 u32 swsm;
493
494 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
495
496 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
497 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
498 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
499}
500
501/**
502 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
503 * @hw: pointer to hardware structure
504 **/
505static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
506{
507 u16 i;
508 u16 j;
509 u16 checksum = 0;
510 u16 length = 0;
511 u16 pointer = 0;
512 u16 word = 0;
513
514 /* Include 0x0-0x3F in the checksum */
515 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
516 if (ixgbe_read_eeprom(hw, i, &word) != 0) {
517 hw_dbg(hw, "EEPROM read failed\n");
518 break;
519 }
520 checksum += word;
521 }
522
523 /* Include all data from pointers except for the fw pointer */
524 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
525 ixgbe_read_eeprom(hw, i, &pointer);
526
527 /* Make sure the pointer seems valid */
528 if (pointer != 0xFFFF && pointer != 0) {
529 ixgbe_read_eeprom(hw, pointer, &length);
530
531 if (length != 0xFFFF && length != 0) {
532 for (j = pointer+1; j <= pointer+length; j++) {
533 ixgbe_read_eeprom(hw, j, &word);
534 checksum += word;
535 }
536 }
537 }
538 }
539
540 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
541
542 return checksum;
543}
544
545/**
546 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
547 * @hw: pointer to hardware structure
548 * @checksum_val: calculated checksum
549 *
550 * Performs checksum calculation and validates the EEPROM checksum. If the
551 * caller does not need checksum_val, the value can be NULL.
552 **/
553s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
554{
555 s32 status;
556 u16 checksum;
557 u16 read_checksum = 0;
558
559 /*
560 * Read the first word from the EEPROM. If this times out or fails, do
561 * not continue or we could be in for a very long wait while every
562 * EEPROM read fails
563 */
564 status = ixgbe_read_eeprom(hw, 0, &checksum);
565
566 if (status == 0) {
567 checksum = ixgbe_calc_eeprom_checksum(hw);
568
569 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
570
571 /*
572 * Verify read checksum from EEPROM is the same as
573 * calculated checksum
574 */
575 if (read_checksum != checksum)
576 status = IXGBE_ERR_EEPROM_CHECKSUM;
577
578 /* If the user cares, return the calculated checksum */
579 if (checksum_val)
580 *checksum_val = checksum;
581 } else {
582 hw_dbg(hw, "EEPROM read failed\n");
583 }
584
585 return status;
586}
587
588/**
589 * ixgbe_validate_mac_addr - Validate MAC address
590 * @mac_addr: pointer to MAC address.
591 *
592 * Tests a MAC address to ensure it is a valid Individual Address
593 **/
594s32 ixgbe_validate_mac_addr(u8 *mac_addr)
595{
596 s32 status = 0;
597
598 /* Make sure it is not a multicast address */
599 if (IXGBE_IS_MULTICAST(mac_addr))
600 status = IXGBE_ERR_INVALID_MAC_ADDR;
601 /* Not a broadcast address */
602 else if (IXGBE_IS_BROADCAST(mac_addr))
603 status = IXGBE_ERR_INVALID_MAC_ADDR;
604 /* Reject the zero address */
605 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
606 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
607 status = IXGBE_ERR_INVALID_MAC_ADDR;
608
609 return status;
610}
611
612/**
613 * ixgbe_set_rar - Set RX address register
614 * @hw: pointer to hardware structure
615 * @addr: Address to put into receive address register
616 * @index: Receive address register to write
617 * @vind: Vind to set RAR to
618 * @enable_addr: set flag that address is active
619 *
620 * Puts an ethernet address into a receive address register.
621 **/
622s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind,
623 u32 enable_addr)
624{
625 u32 rar_low, rar_high;
626
627 /*
628 * HW expects these in little endian so we reverse the byte order from
629 * network order (big endian) to little endian
630 */
631 rar_low = ((u32)addr[0] |
632 ((u32)addr[1] << 8) |
633 ((u32)addr[2] << 16) |
634 ((u32)addr[3] << 24));
635
636 rar_high = ((u32)addr[4] |
637 ((u32)addr[5] << 8) |
638 ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK));
639
640 if (enable_addr != 0)
641 rar_high |= IXGBE_RAH_AV;
642
643 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
644 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
645
646 return 0;
647}
648
649/**
650 * ixgbe_init_rx_addrs - Initializes receive address filters.
651 * @hw: pointer to hardware structure
652 *
653 * Places the MAC address in receive address register 0 and clears the rest
654 * of the receive addresss registers. Clears the multicast table. Assumes
655 * the receiver is in reset when the routine is called.
656 **/
657static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
658{
659 u32 i;
660 u32 rar_entries = hw->mac.num_rx_addrs;
661
662 /*
663 * If the current mac address is valid, assume it is a software override
664 * to the permanent address.
665 * Otherwise, use the permanent address from the eeprom.
666 */
667 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
668 IXGBE_ERR_INVALID_MAC_ADDR) {
669 /* Get the MAC address from the RAR0 for later reference */
670 ixgbe_get_mac_addr(hw, hw->mac.addr);
671
672 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
673 hw->mac.addr[0], hw->mac.addr[1],
674 hw->mac.addr[2]);
675 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
676 hw->mac.addr[4], hw->mac.addr[5]);
677 } else {
678 /* Setup the receive address. */
679 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
680 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
681 hw->mac.addr[0], hw->mac.addr[1],
682 hw->mac.addr[2]);
683 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
684 hw->mac.addr[4], hw->mac.addr[5]);
685
686 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
687 }
688
689 hw->addr_ctrl.rar_used_count = 1;
690
691 /* Zero out the other receive addresses. */
692 hw_dbg(hw, "Clearing RAR[1-15]\n");
693 for (i = 1; i < rar_entries; i++) {
694 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
695 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
696 }
697
698 /* Clear the MTA */
699 hw->addr_ctrl.mc_addr_in_rar_count = 0;
700 hw->addr_ctrl.mta_in_use = 0;
701 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
702
703 hw_dbg(hw, " Clearing MTA\n");
704 for (i = 0; i < IXGBE_MC_TBL_SIZE; i++)
705 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
706
707 return 0;
708}
709
710/**
711 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
712 * @hw: pointer to hardware structure
713 * @mc_addr: the multicast address
714 *
715 * Extracts the 12 bits, from a multicast address, to determine which
716 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
717 * incoming rx multicast addresses, to determine the bit-vector to check in
718 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
719 * by the MO field of the MCSTCTRL. The MO field is set during initalization
720 * to mc_filter_type.
721 **/
722static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
723{
724 u32 vector = 0;
725
726 switch (hw->mac.mc_filter_type) {
727 case 0: /* use bits [47:36] of the address */
728 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
729 break;
730 case 1: /* use bits [46:35] of the address */
731 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
732 break;
733 case 2: /* use bits [45:34] of the address */
734 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
735 break;
736 case 3: /* use bits [43:32] of the address */
737 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
738 break;
739 default: /* Invalid mc_filter_type */
740 hw_dbg(hw, "MC filter type param set incorrectly\n");
741 break;
742 }
743
744 /* vector can only be 12-bits or boundary will be exceeded */
745 vector &= 0xFFF;
746 return vector;
747}
748
749/**
750 * ixgbe_set_mta - Set bit-vector in multicast table
751 * @hw: pointer to hardware structure
752 * @hash_value: Multicast address hash value
753 *
754 * Sets the bit-vector in the multicast table.
755 **/
756static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
757{
758 u32 vector;
759 u32 vector_bit;
760 u32 vector_reg;
761 u32 mta_reg;
762
763 hw->addr_ctrl.mta_in_use++;
764
765 vector = ixgbe_mta_vector(hw, mc_addr);
766 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
767
768 /*
769 * The MTA is a register array of 128 32-bit registers. It is treated
770 * like an array of 4096 bits. We want to set bit
771 * BitArray[vector_value]. So we figure out what register the bit is
772 * in, read it, OR in the new bit, then write back the new value. The
773 * register is determined by the upper 7 bits of the vector value and
774 * the bit within that register are determined by the lower 5 bits of
775 * the value.
776 */
777 vector_reg = (vector >> 5) & 0x7F;
778 vector_bit = vector & 0x1F;
779 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
780 mta_reg |= (1 << vector_bit);
781 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
782}
783
784/**
785 * ixgbe_add_mc_addr - Adds a multicast address.
786 * @hw: pointer to hardware structure
787 * @mc_addr: new multicast address
788 *
789 * Adds it to unused receive address register or to the multicast table.
790 **/
791static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
792{
793 u32 rar_entries = hw->mac.num_rx_addrs;
794
795 hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
796 mc_addr[0], mc_addr[1], mc_addr[2],
797 mc_addr[3], mc_addr[4], mc_addr[5]);
798
799 /*
800 * Place this multicast address in the RAR if there is room,
801 * else put it in the MTA
802 */
803 if (hw->addr_ctrl.rar_used_count < rar_entries) {
804 ixgbe_set_rar(hw, hw->addr_ctrl.rar_used_count,
805 mc_addr, 0, IXGBE_RAH_AV);
806 hw_dbg(hw, "Added a multicast address to RAR[%d]\n",
807 hw->addr_ctrl.rar_used_count);
808 hw->addr_ctrl.rar_used_count++;
809 hw->addr_ctrl.mc_addr_in_rar_count++;
810 } else {
811 ixgbe_set_mta(hw, mc_addr);
812 }
813
814 hw_dbg(hw, "ixgbe_add_mc_addr Complete\n");
815}
816
817/**
818 * ixgbe_update_mc_addr_list - Updates MAC list of multicast addresses
819 * @hw: pointer to hardware structure
820 * @mc_addr_list: the list of new multicast addresses
821 * @mc_addr_count: number of addresses
822 * @pad: number of bytes between addresses in the list
823 *
824 * The given list replaces any existing list. Clears the MC addrs from receive
825 * address registers and the multicast table. Uses unsed receive address
826 * registers for the first multicast addresses, and hashes the rest into the
827 * multicast table.
828 **/
829s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
830 u32 mc_addr_count, u32 pad)
831{
832 u32 i;
833 u32 rar_entries = hw->mac.num_rx_addrs;
834
835 /*
836 * Set the new number of MC addresses that we are being requested to
837 * use.
838 */
839 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
840 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count;
841 hw->addr_ctrl.mc_addr_in_rar_count = 0;
842 hw->addr_ctrl.mta_in_use = 0;
843
844 /* Zero out the other receive addresses. */
845 hw_dbg(hw, "Clearing RAR[1-15]\n");
846 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
847 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
848 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
849 }
850
851 /* Clear the MTA */
852 hw_dbg(hw, " Clearing MTA\n");
853 for (i = 0; i < IXGBE_MC_TBL_SIZE; i++)
854 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
855
856 /* Add the new addresses */
857 for (i = 0; i < mc_addr_count; i++) {
858 hw_dbg(hw, " Adding the multicast addresses:\n");
859 ixgbe_add_mc_addr(hw, mc_addr_list +
860 (i * (IXGBE_ETH_LENGTH_OF_ADDRESS + pad)));
861 }
862
863 /* Enable mta */
864 if (hw->addr_ctrl.mta_in_use > 0)
865 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
866 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
867
868 hw_dbg(hw, "ixgbe_update_mc_addr_list Complete\n");
869 return 0;
870}
871
872/**
873 * ixgbe_clear_vfta - Clear VLAN filter table
874 * @hw: pointer to hardware structure
875 *
876 * Clears the VLAN filer table, and the VMDq index associated with the filter
877 **/
878static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
879{
880 u32 offset;
881 u32 vlanbyte;
882
883 for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++)
884 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
885
886 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
887 for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++)
888 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
889 0);
890
891 return 0;
892}
893
894/**
895 * ixgbe_set_vfta - Set VLAN filter table
896 * @hw: pointer to hardware structure
897 * @vlan: VLAN id to write to VLAN filter
898 * @vind: VMDq output index that maps queue to VLAN id in VFTA
899 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
900 *
901 * Turn on/off specified VLAN in the VLAN filter table.
902 **/
903s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind,
904 bool vlan_on)
905{
906 u32 VftaIndex;
907 u32 BitOffset;
908 u32 VftaReg;
909 u32 VftaByte;
910
911 /* Determine 32-bit word position in array */
912 VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */
913
914 /* Determine the location of the (VMD) queue index */
915 VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
916 BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
917
918 /* Set the nibble for VMD queue index */
919 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex));
920 VftaReg &= (~(0x0F << BitOffset));
921 VftaReg |= (vind << BitOffset);
922 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg);
923
924 /* Determine the location of the bit for this VLAN id */
925 BitOffset = vlan & 0x1F; /* lower five bits */
926
927 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex));
928 if (vlan_on)
929 /* Turn on this VLAN id */
930 VftaReg |= (1 << BitOffset);
931 else
932 /* Turn off this VLAN id */
933 VftaReg &= ~(1 << BitOffset);
934 IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg);
935
936 return 0;
937}
938
939/**
940 * ixgbe_setup_fc - Configure flow control settings
941 * @hw: pointer to hardware structure
942 * @packetbuf_num: packet buffer number (0-7)
943 *
944 * Configures the flow control settings based on SW configuration.
945 * This function is used for 802.3x flow control configuration only.
946 **/
947s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
948{
949 u32 frctl_reg;
950 u32 rmcs_reg;
951
952 if (packetbuf_num < 0 || packetbuf_num > 7)
953 hw_dbg(hw, "Invalid packet buffer number [%d], expected range"
954 "is 0-7\n", packetbuf_num);
955
956 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
957 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
958
959 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
960 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
961
962 /*
963 * We want to save off the original Flow Control configuration just in
964 * case we get disconnected and then reconnected into a different hub
965 * or switch with different Flow Control capabilities.
966 */
967 hw->fc.type = hw->fc.original_type;
968
969 /*
970 * The possible values of the "flow_control" parameter are:
971 * 0: Flow control is completely disabled
972 * 1: Rx flow control is enabled (we can receive pause frames but not
973 * send pause frames).
974 * 2: Tx flow control is enabled (we can send pause frames but we do not
975 * support receiving pause frames)
976 * 3: Both Rx and TX flow control (symmetric) are enabled.
977 * other: Invalid.
978 */
979 switch (hw->fc.type) {
980 case ixgbe_fc_none:
981 break;
982 case ixgbe_fc_rx_pause:
983 /*
984 * RX Flow control is enabled,
985 * and TX Flow control is disabled.
986 */
987 frctl_reg |= IXGBE_FCTRL_RFCE;
988 break;
989 case ixgbe_fc_tx_pause:
990 /*
991 * TX Flow control is enabled, and RX Flow control is disabled,
992 * by a software over-ride.
993 */
994 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
995 break;
996 case ixgbe_fc_full:
997 /*
998 * Flow control (both RX and TX) is enabled by a software
999 * over-ride.
1000 */
1001 frctl_reg |= IXGBE_FCTRL_RFCE;
1002 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
1003 break;
1004 default:
1005 /* We should never get here. The value should be 0-3. */
1006 hw_dbg(hw, "Flow control param set incorrectly\n");
1007 break;
1008 }
1009
1010 /* Enable 802.3x based flow control settings. */
1011 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
1012 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
1013
1014 /*
1015 * We need to set up the Receive Threshold high and low water
1016 * marks as well as (optionally) enabling the transmission of
1017 * XON frames.
1018 */
1019 if (hw->fc.type & ixgbe_fc_tx_pause) {
1020 if (hw->fc.send_xon) {
1021 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
1022 (hw->fc.low_water | IXGBE_FCRTL_XONE));
1023 } else {
1024 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
1025 hw->fc.low_water);
1026 }
1027 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
1028 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
1029 }
1030
1031 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
1032 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1033
1034 return 0;
1035}
1036
1037/**
1038 * ixgbe_disable_pcie_master - Disable PCI-express master access
1039 * @hw: pointer to hardware structure
1040 *
1041 * Disables PCI-Express master access and verifies there are no pending
1042 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1043 * bit hasn't caused the master requests to be disabled, else 0
1044 * is returned signifying master requests disabled.
1045 **/
1046s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1047{
1048 u32 ctrl;
1049 s32 i;
1050 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1051
1052 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1053 ctrl |= IXGBE_CTRL_GIO_DIS;
1054 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1055
1056 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1057 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1058 status = 0;
1059 break;
1060 }
1061 udelay(100);
1062 }
1063
1064 return status;
1065}
1066
1067
1068/**
1069 * ixgbe_acquire_swfw_sync - Aquire SWFW semaphore
1070 * @hw: pointer to hardware structure
1071 * @mask: Mask to specify wich semaphore to acquire
1072 *
1073 * Aquires the SWFW semaphore throught the GSSR register for the specified
1074 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1075 **/
1076s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1077{
1078 u32 gssr;
1079 u32 swmask = mask;
1080 u32 fwmask = mask << 5;
1081 s32 timeout = 200;
1082
1083 while (timeout) {
1084 if (ixgbe_get_eeprom_semaphore(hw))
1085 return -IXGBE_ERR_SWFW_SYNC;
1086
1087 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1088 if (!(gssr & (fwmask | swmask)))
1089 break;
1090
1091 /*
1092 * Firmware currently using resource (fwmask) or other software
1093 * thread currently using resource (swmask)
1094 */
1095 ixgbe_release_eeprom_semaphore(hw);
1096 msleep(5);
1097 timeout--;
1098 }
1099
1100 if (!timeout) {
1101 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
1102 return -IXGBE_ERR_SWFW_SYNC;
1103 }
1104
1105 gssr |= swmask;
1106 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1107
1108 ixgbe_release_eeprom_semaphore(hw);
1109 return 0;
1110}
1111
1112/**
1113 * ixgbe_release_swfw_sync - Release SWFW semaphore
1114 * @hw: pointer to hardware structure
1115 * @mask: Mask to specify wich semaphore to release
1116 *
1117 * Releases the SWFW semaphore throught the GSSR register for the specified
1118 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1119 **/
1120void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1121{
1122 u32 gssr;
1123 u32 swmask = mask;
1124
1125 ixgbe_get_eeprom_semaphore(hw);
1126
1127 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1128 gssr &= ~swmask;
1129 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1130
1131 ixgbe_release_eeprom_semaphore(hw);
1132}
1133
1134/**
1135 * ixgbe_read_analog_reg8- Reads 8 bit 82598 Atlas analog register
1136 * @hw: pointer to hardware structure
1137 * @reg: analog register to read
1138 * @val: read value
1139 *
1140 * Performs write operation to analog register specified.
1141 **/
1142s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1143{
1144 u32 atlas_ctl;
1145
1146 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1147 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1148 IXGBE_WRITE_FLUSH(hw);
1149 udelay(10);
1150 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1151 *val = (u8)atlas_ctl;
1152
1153 return 0;
1154}
1155
1156/**
1157 * ixgbe_write_analog_reg8- Writes 8 bit Atlas analog register
1158 * @hw: pointer to hardware structure
1159 * @reg: atlas register to write
1160 * @val: value to write
1161 *
1162 * Performs write operation to Atlas analog register specified.
1163 **/
1164s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1165{
1166 u32 atlas_ctl;
1167
1168 atlas_ctl = (reg << 8) | val;
1169 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1170 IXGBE_WRITE_FLUSH(hw);
1171 udelay(10);
1172
1173 return 0;
1174}
1175
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 23:17:20 -0500