1 files changed, 608 insertions, 306 deletions

diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index f5b2617111aa..a11ff0db9d25 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -33,20 +33,28 @@
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
 
-static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
-
 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
+static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
+static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
+static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
+                                        u16 count);
+static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
+static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
 
-static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
-static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
+static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
+static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
 static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
+static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
 
 /**
- *  ixgbe_start_hw - Prepare hardware for TX/RX
+ *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
  *  @hw: pointer to hardware structure
  *
  *  Starts the hardware by filling the bus info structure and media type, clears
@@ -54,7 +62,7 @@ static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
  *  table, VLAN filter table, calls routine to set up link and flow control
  *  settings, and leaves transmit and receive units disabled and uninitialized
  **/
-s32 ixgbe_start_hw(struct ixgbe_hw *hw)
+s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
 {
         u32 ctrl_ext;
 
@@ -62,22 +70,22 @@ s32 ixgbe_start_hw(struct ixgbe_hw *hw)
         hw->phy.media_type = hw->mac.ops.get_media_type(hw);
 
         /* Identify the PHY */
-        ixgbe_identify_phy(hw);
+        hw->phy.ops.identify(hw);
 
         /*
          * Store MAC address from RAR0, clear receive address registers, and
          * clear the multicast table
          */
-        ixgbe_init_rx_addrs(hw);
+        hw->mac.ops.init_rx_addrs(hw);
 
         /* Clear the VLAN filter table */
-        ixgbe_clear_vfta(hw);
+        hw->mac.ops.clear_vfta(hw);
 
         /* Set up link */
         hw->mac.ops.setup_link(hw);
 
         /* Clear statistics registers */
-        ixgbe_clear_hw_cntrs(hw);
+        hw->mac.ops.clear_hw_cntrs(hw);
 
         /* Set No Snoop Disable */
         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
@@ -92,34 +100,34 @@ s32 ixgbe_start_hw(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_init_hw - Generic hardware initialization
+ *  ixgbe_init_hw_generic - Generic hardware initialization
  *  @hw: pointer to hardware structure
  *
- *  Initialize the hardware by reseting the hardware, filling the bus info
+ *  Initialize the hardware by resetting the hardware, filling the bus info
  *  structure and media type, clears all on chip counters, initializes receive
  *  address registers, multicast table, VLAN filter table, calls routine to set
  *  up link and flow control settings, and leaves transmit and receive units
  *  disabled and uninitialized
  **/
-s32 ixgbe_init_hw(struct ixgbe_hw *hw)
+s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
 {
         /* Reset the hardware */
-        hw->mac.ops.reset(hw);
+        hw->mac.ops.reset_hw(hw);
 
         /* Start the HW */
-        ixgbe_start_hw(hw);
+        hw->mac.ops.start_hw(hw);
 
         return 0;
 }
 
 /**
- *  ixgbe_clear_hw_cntrs - Generic clear hardware counters
+ *  ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
  *  @hw: pointer to hardware structure
  *
  *  Clears all hardware statistics counters by reading them from the hardware
  *  Statistics counters are clear on read.
  **/
-static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
+s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
 {
         u16 i = 0;
 
@@ -191,7 +199,36 @@ static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_get_mac_addr - Generic get MAC address
+ *  ixgbe_read_pba_num_generic - Reads part number from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number from the EEPROM
+ *
+ *  Reads the part number from the EEPROM.
+ **/
+s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
+{
+        s32 ret_val;
+        u16 data;
+
+        ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
+        if (ret_val) {
+                hw_dbg(hw, "NVM Read Error\n");
+                return ret_val;
+        }
+        *pba_num = (u32)(data << 16);
+
+        ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
+        if (ret_val) {
+                hw_dbg(hw, "NVM Read Error\n");
+                return ret_val;
+        }
+        *pba_num |= data;
+
+        return 0;
+}
+
+/**
+ *  ixgbe_get_mac_addr_generic - Generic get MAC address
  *  @hw: pointer to hardware structure
  *  @mac_addr: Adapter MAC address
  *
@@ -199,7 +236,7 @@ static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
  *  A reset of the adapter must be performed prior to calling this function
  *  in order for the MAC address to have been loaded from the EEPROM into RAR0
  **/
-s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
+s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
 {
         u32 rar_high;
         u32 rar_low;
@@ -217,30 +254,8 @@ s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
         return 0;
 }
 
-s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num)
-{
-        s32 ret_val;
-        u16 data;
-
-        ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM0_PTR, &data);
-        if (ret_val) {
-                hw_dbg(hw, "NVM Read Error\n");
-                return ret_val;
-        }
-        *part_num = (u32)(data << 16);
-
-        ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM1_PTR, &data);
-        if (ret_val) {
-                hw_dbg(hw, "NVM Read Error\n");
-                return ret_val;
-        }
-        *part_num |= data;
-
-        return 0;
-}
-
 /**
- *  ixgbe_stop_adapter - Generic stop TX/RX units
+ *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
  *  @hw: pointer to hardware structure
  *
  *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
@@ -248,7 +263,7 @@ s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num)
  *  the shared code and drivers to determine if the adapter is in a stopped
  *  state and should not touch the hardware.
  **/
-s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
+s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
 {
         u32 number_of_queues;
         u32 reg_val;
@@ -264,6 +279,7 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
         reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
         reg_val &= ~(IXGBE_RXCTRL_RXEN);
         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
+        IXGBE_WRITE_FLUSH(hw);
         msleep(2);
 
         /* Clear interrupt mask to stop from interrupts being generated */
@@ -273,7 +289,7 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
         IXGBE_READ_REG(hw, IXGBE_EICR);
 
         /* Disable the transmit unit.  Each queue must be disabled. */
-        number_of_queues = hw->mac.num_tx_queues;
+        number_of_queues = hw->mac.max_tx_queues;
         for (i = 0; i < number_of_queues; i++) {
                 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
                 if (reg_val & IXGBE_TXDCTL_ENABLE) {
@@ -282,15 +298,22 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
                 }
         }
 
+        /*
+         * Prevent the PCI-E bus from from hanging by disabling PCI-E master
+         * access and verify no pending requests
+         */
+        if (ixgbe_disable_pcie_master(hw) != 0)
+                hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+
         return 0;
 }
 
 /**
- *  ixgbe_led_on - Turns on the software controllable LEDs.
+ *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
  *  @hw: pointer to hardware structure
  *  @index: led number to turn on
  **/
-s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
+s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
 {
         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
@@ -304,11 +327,11 @@ s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
 }
 
 /**
- *  ixgbe_led_off - Turns off the software controllable LEDs.
+ *  ixgbe_led_off_generic - Turns off the software controllable LEDs.
  *  @hw: pointer to hardware structure
  *  @index: led number to turn off
  **/
-s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
+s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
 {
         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
@@ -321,15 +344,14 @@ s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
         return 0;
 }
 
-
 /**
- *  ixgbe_init_eeprom - Initialize EEPROM params
+ *  ixgbe_init_eeprom_params_generic - Initialize EEPROM params
  *  @hw: pointer to hardware structure
  *
  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
  *  ixgbe_hw struct in order to set up EEPROM access.
  **/
-s32 ixgbe_init_eeprom(struct ixgbe_hw *hw)
+s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
 {
         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
         u32 eec;
@@ -337,6 +359,9 @@ s32 ixgbe_init_eeprom(struct ixgbe_hw *hw)
 
         if (eeprom->type == ixgbe_eeprom_uninitialized) {
                 eeprom->type = ixgbe_eeprom_none;
+                /* Set default semaphore delay to 10ms which is a well
+                 * tested value */
+                eeprom->semaphore_delay = 10;
 
                 /*
                  * Check for EEPROM present first.
@@ -369,18 +394,85 @@ s32 ixgbe_init_eeprom(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_read_eeprom - Read EEPROM word using EERD
+ *  ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be read
+ *  @data: read 16 bit value from EEPROM
+ *
+ *  Reads 16 bit value from EEPROM through bit-bang method
+ **/
+s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+                                       u16 *data)
+{
+        s32 status;
+        u16 word_in;
+        u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
+
+        hw->eeprom.ops.init_params(hw);
+
+        if (offset >= hw->eeprom.word_size) {
+                status = IXGBE_ERR_EEPROM;
+                goto out;
+        }
+
+        /* Prepare the EEPROM for reading  */
+        status = ixgbe_acquire_eeprom(hw);
+
+        if (status == 0) {
+                if (ixgbe_ready_eeprom(hw) != 0) {
+                        ixgbe_release_eeprom(hw);
+                        status = IXGBE_ERR_EEPROM;
+                }
+        }
+
+        if (status == 0) {
+                ixgbe_standby_eeprom(hw);
+
+                /*
+                 * Some SPI eeproms use the 8th address bit embedded in the
+                 * opcode
+                 */
+                if ((hw->eeprom.address_bits == 8) && (offset >= 128))
+                        read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
+
+                /* Send the READ command (opcode + addr) */
+                ixgbe_shift_out_eeprom_bits(hw, read_opcode,
+                                            IXGBE_EEPROM_OPCODE_BITS);
+                ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
+                                            hw->eeprom.address_bits);
+
+                /* Read the data. */
+                word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
+                *data = (word_in >> 8) | (word_in << 8);
+
+                /* End this read operation */
+                ixgbe_release_eeprom(hw);
+        }
+
+out:
+        return status;
+}
+
+/**
+ *  ixgbe_read_eeprom_generic - Read EEPROM word using EERD
  *  @hw: pointer to hardware structure
  *  @offset: offset of  word in the EEPROM to read
  *  @data: word read from the EEPROM
  *
  *  Reads a 16 bit word from the EEPROM using the EERD register.
  **/
-s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
+s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
 {
         u32 eerd;
         s32 status;
 
+        hw->eeprom.ops.init_params(hw);
+
+        if (offset >= hw->eeprom.word_size) {
+                status = IXGBE_ERR_EEPROM;
+                goto out;
+        }
+
         eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
                IXGBE_EEPROM_READ_REG_START;
 
@@ -393,6 +485,7 @@ s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
         else
                 hw_dbg(hw, "Eeprom read timed out\n");
 
+out:
         return status;
 }
 
@@ -420,6 +513,58 @@ static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
 }
 
 /**
+ *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
+ *  @hw: pointer to hardware structure
+ *
+ *  Prepares EEPROM for access using bit-bang method. This function should
+ *  be called before issuing a command to the EEPROM.
+ **/
+static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
+{
+        s32 status = 0;
+        u32 eec;
+        u32 i;
+
+        if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
+                status = IXGBE_ERR_SWFW_SYNC;
+
+        if (status == 0) {
+                eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+                /* Request EEPROM Access */
+                eec |= IXGBE_EEC_REQ;
+                IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+
+                for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
+                        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+                        if (eec & IXGBE_EEC_GNT)
+                                break;
+                        udelay(5);
+                }
+
+                /* Release if grant not acquired */
+                if (!(eec & IXGBE_EEC_GNT)) {
+                        eec &= ~IXGBE_EEC_REQ;
+                        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                        hw_dbg(hw, "Could not acquire EEPROM grant\n");
+
+                        ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+                        status = IXGBE_ERR_EEPROM;
+                }
+        }
+
+        /* Setup EEPROM for Read/Write */
+        if (status == 0) {
+                /* Clear CS and SK */
+                eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
+                IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                IXGBE_WRITE_FLUSH(hw);
+                udelay(1);
+        }
+        return status;
+}
+
+/**
  *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
  *  @hw: pointer to hardware structure
  *
@@ -503,6 +648,217 @@ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
 }
 
 /**
+ *  ixgbe_ready_eeprom - Polls for EEPROM ready
+ *  @hw: pointer to hardware structure
+ **/
+static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
+{
+        s32 status = 0;
+        u16 i;
+        u8 spi_stat_reg;
+
+        /*
+         * Read "Status Register" repeatedly until the LSB is cleared.  The
+         * EEPROM will signal that the command has been completed by clearing
+         * bit 0 of the internal status register.  If it's not cleared within
+         * 5 milliseconds, then error out.
+         */
+        for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
+                ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
+                                            IXGBE_EEPROM_OPCODE_BITS);
+                spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
+                if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
+                        break;
+
+                udelay(5);
+                ixgbe_standby_eeprom(hw);
+        };
+
+        /*
+         * On some parts, SPI write time could vary from 0-20mSec on 3.3V
+         * devices (and only 0-5mSec on 5V devices)
+         */
+        if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
+                hw_dbg(hw, "SPI EEPROM Status error\n");
+                status = IXGBE_ERR_EEPROM;
+        }
+
+        return status;
+}
+
+/**
+ *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
+ *  @hw: pointer to hardware structure
+ **/
+static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
+{
+        u32 eec;
+
+        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+        /* Toggle CS to flush commands */
+        eec |= IXGBE_EEC_CS;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+        IXGBE_WRITE_FLUSH(hw);
+        udelay(1);
+        eec &= ~IXGBE_EEC_CS;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+        IXGBE_WRITE_FLUSH(hw);
+        udelay(1);
+}
+
+/**
+ *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
+ *  @hw: pointer to hardware structure
+ *  @data: data to send to the EEPROM
+ *  @count: number of bits to shift out
+ **/
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
+                                        u16 count)
+{
+        u32 eec;
+        u32 mask;
+        u32 i;
+
+        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+        /*
+         * Mask is used to shift "count" bits of "data" out to the EEPROM
+         * one bit at a time.  Determine the starting bit based on count
+         */
+        mask = 0x01 << (count - 1);
+
+        for (i = 0; i < count; i++) {
+                /*
+                 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
+                 * "1", and then raising and then lowering the clock (the SK
+                 * bit controls the clock input to the EEPROM).  A "0" is
+                 * shifted out to the EEPROM by setting "DI" to "0" and then
+                 * raising and then lowering the clock.
+                 */
+                if (data & mask)
+                        eec |= IXGBE_EEC_DI;
+                else
+                        eec &= ~IXGBE_EEC_DI;
+
+                IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                IXGBE_WRITE_FLUSH(hw);
+
+                udelay(1);
+
+                ixgbe_raise_eeprom_clk(hw, &eec);
+                ixgbe_lower_eeprom_clk(hw, &eec);
+
+                /*
+                 * Shift mask to signify next bit of data to shift in to the
+                 * EEPROM
+                 */
+                mask = mask >> 1;
+        };
+
+        /* We leave the "DI" bit set to "0" when we leave this routine. */
+        eec &= ~IXGBE_EEC_DI;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+        IXGBE_WRITE_FLUSH(hw);
+}
+
+/**
+ *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
+ *  @hw: pointer to hardware structure
+ **/
+static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
+{
+        u32 eec;
+        u32 i;
+        u16 data = 0;
+
+        /*
+         * In order to read a register from the EEPROM, we need to shift
+         * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
+         * the clock input to the EEPROM (setting the SK bit), and then reading
+         * the value of the "DO" bit.  During this "shifting in" process the
+         * "DI" bit should always be clear.
+         */
+        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+        eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
+
+        for (i = 0; i < count; i++) {
+                data = data << 1;
+                ixgbe_raise_eeprom_clk(hw, &eec);
+
+                eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+                eec &= ~(IXGBE_EEC_DI);
+                if (eec & IXGBE_EEC_DO)
+                        data |= 1;
+
+                ixgbe_lower_eeprom_clk(hw, &eec);
+        }
+
+        return data;
+}
+
+/**
+ *  ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
+ *  @hw: pointer to hardware structure
+ *  @eec: EEC register's current value
+ **/
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+{
+        /*
+         * Raise the clock input to the EEPROM
+         * (setting the SK bit), then delay
+         */
+        *eec = *eec | IXGBE_EEC_SK;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+        IXGBE_WRITE_FLUSH(hw);
+        udelay(1);
+}
+
+/**
+ *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
+ *  @hw: pointer to hardware structure
+ *  @eecd: EECD's current value
+ **/
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+{
+        /*
+         * Lower the clock input to the EEPROM (clearing the SK bit), then
+         * delay
+         */
+        *eec = *eec & ~IXGBE_EEC_SK;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+        IXGBE_WRITE_FLUSH(hw);
+        udelay(1);
+}
+
+/**
+ *  ixgbe_release_eeprom - Release EEPROM, release semaphores
+ *  @hw: pointer to hardware structure
+ **/
+static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
+{
+        u32 eec;
+
+        eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+        eec |= IXGBE_EEC_CS;  /* Pull CS high */
+        eec &= ~IXGBE_EEC_SK; /* Lower SCK */
+
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+        IXGBE_WRITE_FLUSH(hw);
+
+        udelay(1);
+
+        /* Stop requesting EEPROM access */
+        eec &= ~IXGBE_EEC_REQ;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+
+        ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+}
+
+/**
  *  ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
  *  @hw: pointer to hardware structure
  **/
@@ -517,7 +873,7 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
 
         /* Include 0x0-0x3F in the checksum */
         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
-                if (ixgbe_read_eeprom(hw, i, &word) != 0) {
+                if (hw->eeprom.ops.read(hw, i, &word) != 0) {
                         hw_dbg(hw, "EEPROM read failed\n");
                         break;
                 }
@@ -526,15 +882,15 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
 
         /* Include all data from pointers except for the fw pointer */
         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
-                ixgbe_read_eeprom(hw, i, &pointer);
+                hw->eeprom.ops.read(hw, i, &pointer);
 
                 /* Make sure the pointer seems valid */
                 if (pointer != 0xFFFF && pointer != 0) {
-                        ixgbe_read_eeprom(hw, pointer, &length);
+                        hw->eeprom.ops.read(hw, pointer, &length);
 
                         if (length != 0xFFFF && length != 0) {
                                 for (j = pointer+1; j <= pointer+length; j++) {
-                                        ixgbe_read_eeprom(hw, j, &word);
+                                        hw->eeprom.ops.read(hw, j, &word);
                                         checksum += word;
                                 }
                         }
@@ -547,14 +903,15 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
+ *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
  *  @hw: pointer to hardware structure
  *  @checksum_val: calculated checksum
  *
  *  Performs checksum calculation and validates the EEPROM checksum.  If the
  *  caller does not need checksum_val, the value can be NULL.
  **/
-s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
+s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
+                                           u16 *checksum_val)
 {
         s32 status;
         u16 checksum;
@@ -565,12 +922,12 @@ s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
          * not continue or we could be in for a very long wait while every
          * EEPROM read fails
          */
-        status = ixgbe_read_eeprom(hw, 0, &checksum);
+        status = hw->eeprom.ops.read(hw, 0, &checksum);
 
         if (status == 0) {
                 checksum = ixgbe_calc_eeprom_checksum(hw);
 
-                ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
+                hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
 
                 /*
                  * Verify read checksum from EEPROM is the same as
@@ -590,6 +947,33 @@ s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
 }
 
 /**
+ *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
+{
+        s32 status;
+        u16 checksum;
+
+        /*
+         * Read the first word from the EEPROM. If this times out or fails, do
+         * not continue or we could be in for a very long wait while every
+         * EEPROM read fails
+         */
+        status = hw->eeprom.ops.read(hw, 0, &checksum);
+
+        if (status == 0) {
+                checksum = ixgbe_calc_eeprom_checksum(hw);
+                status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
+                                            checksum);
+        } else {
+                hw_dbg(hw, "EEPROM read failed\n");
+        }
+
+        return status;
+}
+
+/**
  *  ixgbe_validate_mac_addr - Validate MAC address
  *  @mac_addr: pointer to MAC address.
  *
@@ -607,58 +991,137 @@ s32 ixgbe_validate_mac_addr(u8 *mac_addr)
                 status = IXGBE_ERR_INVALID_MAC_ADDR;
         /* Reject the zero address */
         else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
-                 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
+                 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
                 status = IXGBE_ERR_INVALID_MAC_ADDR;
 
         return status;
 }
 
 /**
- *  ixgbe_set_rar - Set RX address register
+ *  ixgbe_set_rar_generic - Set Rx address register
  *  @hw: pointer to hardware structure
- *  @addr: Address to put into receive address register
  *  @index: Receive address register to write
- *  @vind: Vind to set RAR to
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq "set" or "pool" index
  *  @enable_addr: set flag that address is active
  *
  *  Puts an ethernet address into a receive address register.
  **/
-s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind,
-                  u32 enable_addr)
+s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                          u32 enable_addr)
 {
         u32 rar_low, rar_high;
+        u32 rar_entries = hw->mac.num_rar_entries;
+
+        /* setup VMDq pool selection before this RAR gets enabled */
+        hw->mac.ops.set_vmdq(hw, index, vmdq);
 
+        /* Make sure we are using a valid rar index range */
+        if (index < rar_entries) {
         /*
-         * HW expects these in little endian so we reverse the byte order from
-         * network order (big endian) to little endian
+                 * HW expects these in little endian so we reverse the byte
+                 * order from network order (big endian) to little endian
          */
         rar_low = ((u32)addr[0] |
                    ((u32)addr[1] << 8) |
                    ((u32)addr[2] << 16) |
                    ((u32)addr[3] << 24));
-
-        rar_high = ((u32)addr[4] |
-                    ((u32)addr[5] << 8) |
-                    ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK));
+                /*
+                 * Some parts put the VMDq setting in the extra RAH bits,
+                 * so save everything except the lower 16 bits that hold part
+                 * of the address and the address valid bit.
+                 */
+                rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+                rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
+                rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
 
         if (enable_addr != 0)
                 rar_high |= IXGBE_RAH_AV;
 
         IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
         IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+        } else {
+                hw_dbg(hw, "RAR index %d is out of range.\n", index);
+        }
+
+        return 0;
+}
+
+/**
+ *  ixgbe_clear_rar_generic - Remove Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *
+ *  Clears an ethernet address from a receive address register.
+ **/
+s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
+{
+        u32 rar_high;
+        u32 rar_entries = hw->mac.num_rar_entries;
+
+        /* Make sure we are using a valid rar index range */
+        if (index < rar_entries) {
+                /*
+                 * Some parts put the VMDq setting in the extra RAH bits,
+                 * so save everything except the lower 16 bits that hold part
+                 * of the address and the address valid bit.
+                 */
+                rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+                rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
+
+                IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
+                IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+        } else {
+                hw_dbg(hw, "RAR index %d is out of range.\n", index);
+        }
+
+        /* clear VMDq pool/queue selection for this RAR */
+        hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
 
         return 0;
 }
 
 /**
- *  ixgbe_init_rx_addrs - Initializes receive address filters.
+ *  ixgbe_enable_rar - Enable Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: index into the RAR table
+ *
+ *  Enables the select receive address register.
+ **/
+static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
+{
+        u32 rar_high;
+
+        rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+        rar_high |= IXGBE_RAH_AV;
+        IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+}
+
+/**
+ *  ixgbe_disable_rar - Disable Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: index into the RAR table
+ *
+ *  Disables the select receive address register.
+ **/
+static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
+{
+        u32 rar_high;
+
+        rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+        rar_high &= (~IXGBE_RAH_AV);
+        IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+}
+
+/**
+ *  ixgbe_init_rx_addrs_generic - Initializes receive address filters.
  *  @hw: pointer to hardware structure
  *
  *  Places the MAC address in receive address register 0 and clears the rest
- *  of the receive addresss registers. Clears the multicast table. Assumes
+ *  of the receive address registers. Clears the multicast table. Assumes
  *  the receiver is in reset when the routine is called.
  **/
-static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
+s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
 {
         u32 i;
         u32 rar_entries = hw->mac.num_rar_entries;
@@ -671,7 +1134,7 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
         if (ixgbe_validate_mac_addr(hw->mac.addr) ==
             IXGBE_ERR_INVALID_MAC_ADDR) {
                 /* Get the MAC address from the RAR0 for later reference */
-                ixgbe_get_mac_addr(hw, hw->mac.addr);
+                hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
 
                 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
                           hw->mac.addr[0], hw->mac.addr[1],
@@ -687,13 +1150,14 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
                 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
                           hw->mac.addr[4], hw->mac.addr[5]);
 
-                ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
+                hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
         }
+        hw->addr_ctrl.overflow_promisc = 0;
 
         hw->addr_ctrl.rar_used_count = 1;
 
         /* Zero out the other receive addresses. */
-        hw_dbg(hw, "Clearing RAR[1-15]\n");
+        hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
         for (i = 1; i < rar_entries; i++) {
                 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
                 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
@@ -708,6 +1172,9 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
         for (i = 0; i < hw->mac.mcft_size; i++)
                 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
 
+        if (hw->mac.ops.init_uta_tables)
+                hw->mac.ops.init_uta_tables(hw);
+
         return 0;
 }
 
@@ -718,7 +1185,7 @@ static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
  *
  *  Adds it to unused receive address register or goes into promiscuous mode.
  **/
-void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr)
+static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
 {
         u32 rar_entries = hw->mac.num_rar_entries;
         u32 rar;
@@ -733,7 +1200,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr)
         if (hw->addr_ctrl.rar_used_count < rar_entries) {
                 rar = hw->addr_ctrl.rar_used_count -
                       hw->addr_ctrl.mc_addr_in_rar_count;
-                ixgbe_set_rar(hw, rar, addr, 0, IXGBE_RAH_AV);
+                hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
                 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
                 hw->addr_ctrl.rar_used_count++;
         } else {
@@ -744,7 +1211,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr)
 }
 
 /**
- *  ixgbe_update_uc_addr_list - Updates MAC list of secondary addresses
+ *  ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
  *  @hw: pointer to hardware structure
  *  @addr_list: the list of new addresses
  *  @addr_count: number of addresses
@@ -757,7 +1224,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr)
  *  Drivers using secondary unicast addresses must set user_set_promisc when
  *  manually putting the device into promiscuous mode.
  **/
-s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
+s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
                               u32 addr_count, ixgbe_mc_addr_itr next)
 {
         u8 *addr;
@@ -787,7 +1254,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
         for (i = 0; i < addr_count; i++) {
                 hw_dbg(hw, " Adding the secondary addresses:\n");
                 addr = next(hw, &addr_list, &vmdq);
-                ixgbe_add_uc_addr(hw, addr);
+                ixgbe_add_uc_addr(hw, addr, vmdq);
         }
 
         if (hw->addr_ctrl.overflow_promisc) {
@@ -808,7 +1275,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
                 }
         }
 
-        hw_dbg(hw, "ixgbe_update_uc_addr_list Complete\n");
+        hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
         return 0;
 }
 
@@ -821,7 +1288,7 @@ s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
  *  bit-vector to set in the multicast table. The hardware uses 12 bits, from
  *  incoming rx multicast addresses, to determine the bit-vector to check in
  *  the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
- *  by the MO field of the MCSTCTRL. The MO field is set during initalization
+ *  by the MO field of the MCSTCTRL. The MO field is set during initialization
  *  to mc_filter_type.
  **/
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
@@ -907,10 +1374,10 @@ static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
          * else put it in the MTA
          */
         if (hw->addr_ctrl.rar_used_count < rar_entries) {
+                /* use RAR from the end up for multicast */
                 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1;
-                ixgbe_set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV);
-                hw_dbg(hw, "Added a multicast address to RAR[%d]\n",
-                          hw->addr_ctrl.rar_used_count);
+                hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV);
+                hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar);
                 hw->addr_ctrl.rar_used_count++;
                 hw->addr_ctrl.mc_addr_in_rar_count++;
         } else {
@@ -921,18 +1388,18 @@ static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
 }
 
 /**
- *  ixgbe_update_mc_addr_list - Updates MAC list of multicast addresses
+ *  ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
  *  @hw: pointer to hardware structure
  *  @mc_addr_list: the list of new multicast addresses
  *  @mc_addr_count: number of addresses
  *  @next: iterator function to walk the multicast address list
  *
  *  The given list replaces any existing list. Clears the MC addrs from receive
- *  address registers and the multicast table. Uses unsed receive address
+ *  address registers and the multicast table. Uses unused receive address
  *  registers for the first multicast addresses, and hashes the rest into the
  *  multicast table.
  **/
-s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
+s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
                               u32 mc_addr_count, ixgbe_mc_addr_itr next)
 {
         u32 i;
@@ -949,7 +1416,8 @@ s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
         hw->addr_ctrl.mta_in_use = 0;
 
         /* Zero out the other receive addresses. */
-        hw_dbg(hw, "Clearing RAR[1-15]\n");
+        hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count,
+                  rar_entries - 1);
         for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
                 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
                 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
@@ -971,188 +1439,53 @@ s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
 
-        hw_dbg(hw, "ixgbe_update_mc_addr_list Complete\n");
+        hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
         return 0;
 }
 
 /**
- *  ixgbe_clear_vfta - Clear VLAN filter table
+ *  ixgbe_enable_mc_generic - Enable multicast address in RAR
  *  @hw: pointer to hardware structure
  *
- *  Clears the VLAN filer table, and the VMDq index associated with the filter
+ *  Enables multicast address in RAR and the use of the multicast hash table.
  **/
-static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
+s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
 {
-        u32 offset;
-        u32 vlanbyte;
+        u32 i;
+        u32 rar_entries = hw->mac.num_rar_entries;
+        struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 
-        for (offset = 0; offset < hw->mac.vft_size; offset++)
-                IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
+        if (a->mc_addr_in_rar_count > 0)
+                for (i = (rar_entries - a->mc_addr_in_rar_count);
+                     i < rar_entries; i++)
+                        ixgbe_enable_rar(hw, i);
 
-        for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
-                for (offset = 0; offset < hw->mac.vft_size; offset++)
-                        IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
-                                        0);
+        if (a->mta_in_use > 0)
+                IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
+                                hw->mac.mc_filter_type);
 
         return 0;
 }
 
 /**
- *  ixgbe_set_vfta - Set VLAN filter table
+ *  ixgbe_disable_mc_generic - Disable multicast address in RAR
  *  @hw: pointer to hardware structure
- *  @vlan: VLAN id to write to VLAN filter
- *  @vind: VMDq output index that maps queue to VLAN id in VFTA
- *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
  *
- *  Turn on/off specified VLAN in the VLAN filter table.
+ *  Disables multicast address in RAR and the use of the multicast hash table.
  **/
-s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind,
-                   bool vlan_on)
+s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
 {
-        u32 VftaIndex;
-        u32 BitOffset;
-        u32 VftaReg;
-        u32 VftaByte;
-
-        /* Determine 32-bit word position in array */
-        VftaIndex = (vlan >> 5) & 0x7F;   /* upper seven bits */
-
-        /* Determine the location of the (VMD) queue index */
-        VftaByte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
-        BitOffset = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
-
-        /* Set the nibble for VMD queue index */
-        VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex));
-        VftaReg &= (~(0x0F << BitOffset));
-        VftaReg |= (vind << BitOffset);
-        IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg);
-
-        /* Determine the location of the bit for this VLAN id */
-        BitOffset = vlan & 0x1F;           /* lower five bits */
-
-        VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex));
-        if (vlan_on)
-                /* Turn on this VLAN id */
-                VftaReg |= (1 << BitOffset);
-        else
-                /* Turn off this VLAN id */
-                VftaReg &= ~(1 << BitOffset);
-        IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg);
-
-        return 0;
-}
-
-/**
- *  ixgbe_setup_fc - Configure flow control settings
- *  @hw: pointer to hardware structure
- *  @packetbuf_num: packet buffer number (0-7)
- *
- *  Configures the flow control settings based on SW configuration.
- *  This function is used for 802.3x flow control configuration only.
- **/
-s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
-{
-        u32 frctl_reg;
-        u32 rmcs_reg;
-
-        if (packetbuf_num < 0 || packetbuf_num > 7)
-                hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
-                       "is 0-7\n", packetbuf_num);
-
-        frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
-        frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
-
-        rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
-        rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
-
-        /*
-         * 10 gig parts do not have a word in the EEPROM to determine the
-         * default flow control setting, so we explicitly set it to full.
-         */
-        if (hw->fc.type == ixgbe_fc_default)
-                hw->fc.type = ixgbe_fc_full;
-
-        /*
-         * We want to save off the original Flow Control configuration just in
-         * case we get disconnected and then reconnected into a different hub
-         * or switch with different Flow Control capabilities.
-         */
-        hw->fc.type = hw->fc.original_type;
-
-        /*
-         * The possible values of the "flow_control" parameter are:
-         * 0: Flow control is completely disabled
-         * 1: Rx flow control is enabled (we can receive pause frames but not
-         *    send pause frames).
-         * 2: Tx flow control is enabled (we can send pause frames but we do not
-         *    support receiving pause frames)
-         * 3: Both Rx and TX flow control (symmetric) are enabled.
-         * other: Invalid.
-         */
-        switch (hw->fc.type) {
-        case ixgbe_fc_none:
-                break;
-        case ixgbe_fc_rx_pause:
-                /*
-                 * RX Flow control is enabled,
-                 * and TX Flow control is disabled.
-                 */
-                frctl_reg |= IXGBE_FCTRL_RFCE;
-                break;
-        case ixgbe_fc_tx_pause:
-                /*
-                 * TX Flow control is enabled, and RX Flow control is disabled,
-                 * by a software over-ride.
-                 */
-                rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
-                break;
-        case ixgbe_fc_full:
-                /*
-                 * Flow control (both RX and TX) is enabled by a software
-                 * over-ride.
-                 */
-                frctl_reg |= IXGBE_FCTRL_RFCE;
-                rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
-                break;
-        default:
-                /* We should never get here.  The value should be 0-3. */
-                hw_dbg(hw, "Flow control param set incorrectly\n");
-                break;
-        }
-
-        /* Enable 802.3x based flow control settings. */
-        IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
-        IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
-
-        /*
-         * Check for invalid software configuration, zeros are completely
-         * invalid for all parameters used past this point, and if we enable
-         * flow control with zero water marks, we blast flow control packets.
-         */
-        if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
-                hw_dbg(hw, "Flow control structure initialized incorrectly\n");
-                return IXGBE_ERR_INVALID_LINK_SETTINGS;
-        }
+        u32 i;
+        u32 rar_entries = hw->mac.num_rar_entries;
+        struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 
-        /*
-         * We need to set up the Receive Threshold high and low water
-         * marks as well as (optionally) enabling the transmission of
-         * XON frames.
-         */
-        if (hw->fc.type & ixgbe_fc_tx_pause) {
-                if (hw->fc.send_xon) {
-                        IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
-                                        (hw->fc.low_water | IXGBE_FCRTL_XONE));
-                } else {
-                        IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
-                                        hw->fc.low_water);
-                }
-                IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
-                                (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
-        }
+        if (a->mc_addr_in_rar_count > 0)
+                for (i = (rar_entries - a->mc_addr_in_rar_count);
+                     i < rar_entries; i++)
+                        ixgbe_disable_rar(hw, i);
 
-        IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
-        IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
+        if (a->mta_in_use > 0)
+                IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
 
         return 0;
 }
@@ -1168,13 +1501,24 @@ s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
  **/
 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
 {
-        u32 ctrl;
-        s32 i;
+        u32 i;
+        u32 reg_val;
+        u32 number_of_queues;
         s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 
-        ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
-        ctrl |= IXGBE_CTRL_GIO_DIS;
-        IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
+        /* Disable the receive unit by stopping each queue */
+        number_of_queues = hw->mac.max_rx_queues;
+        for (i = 0; i < number_of_queues; i++) {
+                reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
+                if (reg_val & IXGBE_RXDCTL_ENABLE) {
+                        reg_val &= ~IXGBE_RXDCTL_ENABLE;
+                        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
+                }
+        }
+
+        reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
+        reg_val |= IXGBE_CTRL_GIO_DIS;
+        IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
 
         for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
                 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
@@ -1189,11 +1533,11 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
 
 
 /**
- *  ixgbe_acquire_swfw_sync - Aquire SWFW semaphore
+ *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
  *  @hw: pointer to hardware structure
- *  @mask: Mask to specify wich semaphore to acquire
+ *  @mask: Mask to specify which semaphore to acquire
  *
- *  Aquires the SWFW semaphore throught the GSSR register for the specified
+ *  Acquires the SWFW semaphore thought the GSSR register for the specified
  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
  **/
 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
@@ -1235,9 +1579,9 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
 /**
  *  ixgbe_release_swfw_sync - Release SWFW semaphore
  *  @hw: pointer to hardware structure
- *  @mask: Mask to specify wich semaphore to release
+ *  @mask: Mask to specify which semaphore to release
  *
- *  Releases the SWFW semaphore throught the GSSR register for the specified
+ *  Releases the SWFW semaphore thought the GSSR register for the specified
  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
  **/
 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
@@ -1254,45 +1598,3 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
         ixgbe_release_eeprom_semaphore(hw);
 }
 
-/**
- *  ixgbe_read_analog_reg8 - Reads 8 bit Atlas analog register
- *  @hw: pointer to hardware structure
- *  @reg: analog register to read
- *  @val: read value
- *
- *  Performs write operation to analog register specified.
- **/
-s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
-{
-        u32  atlas_ctl;
-
-        IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
-                        IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
-        IXGBE_WRITE_FLUSH(hw);
-        udelay(10);
-        atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
-        *val = (u8)atlas_ctl;
-
-        return 0;
-}
-
-/**
- *  ixgbe_write_analog_reg8 - Writes 8 bit Atlas analog register
- *  @hw: pointer to hardware structure
- *  @reg: atlas register to write
- *  @val: value to write
- *
- *  Performs write operation to Atlas analog register specified.
- **/
-s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
-{
-        u32  atlas_ctl;
-
-        atlas_ctl = (reg << 8) | val;
-        IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
-        IXGBE_WRITE_FLUSH(hw);
-        udelay(10);
-
-        return 0;
-}
-