aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ixgbe/ixgbe_82598.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_82598.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c186
1 files changed, 128 insertions, 58 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 4791238c3f6e..03eb54f4f1cc 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -75,18 +75,49 @@ static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
75static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 75static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
76{ 76{
77 struct ixgbe_mac_info *mac = &hw->mac; 77 struct ixgbe_mac_info *mac = &hw->mac;
78
79 /* Call PHY identify routine to get the phy type */
80 ixgbe_identify_phy_generic(hw);
81
82 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
83 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
84 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
85 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
86 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
87 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
88
89 return 0;
90}
91
92/**
93 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
94 * @hw: pointer to hardware structure
95 *
96 * Initialize any function pointers that were not able to be
97 * set during get_invariants because the PHY/SFP type was
98 * not known. Perform the SFP init if necessary.
99 *
100 **/
101s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
102{
103 struct ixgbe_mac_info *mac = &hw->mac;
78 struct ixgbe_phy_info *phy = &hw->phy; 104 struct ixgbe_phy_info *phy = &hw->phy;
79 s32 ret_val = 0; 105 s32 ret_val = 0;
80 u16 list_offset, data_offset; 106 u16 list_offset, data_offset;
81 107
82 /* Set the bus information prior to PHY identification */ 108 /* Identify the PHY */
83 mac->ops.get_bus_info(hw); 109 phy->ops.identify(hw);
84 110
85 /* Call PHY identify routine to get the phy type */ 111 /* Overwrite the link function pointers if copper PHY */
86 ixgbe_identify_phy_generic(hw); 112 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
113 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
114 mac->ops.setup_link_speed =
115 &ixgbe_setup_copper_link_speed_82598;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_82598;
118 }
87 119
88 /* PHY Init */ 120 switch (hw->phy.type) {
89 switch (phy->type) {
90 case ixgbe_phy_tn: 121 case ixgbe_phy_tn:
91 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 122 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
92 phy->ops.get_firmware_version = 123 phy->ops.get_firmware_version =
@@ -106,8 +137,8 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
106 137
107 /* Check to see if SFP+ module is supported */ 138 /* Check to see if SFP+ module is supported */
108 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 139 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
109 &list_offset, 140 &list_offset,
110 &data_offset); 141 &data_offset);
111 if (ret_val != 0) { 142 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 143 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
113 goto out; 144 goto out;
@@ -117,21 +148,6 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
117 break; 148 break;
118 } 149 }
119 150
120 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
121 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
122 mac->ops.setup_link_speed =
123 &ixgbe_setup_copper_link_speed_82598;
124 mac->ops.get_link_capabilities =
125 &ixgbe_get_copper_link_capabilities_82598;
126 }
127
128 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
129 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
130 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
131 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
132 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
133 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
134
135out: 151out:
136 return ret_val; 152 return ret_val;
137} 153}
@@ -149,12 +165,19 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
149 bool *autoneg) 165 bool *autoneg)
150{ 166{
151 s32 status = 0; 167 s32 status = 0;
168 u32 autoc = 0;
152 169
153 /* 170 /*
154 * Determine link capabilities based on the stored value of AUTOC, 171 * Determine link capabilities based on the stored value of AUTOC,
155 * which represents EEPROM defaults. 172 * which represents EEPROM defaults. If AUTOC value has not been
173 * stored, use the current register value.
156 */ 174 */
157 switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) { 175 if (hw->mac.orig_link_settings_stored)
176 autoc = hw->mac.orig_autoc;
177 else
178 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
179
180 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
158 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 181 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
159 *speed = IXGBE_LINK_SPEED_1GB_FULL; 182 *speed = IXGBE_LINK_SPEED_1GB_FULL;
160 *autoneg = false; 183 *autoneg = false;
@@ -173,9 +196,9 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
173 case IXGBE_AUTOC_LMS_KX4_AN: 196 case IXGBE_AUTOC_LMS_KX4_AN:
174 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 197 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
175 *speed = IXGBE_LINK_SPEED_UNKNOWN; 198 *speed = IXGBE_LINK_SPEED_UNKNOWN;
176 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP) 199 if (autoc & IXGBE_AUTOC_KX4_SUPP)
177 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 200 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
178 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP) 201 if (autoc & IXGBE_AUTOC_KX_SUPP)
179 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 202 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
180 *autoneg = true; 203 *autoneg = true;
181 break; 204 break;
@@ -322,6 +345,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
322 } 345 }
323 346
324 /* Enable 802.3x based flow control settings. */ 347 /* Enable 802.3x based flow control settings. */
348 fctrl_reg |= IXGBE_FCTRL_DPF;
325 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 349 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
326 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 350 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
327 351
@@ -380,9 +404,11 @@ static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
380 * because it causes the controller to just blast out fc packets. 404 * because it causes the controller to just blast out fc packets.
381 */ 405 */
382 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 406 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
383 hw_dbg(hw, "Invalid water mark configuration\n"); 407 if (hw->fc.requested_mode != ixgbe_fc_none) {
384 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 408 hw_dbg(hw, "Invalid water mark configuration\n");
385 goto out; 409 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
410 goto out;
411 }
386 } 412 }
387 413
388 /* 414 /*
@@ -716,14 +742,23 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
716 } 742 }
717 743
718 /* Reset PHY */ 744 /* Reset PHY */
719 if (hw->phy.reset_disable == false) 745 if (hw->phy.reset_disable == false) {
746 /* PHY ops must be identified and initialized prior to reset */
747
748 /* Init PHY and function pointers, perform SFP setup */
749 status = hw->phy.ops.init(hw);
750 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
751 goto reset_hw_out;
752
720 hw->phy.ops.reset(hw); 753 hw->phy.ops.reset(hw);
754 }
721 755
722 /* 756 /*
723 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 757 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
724 * access and verify no pending requests before reset 758 * access and verify no pending requests before reset
725 */ 759 */
726 if (ixgbe_disable_pcie_master(hw) != 0) { 760 status = ixgbe_disable_pcie_master(hw);
761 if (status != 0) {
727 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 762 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
728 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); 763 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
729 } 764 }
@@ -770,6 +805,7 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
770 /* Store the permanent mac address */ 805 /* Store the permanent mac address */
771 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 806 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
772 807
808reset_hw_out:
773 return status; 809 return status;
774} 810}
775 811
@@ -998,35 +1034,56 @@ out:
998static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1034static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
999{ 1035{
1000 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1036 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1037 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1038 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1039 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1040 u16 ext_ability = 0;
1041
1042 hw->phy.ops.identify(hw);
1043
1044 /* Copper PHY must be checked before AUTOC LMS to determine correct
1045 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1046 if (hw->phy.type == ixgbe_phy_tn ||
1047 hw->phy.type == ixgbe_phy_cu_unknown) {
1048 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1049 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1050 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1051 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1052 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1053 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1054 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1055 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1056 goto out;
1057 }
1001 1058
1002 switch (hw->device_id) { 1059 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1003 case IXGBE_DEV_ID_82598: 1060 case IXGBE_AUTOC_LMS_1G_AN:
1004 /* Default device ID is mezzanine card KX/KX4 */ 1061 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1005 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 1062 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1006 IXGBE_PHYSICAL_LAYER_1000BASE_KX); 1063 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1007 break; 1064 else
1008 case IXGBE_DEV_ID_82598_BX: 1065 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1009 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1010 case IXGBE_DEV_ID_82598EB_CX4:
1011 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1012 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1013 break;
1014 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1015 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1016 break; 1066 break;
1017 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1067 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1018 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1068 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1019 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1069 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1020 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1070 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1071 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1072 else /* XAUI */
1073 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1021 break; 1074 break;
1022 case IXGBE_DEV_ID_82598EB_XF_LR: 1075 case IXGBE_AUTOC_LMS_KX4_AN:
1023 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1076 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1077 if (autoc & IXGBE_AUTOC_KX_SUPP)
1078 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1079 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1080 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1024 break; 1081 break;
1025 case IXGBE_DEV_ID_82598AT: 1082 default:
1026 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1027 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1028 break; 1083 break;
1029 case IXGBE_DEV_ID_82598EB_SFP_LOM: 1084 }
1085
1086 if (hw->phy.type == ixgbe_phy_nl) {
1030 hw->phy.ops.identify_sfp(hw); 1087 hw->phy.ops.identify_sfp(hw);
1031 1088
1032 switch (hw->phy.sfp_type) { 1089 switch (hw->phy.sfp_type) {
@@ -1043,13 +1100,25 @@ static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1043 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1100 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1044 break; 1101 break;
1045 } 1102 }
1046 break; 1103 }
1047 1104
1105 switch (hw->device_id) {
1106 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1107 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1108 break;
1109 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1110 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1111 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1112 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1113 break;
1114 case IXGBE_DEV_ID_82598EB_XF_LR:
1115 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1116 break;
1048 default: 1117 default:
1049 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1050 break; 1118 break;
1051 } 1119 }
1052 1120
1121out:
1053 return physical_layer; 1122 return physical_layer;
1054} 1123}
1055 1124
@@ -1099,6 +1168,7 @@ static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1099static struct ixgbe_phy_operations phy_ops_82598 = { 1168static struct ixgbe_phy_operations phy_ops_82598 = {
1100 .identify = &ixgbe_identify_phy_generic, 1169 .identify = &ixgbe_identify_phy_generic,
1101 .identify_sfp = &ixgbe_identify_sfp_module_generic, 1170 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1171 .init = &ixgbe_init_phy_ops_82598,
1102 .reset = &ixgbe_reset_phy_generic, 1172 .reset = &ixgbe_reset_phy_generic,
1103 .read_reg = &ixgbe_read_phy_reg_generic, 1173 .read_reg = &ixgbe_read_phy_reg_generic,
1104 .write_reg = &ixgbe_write_phy_reg_generic, 1174 .write_reg = &ixgbe_write_phy_reg_generic,