aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ixgbe/ixgbe_82598.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_82598.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c600
1 files changed, 507 insertions, 93 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 07261406cd63..a08a267f1667 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -39,68 +39,80 @@
39#define IXGBE_82598_MC_TBL_SIZE 128 39#define IXGBE_82598_MC_TBL_SIZE 128
40#define IXGBE_82598_VFT_TBL_SIZE 128 40#define IXGBE_82598_VFT_TBL_SIZE 128
41 41
42static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw); 42static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
43static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed, 43 ixgbe_link_speed *speed,
44 bool *autoneg); 44 bool *autoneg);
45static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
46 u32 *speed, bool *autoneg);
47static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 45static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
48static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 47static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
49static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed, 48static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
50 bool *link_up, 49 ixgbe_link_speed *speed,
51 bool link_up_wait_to_complete); 50 bool *link_up, bool link_up_wait_to_complete);
52static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, u32 speed, 51static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
53 bool autoneg, 52 ixgbe_link_speed speed,
54 bool autoneg_wait_to_complete); 53 bool autoneg,
54 bool autoneg_wait_to_complete);
55static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 55static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
56static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed, 56static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
57 bool autoneg, 57 ixgbe_link_speed speed,
58 bool autoneg_wait_to_complete); 58 bool autoneg,
59 bool autoneg_wait_to_complete);
59static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 60static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
61static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
62static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
63static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
64 u32 vind, bool vlan_on);
65static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
66static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index);
67static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
68static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
69static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
70static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
71static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw);
60 72
61 73/**
74 */
62static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 75static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
63{ 76{
64 hw->mac.num_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 77 struct ixgbe_mac_info *mac = &hw->mac;
65 hw->mac.num_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 78 struct ixgbe_phy_info *phy = &hw->phy;
66 hw->mac.mcft_size = IXGBE_82598_MC_TBL_SIZE; 79
67 hw->mac.vft_size = IXGBE_82598_VFT_TBL_SIZE; 80 /* Call PHY identify routine to get the phy type */
68 hw->mac.num_rar_entries = IXGBE_82598_RAR_ENTRIES; 81 ixgbe_identify_phy_generic(hw);
69 82
70 /* PHY ops are filled in by default properly for Fiber only */ 83 /* PHY Init */
71 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 84 switch (phy->type) {
72 hw->mac.ops.setup_link = &ixgbe_setup_copper_link_82598; 85 default:
73 hw->mac.ops.setup_link_speed = &ixgbe_setup_copper_link_speed_82598; 86 break;
74 hw->mac.ops.get_link_settings = 87 }
75 &ixgbe_get_copper_link_settings_82598; 88
76 89 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
77 /* Call PHY identify routine to get the phy type */ 90 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
78 ixgbe_identify_phy(hw); 91 mac->ops.setup_link_speed =
79 92 &ixgbe_setup_copper_link_speed_82598;
80 switch (hw->phy.type) { 93 mac->ops.get_link_capabilities =
81 case ixgbe_phy_tn: 94 &ixgbe_get_copper_link_capabilities_82598;
82 hw->phy.ops.setup_link = &ixgbe_setup_tnx_phy_link;
83 hw->phy.ops.check_link = &ixgbe_check_tnx_phy_link;
84 hw->phy.ops.setup_link_speed =
85 &ixgbe_setup_tnx_phy_link_speed;
86 break;
87 default:
88 break;
89 }
90 } 95 }
91 96
97 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
98 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
99 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
100 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
101 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
102
92 return 0; 103 return 0;
93} 104}
94 105
95/** 106/**
96 * ixgbe_get_link_settings_82598 - Determines default link settings 107 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
97 * @hw: pointer to hardware structure 108 * @hw: pointer to hardware structure
98 * @speed: pointer to link speed 109 * @speed: pointer to link speed
99 * @autoneg: boolean auto-negotiation value 110 * @autoneg: boolean auto-negotiation value
100 * 111 *
101 * Determines the default link settings by reading the AUTOC register. 112 * Determines the link capabilities by reading the AUTOC register.
102 **/ 113 **/
103static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed, 114static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
115 ixgbe_link_speed *speed,
104 bool *autoneg) 116 bool *autoneg)
105{ 117{
106 s32 status = 0; 118 s32 status = 0;
@@ -150,15 +162,16 @@ static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed,
150} 162}
151 163
152/** 164/**
153 * ixgbe_get_copper_link_settings_82598 - Determines default link settings 165 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
154 * @hw: pointer to hardware structure 166 * @hw: pointer to hardware structure
155 * @speed: pointer to link speed 167 * @speed: pointer to link speed
156 * @autoneg: boolean auto-negotiation value 168 * @autoneg: boolean auto-negotiation value
157 * 169 *
158 * Determines the default link settings by reading the AUTOC register. 170 * Determines the link capabilities by reading the AUTOC register.
159 **/ 171 **/
160static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw, 172s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
161 u32 *speed, bool *autoneg) 173 ixgbe_link_speed *speed,
174 bool *autoneg)
162{ 175{
163 s32 status = IXGBE_ERR_LINK_SETUP; 176 s32 status = IXGBE_ERR_LINK_SETUP;
164 u16 speed_ability; 177 u16 speed_ability;
@@ -166,7 +179,7 @@ static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
166 *speed = 0; 179 *speed = 0;
167 *autoneg = true; 180 *autoneg = true;
168 181
169 status = ixgbe_read_phy_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 182 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
170 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 183 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 &speed_ability); 184 &speed_ability);
172 185
@@ -199,9 +212,6 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
199 case IXGBE_DEV_ID_82598EB_XF_LR: 212 case IXGBE_DEV_ID_82598EB_XF_LR:
200 media_type = ixgbe_media_type_fiber; 213 media_type = ixgbe_media_type_fiber;
201 break; 214 break;
202 case IXGBE_DEV_ID_82598AT_DUAL_PORT:
203 media_type = ixgbe_media_type_copper;
204 break;
205 default: 215 default:
206 media_type = ixgbe_media_type_unknown; 216 media_type = ixgbe_media_type_unknown;
207 break; 217 break;
@@ -211,6 +221,122 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
211} 221}
212 222
213/** 223/**
224 * ixgbe_setup_fc_82598 - Configure flow control settings
225 * @hw: pointer to hardware structure
226 * @packetbuf_num: packet buffer number (0-7)
227 *
228 * Configures the flow control settings based on SW configuration. This
229 * function is used for 802.3x flow control configuration only.
230 **/
231s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
232{
233 u32 frctl_reg;
234 u32 rmcs_reg;
235
236 if (packetbuf_num < 0 || packetbuf_num > 7) {
237 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
238 " 0-7\n", packetbuf_num);
239 }
240
241 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
242 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
243
244 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
245 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
246
247 /*
248 * 10 gig parts do not have a word in the EEPROM to determine the
249 * default flow control setting, so we explicitly set it to full.
250 */
251 if (hw->fc.type == ixgbe_fc_default)
252 hw->fc.type = ixgbe_fc_full;
253
254 /*
255 * We want to save off the original Flow Control configuration just in
256 * case we get disconnected and then reconnected into a different hub
257 * or switch with different Flow Control capabilities.
258 */
259 hw->fc.original_type = hw->fc.type;
260
261 /*
262 * The possible values of the "flow_control" parameter are:
263 * 0: Flow control is completely disabled
264 * 1: Rx flow control is enabled (we can receive pause frames but not
265 * send pause frames).
266 * 2: Tx flow control is enabled (we can send pause frames but we do not
267 * support receiving pause frames)
268 * 3: Both Rx and Tx flow control (symmetric) are enabled.
269 * other: Invalid.
270 */
271 switch (hw->fc.type) {
272 case ixgbe_fc_none:
273 break;
274 case ixgbe_fc_rx_pause:
275 /*
276 * Rx Flow control is enabled,
277 * and Tx Flow control is disabled.
278 */
279 frctl_reg |= IXGBE_FCTRL_RFCE;
280 break;
281 case ixgbe_fc_tx_pause:
282 /*
283 * Tx Flow control is enabled, and Rx Flow control is disabled,
284 * by a software over-ride.
285 */
286 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
287 break;
288 case ixgbe_fc_full:
289 /*
290 * Flow control (both Rx and Tx) is enabled by a software
291 * over-ride.
292 */
293 frctl_reg |= IXGBE_FCTRL_RFCE;
294 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
295 break;
296 default:
297 /* We should never get here. The value should be 0-3. */
298 hw_dbg(hw, "Flow control param set incorrectly\n");
299 break;
300 }
301
302 /* Enable 802.3x based flow control settings. */
303 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
304 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
305
306 /*
307 * Check for invalid software configuration, zeros are completely
308 * invalid for all parameters used past this point, and if we enable
309 * flow control with zero water marks, we blast flow control packets.
310 */
311 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
312 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
313 return IXGBE_ERR_INVALID_LINK_SETTINGS;
314 }
315
316 /*
317 * We need to set up the Receive Threshold high and low water
318 * marks as well as (optionally) enabling the transmission of
319 * XON frames.
320 */
321 if (hw->fc.type & ixgbe_fc_tx_pause) {
322 if (hw->fc.send_xon) {
323 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
324 (hw->fc.low_water | IXGBE_FCRTL_XONE));
325 } else {
326 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
327 hw->fc.low_water);
328 }
329 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
330 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
331 }
332
333 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
334 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
335
336 return 0;
337}
338
339/**
214 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 340 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
215 * @hw: pointer to hardware structure 341 * @hw: pointer to hardware structure
216 * 342 *
@@ -254,8 +380,7 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
254 } 380 }
255 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 381 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
256 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 382 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
257 hw_dbg(hw, 383 hw_dbg(hw, "Autonegotiation did not complete.\n");
258 "Autonegotiation did not complete.\n");
259 } 384 }
260 } 385 }
261 } 386 }
@@ -265,8 +390,8 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
265 * case we get disconnected and then reconnected into a different hub 390 * case we get disconnected and then reconnected into a different hub
266 * or switch with different Flow Control capabilities. 391 * or switch with different Flow Control capabilities.
267 */ 392 */
268 hw->fc.type = hw->fc.original_type; 393 hw->fc.original_type = hw->fc.type;
269 ixgbe_setup_fc(hw, 0); 394 ixgbe_setup_fc_82598(hw, 0);
270 395
271 /* Add delay to filter out noises during initial link setup */ 396 /* Add delay to filter out noises during initial link setup */
272 msleep(50); 397 msleep(50);
@@ -283,15 +408,13 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
283 * 408 *
284 * Reads the links register to determine if link is up and the current speed 409 * Reads the links register to determine if link is up and the current speed
285 **/ 410 **/
286static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed, 411static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
287 bool *link_up, 412 bool *link_up, bool link_up_wait_to_complete)
288 bool link_up_wait_to_complete)
289{ 413{
290 u32 links_reg; 414 u32 links_reg;
291 u32 i; 415 u32 i;
292 416
293 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 417 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
294
295 if (link_up_wait_to_complete) { 418 if (link_up_wait_to_complete) {
296 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 419 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
297 if (links_reg & IXGBE_LINKS_UP) { 420 if (links_reg & IXGBE_LINKS_UP) {
@@ -318,6 +441,7 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
318 return 0; 441 return 0;
319} 442}
320 443
444
321/** 445/**
322 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 446 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
323 * @hw: pointer to hardware structure 447 * @hw: pointer to hardware structure
@@ -328,18 +452,18 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
328 * Set the link speed in the AUTOC register and restarts link. 452 * Set the link speed in the AUTOC register and restarts link.
329 **/ 453 **/
330static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 454static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
331 u32 speed, bool autoneg, 455 ixgbe_link_speed speed, bool autoneg,
332 bool autoneg_wait_to_complete) 456 bool autoneg_wait_to_complete)
333{ 457{
334 s32 status = 0; 458 s32 status = 0;
335 459
336 /* If speed is 10G, then check for CX4 or XAUI. */ 460 /* If speed is 10G, then check for CX4 or XAUI. */
337 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 461 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
338 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) 462 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
339 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 463 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
340 else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) 464 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {
341 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 465 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
342 else if (autoneg) { 466 } else if (autoneg) {
343 /* BX mode - Autonegotiate 1G */ 467 /* BX mode - Autonegotiate 1G */
344 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 468 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
345 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 469 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
@@ -358,7 +482,7 @@ static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
358 * ixgbe_hw This will write the AUTOC register based on the new 482 * ixgbe_hw This will write the AUTOC register based on the new
359 * stored values 483 * stored values
360 */ 484 */
361 hw->mac.ops.setup_link(hw); 485 ixgbe_setup_mac_link_82598(hw);
362 } 486 }
363 487
364 return status; 488 return status;
@@ -376,18 +500,17 @@ static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
376 **/ 500 **/
377static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 501static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
378{ 502{
379 s32 status = 0; 503 s32 status;
380 504
381 /* Restart autonegotiation on PHY */ 505 /* Restart autonegotiation on PHY */
382 if (hw->phy.ops.setup_link) 506 status = hw->phy.ops.setup_link(hw);
383 status = hw->phy.ops.setup_link(hw);
384 507
385 /* Set MAC to KX/KX4 autoneg, which defaultis to Parallel detection */ 508 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
386 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 509 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
387 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 510 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
388 511
389 /* Set up MAC */ 512 /* Set up MAC */
390 hw->mac.ops.setup_link(hw); 513 ixgbe_setup_mac_link_82598(hw);
391 514
392 return status; 515 return status;
393} 516}
@@ -401,14 +524,14 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
401 * 524 *
402 * Sets the link speed in the AUTOC register in the MAC and restarts link. 525 * Sets the link speed in the AUTOC register in the MAC and restarts link.
403 **/ 526 **/
404static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed, 527static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
528 ixgbe_link_speed speed,
405 bool autoneg, 529 bool autoneg,
406 bool autoneg_wait_to_complete) 530 bool autoneg_wait_to_complete)
407{ 531{
408 s32 status = 0; 532 s32 status;
409 533
410 /* Setup the PHY according to input speed */ 534 /* Setup the PHY according to input speed */
411 if (hw->phy.ops.setup_link_speed)
412 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 535 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
413 autoneg_wait_to_complete); 536 autoneg_wait_to_complete);
414 537
@@ -417,7 +540,7 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
417 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 540 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
418 541
419 /* Set up MAC */ 542 /* Set up MAC */
420 hw->mac.ops.setup_link(hw); 543 ixgbe_setup_mac_link_82598(hw);
421 544
422 return status; 545 return status;
423} 546}
@@ -426,7 +549,7 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
426 * ixgbe_reset_hw_82598 - Performs hardware reset 549 * ixgbe_reset_hw_82598 - Performs hardware reset
427 * @hw: pointer to hardware structure 550 * @hw: pointer to hardware structure
428 * 551 *
429 * Resets the hardware by reseting the transmit and receive units, masks and 552 * Resets the hardware by resetting the transmit and receive units, masks and
430 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 553 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
431 * reset. 554 * reset.
432 **/ 555 **/
@@ -440,35 +563,44 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
440 u8 analog_val; 563 u8 analog_val;
441 564
442 /* Call adapter stop to disable tx/rx and clear interrupts */ 565 /* Call adapter stop to disable tx/rx and clear interrupts */
443 ixgbe_stop_adapter(hw); 566 hw->mac.ops.stop_adapter(hw);
444 567
445 /* 568 /*
446 * Power up the Atlas TX lanes if they are currently powered down. 569 * Power up the Atlas Tx lanes if they are currently powered down.
447 * Atlas TX lanes are powered down for MAC loopback tests, but 570 * Atlas Tx lanes are powered down for MAC loopback tests, but
448 * they are not automatically restored on reset. 571 * they are not automatically restored on reset.
449 */ 572 */
450 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 573 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
451 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 574 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
452 /* Enable TX Atlas so packets can be transmitted again */ 575 /* Enable Tx Atlas so packets can be transmitted again */
453 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 576 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
577 &analog_val);
454 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 578 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
455 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, analog_val); 579 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
580 analog_val);
456 581
457 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &analog_val); 582 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
583 &analog_val);
458 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 584 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
459 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, analog_val); 585 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
586 analog_val);
460 587
461 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &analog_val); 588 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
589 &analog_val);
462 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 590 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
463 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, analog_val); 591 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
592 analog_val);
464 593
465 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &analog_val); 594 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
595 &analog_val);
466 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 596 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
467 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, analog_val); 597 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
598 analog_val);
468 } 599 }
469 600
470 /* Reset PHY */ 601 /* Reset PHY */
471 ixgbe_reset_phy(hw); 602 if (hw->phy.reset_disable == false)
603 hw->phy.ops.reset(hw);
472 604
473 /* 605 /*
474 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 606 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
@@ -527,23 +659,305 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
527 } 659 }
528 660
529 /* Store the permanent mac address */ 661 /* Store the permanent mac address */
530 ixgbe_get_mac_addr(hw, hw->mac.perm_addr); 662 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
531 663
532 return status; 664 return status;
533} 665}
534 666
667/**
668 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
669 * @hw: pointer to hardware struct
670 * @rar: receive address register index to associate with a VMDq index
671 * @vmdq: VMDq set index
672 **/
673s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
674{
675 u32 rar_high;
676
677 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
678 rar_high &= ~IXGBE_RAH_VIND_MASK;
679 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
680 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
681 return 0;
682}
683
684/**
685 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
686 * @hw: pointer to hardware struct
687 * @rar: receive address register index to associate with a VMDq index
688 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
689 **/
690static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
691{
692 u32 rar_high;
693 u32 rar_entries = hw->mac.num_rar_entries;
694
695 if (rar < rar_entries) {
696 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
697 if (rar_high & IXGBE_RAH_VIND_MASK) {
698 rar_high &= ~IXGBE_RAH_VIND_MASK;
699 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
700 }
701 } else {
702 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
703 }
704
705 return 0;
706}
707
708/**
709 * ixgbe_set_vfta_82598 - Set VLAN filter table
710 * @hw: pointer to hardware structure
711 * @vlan: VLAN id to write to VLAN filter
712 * @vind: VMDq output index that maps queue to VLAN id in VFTA
713 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
714 *
715 * Turn on/off specified VLAN in the VLAN filter table.
716 **/
717s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
718 bool vlan_on)
719{
720 u32 regindex;
721 u32 bitindex;
722 u32 bits;
723 u32 vftabyte;
724
725 if (vlan > 4095)
726 return IXGBE_ERR_PARAM;
727
728 /* Determine 32-bit word position in array */
729 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
730
731 /* Determine the location of the (VMD) queue index */
732 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
733 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
734
735 /* Set the nibble for VMD queue index */
736 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
737 bits &= (~(0x0F << bitindex));
738 bits |= (vind << bitindex);
739 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
740
741 /* Determine the location of the bit for this VLAN id */
742 bitindex = vlan & 0x1F; /* lower five bits */
743
744 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
745 if (vlan_on)
746 /* Turn on this VLAN id */
747 bits |= (1 << bitindex);
748 else
749 /* Turn off this VLAN id */
750 bits &= ~(1 << bitindex);
751 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
752
753 return 0;
754}
755
756/**
757 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
758 * @hw: pointer to hardware structure
759 *
760 * Clears the VLAN filer table, and the VMDq index associated with the filter
761 **/
762static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
763{
764 u32 offset;
765 u32 vlanbyte;
766
767 for (offset = 0; offset < hw->mac.vft_size; offset++)
768 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
769
770 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
771 for (offset = 0; offset < hw->mac.vft_size; offset++)
772 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
773 0);
774
775 return 0;
776}
777
778/**
779 * ixgbe_blink_led_start_82598 - Blink LED based on index.
780 * @hw: pointer to hardware structure
781 * @index: led number to blink
782 **/
783static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
784{
785 ixgbe_link_speed speed = 0;
786 bool link_up = 0;
787 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
788 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
789
790 /*
791 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
792 * force it if link is down.
793 */
794 hw->mac.ops.check_link(hw, &speed, &link_up, false);
795
796 if (!link_up) {
797 autoc_reg |= IXGBE_AUTOC_FLU;
798 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
799 msleep(10);
800 }
801
802 led_reg &= ~IXGBE_LED_MODE_MASK(index);
803 led_reg |= IXGBE_LED_BLINK(index);
804 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
805 IXGBE_WRITE_FLUSH(hw);
806
807 return 0;
808}
809
810/**
811 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
812 * @hw: pointer to hardware structure
813 * @index: led number to stop blinking
814 **/
815static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
816{
817 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
818 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
819
820 autoc_reg &= ~IXGBE_AUTOC_FLU;
821 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
822 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
823
824 led_reg &= ~IXGBE_LED_MODE_MASK(index);
825 led_reg &= ~IXGBE_LED_BLINK(index);
826 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
827 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
828 IXGBE_WRITE_FLUSH(hw);
829
830 return 0;
831}
832
833/**
834 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
835 * @hw: pointer to hardware structure
836 * @reg: analog register to read
837 * @val: read value
838 *
839 * Performs read operation to Atlas analog register specified.
840 **/
841s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
842{
843 u32 atlas_ctl;
844
845 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
846 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
847 IXGBE_WRITE_FLUSH(hw);
848 udelay(10);
849 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
850 *val = (u8)atlas_ctl;
851
852 return 0;
853}
854
855/**
856 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
857 * @hw: pointer to hardware structure
858 * @reg: atlas register to write
859 * @val: value to write
860 *
861 * Performs write operation to Atlas analog register specified.
862 **/
863s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
864{
865 u32 atlas_ctl;
866
867 atlas_ctl = (reg << 8) | val;
868 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
869 IXGBE_WRITE_FLUSH(hw);
870 udelay(10);
871
872 return 0;
873}
874
875/**
876 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
877 * @hw: pointer to hardware structure
878 *
879 * Determines physical layer capabilities of the current configuration.
880 **/
881s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
882{
883 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
884
885 switch (hw->device_id) {
886 case IXGBE_DEV_ID_82598EB_CX4:
887 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
888 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
889 break;
890 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
891 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
892 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
893 break;
894 case IXGBE_DEV_ID_82598EB_XF_LR:
895 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
896 break;
897
898 default:
899 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
900 break;
901 }
902
903 return physical_layer;
904}
905
535static struct ixgbe_mac_operations mac_ops_82598 = { 906static struct ixgbe_mac_operations mac_ops_82598 = {
536 .reset = &ixgbe_reset_hw_82598, 907 .init_hw = &ixgbe_init_hw_generic,
908 .reset_hw = &ixgbe_reset_hw_82598,
909 .start_hw = &ixgbe_start_hw_generic,
910 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
537 .get_media_type = &ixgbe_get_media_type_82598, 911 .get_media_type = &ixgbe_get_media_type_82598,
912 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
913 .get_mac_addr = &ixgbe_get_mac_addr_generic,
914 .stop_adapter = &ixgbe_stop_adapter_generic,
915 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
916 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
538 .setup_link = &ixgbe_setup_mac_link_82598, 917 .setup_link = &ixgbe_setup_mac_link_82598,
539 .check_link = &ixgbe_check_mac_link_82598,
540 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598, 918 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
541 .get_link_settings = &ixgbe_get_link_settings_82598, 919 .check_link = &ixgbe_check_mac_link_82598,
920 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
921 .led_on = &ixgbe_led_on_generic,
922 .led_off = &ixgbe_led_off_generic,
923 .blink_led_start = &ixgbe_blink_led_start_82598,
924 .blink_led_stop = &ixgbe_blink_led_stop_82598,
925 .set_rar = &ixgbe_set_rar_generic,
926 .clear_rar = &ixgbe_clear_rar_generic,
927 .set_vmdq = &ixgbe_set_vmdq_82598,
928 .clear_vmdq = &ixgbe_clear_vmdq_82598,
929 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
930 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
931 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
932 .enable_mc = &ixgbe_enable_mc_generic,
933 .disable_mc = &ixgbe_disable_mc_generic,
934 .clear_vfta = &ixgbe_clear_vfta_82598,
935 .set_vfta = &ixgbe_set_vfta_82598,
936 .setup_fc = &ixgbe_setup_fc_82598,
937};
938
939static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
940 .init_params = &ixgbe_init_eeprom_params_generic,
941 .read = &ixgbe_read_eeprom_generic,
942 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
943 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
944};
945
946static struct ixgbe_phy_operations phy_ops_82598 = {
947 .identify = &ixgbe_identify_phy_generic,
948 /* .identify_sfp = &ixgbe_identify_sfp_module_generic, */
949 .reset = &ixgbe_reset_phy_generic,
950 .read_reg = &ixgbe_read_phy_reg_generic,
951 .write_reg = &ixgbe_write_phy_reg_generic,
952 .setup_link = &ixgbe_setup_phy_link_generic,
953 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
542}; 954};
543 955
544struct ixgbe_info ixgbe_82598_info = { 956struct ixgbe_info ixgbe_82598_info = {
545 .mac = ixgbe_mac_82598EB, 957 .mac = ixgbe_mac_82598EB,
546 .get_invariants = &ixgbe_get_invariants_82598, 958 .get_invariants = &ixgbe_get_invariants_82598,
547 .mac_ops = &mac_ops_82598, 959 .mac_ops = &mac_ops_82598,
960 .eeprom_ops = &eeprom_ops_82598,
961 .phy_ops = &phy_ops_82598,
548}; 962};
549 963
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 23:39:46 -0500