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Diffstat (limited to 'drivers/net/ixgbe/ixgbe_82598.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c628
1 files changed, 521 insertions, 107 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index f96358b641af..7cddcfba809e 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -20,7 +20,6 @@
20 the file called "COPYING". 20 the file called "COPYING".
21 21
22 Contact Information: 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 25
@@ -36,67 +35,62 @@
36#define IXGBE_82598_MAX_TX_QUEUES 32 35#define IXGBE_82598_MAX_TX_QUEUES 32
37#define IXGBE_82598_MAX_RX_QUEUES 64 36#define IXGBE_82598_MAX_RX_QUEUES 64
38#define IXGBE_82598_RAR_ENTRIES 16 37#define IXGBE_82598_RAR_ENTRIES 16
38#define IXGBE_82598_MC_TBL_SIZE 128
39#define IXGBE_82598_VFT_TBL_SIZE 128
39 40
40static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw); 41static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
41static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed, 42 ixgbe_link_speed *speed,
42 bool *autoneg); 43 bool *autoneg);
43static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
44 u32 *speed, bool *autoneg);
45static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
47static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
48 bool *link_up);
49static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
50 bool autoneg,
51 bool autoneg_wait_to_complete);
52static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 44static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
53static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed, 45static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
54 bool autoneg, 46 ixgbe_link_speed speed,
55 bool autoneg_wait_to_complete); 47 bool autoneg,
56static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 48 bool autoneg_wait_to_complete);
57
58 49
50/**
51 */
59static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 52static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
60{ 53{
61 hw->mac.num_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 54 struct ixgbe_mac_info *mac = &hw->mac;
62 hw->mac.num_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 55 struct ixgbe_phy_info *phy = &hw->phy;
63 hw->mac.num_rx_addrs = IXGBE_82598_RAR_ENTRIES; 56
64 57 /* Call PHY identify routine to get the phy type */
65 /* PHY ops are filled in by default properly for Fiber only */ 58 ixgbe_identify_phy_generic(hw);
66 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 59
67 hw->mac.ops.setup_link = &ixgbe_setup_copper_link_82598; 60 /* PHY Init */
68 hw->mac.ops.setup_link_speed = &ixgbe_setup_copper_link_speed_82598; 61 switch (phy->type) {
69 hw->mac.ops.get_link_settings = 62 default:
70 &ixgbe_get_copper_link_settings_82598; 63 break;
71
72 /* Call PHY identify routine to get the phy type */
73 ixgbe_identify_phy(hw);
74
75 switch (hw->phy.type) {
76 case ixgbe_phy_tn:
77 hw->phy.ops.setup_link = &ixgbe_setup_tnx_phy_link;
78 hw->phy.ops.check_link = &ixgbe_check_tnx_phy_link;
79 hw->phy.ops.setup_link_speed =
80 &ixgbe_setup_tnx_phy_link_speed;
81 break;
82 default:
83 break;
84 }
85 } 64 }
86 65
66 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
67 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
68 mac->ops.setup_link_speed =
69 &ixgbe_setup_copper_link_speed_82598;
70 mac->ops.get_link_capabilities =
71 &ixgbe_get_copper_link_capabilities_82598;
72 }
73
74 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
75 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
76 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
77 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
78 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
79
87 return 0; 80 return 0;
88} 81}
89 82
90/** 83/**
91 * ixgbe_get_link_settings_82598 - Determines default link settings 84 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
92 * @hw: pointer to hardware structure 85 * @hw: pointer to hardware structure
93 * @speed: pointer to link speed 86 * @speed: pointer to link speed
94 * @autoneg: boolean auto-negotiation value 87 * @autoneg: boolean auto-negotiation value
95 * 88 *
96 * Determines the default link settings by reading the AUTOC register. 89 * Determines the link capabilities by reading the AUTOC register.
97 **/ 90 **/
98static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed, 91static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
99 bool *autoneg) 92 ixgbe_link_speed *speed,
93 bool *autoneg)
100{ 94{
101 s32 status = 0; 95 s32 status = 0;
102 s32 autoc_reg; 96 s32 autoc_reg;
@@ -145,15 +139,16 @@ static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed,
145} 139}
146 140
147/** 141/**
148 * ixgbe_get_copper_link_settings_82598 - Determines default link settings 142 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
149 * @hw: pointer to hardware structure 143 * @hw: pointer to hardware structure
150 * @speed: pointer to link speed 144 * @speed: pointer to link speed
151 * @autoneg: boolean auto-negotiation value 145 * @autoneg: boolean auto-negotiation value
152 * 146 *
153 * Determines the default link settings by reading the AUTOC register. 147 * Determines the link capabilities by reading the AUTOC register.
154 **/ 148 **/
155static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw, 149s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
156 u32 *speed, bool *autoneg) 150 ixgbe_link_speed *speed,
151 bool *autoneg)
157{ 152{
158 s32 status = IXGBE_ERR_LINK_SETUP; 153 s32 status = IXGBE_ERR_LINK_SETUP;
159 u16 speed_ability; 154 u16 speed_ability;
@@ -161,9 +156,9 @@ static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
161 *speed = 0; 156 *speed = 0;
162 *autoneg = true; 157 *autoneg = true;
163 158
164 status = ixgbe_read_phy_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 159 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
165 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 160 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
166 &speed_ability); 161 &speed_ability);
167 162
168 if (status == 0) { 163 if (status == 0) {
169 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 164 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
@@ -191,11 +186,9 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
191 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 186 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
192 case IXGBE_DEV_ID_82598EB_CX4: 187 case IXGBE_DEV_ID_82598EB_CX4:
193 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 188 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
189 case IXGBE_DEV_ID_82598EB_XF_LR:
194 media_type = ixgbe_media_type_fiber; 190 media_type = ixgbe_media_type_fiber;
195 break; 191 break;
196 case IXGBE_DEV_ID_82598AT_DUAL_PORT:
197 media_type = ixgbe_media_type_copper;
198 break;
199 default: 192 default:
200 media_type = ixgbe_media_type_unknown; 193 media_type = ixgbe_media_type_unknown;
201 break; 194 break;
@@ -205,6 +198,122 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
205} 198}
206 199
207/** 200/**
201 * ixgbe_setup_fc_82598 - Configure flow control settings
202 * @hw: pointer to hardware structure
203 * @packetbuf_num: packet buffer number (0-7)
204 *
205 * Configures the flow control settings based on SW configuration. This
206 * function is used for 802.3x flow control configuration only.
207 **/
208s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
209{
210 u32 frctl_reg;
211 u32 rmcs_reg;
212
213 if (packetbuf_num < 0 || packetbuf_num > 7) {
214 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
215 " 0-7\n", packetbuf_num);
216 }
217
218 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
219 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
220
221 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
222 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
223
224 /*
225 * 10 gig parts do not have a word in the EEPROM to determine the
226 * default flow control setting, so we explicitly set it to full.
227 */
228 if (hw->fc.type == ixgbe_fc_default)
229 hw->fc.type = ixgbe_fc_full;
230
231 /*
232 * We want to save off the original Flow Control configuration just in
233 * case we get disconnected and then reconnected into a different hub
234 * or switch with different Flow Control capabilities.
235 */
236 hw->fc.original_type = hw->fc.type;
237
238 /*
239 * The possible values of the "flow_control" parameter are:
240 * 0: Flow control is completely disabled
241 * 1: Rx flow control is enabled (we can receive pause frames but not
242 * send pause frames).
243 * 2: Tx flow control is enabled (we can send pause frames but we do not
244 * support receiving pause frames)
245 * 3: Both Rx and Tx flow control (symmetric) are enabled.
246 * other: Invalid.
247 */
248 switch (hw->fc.type) {
249 case ixgbe_fc_none:
250 break;
251 case ixgbe_fc_rx_pause:
252 /*
253 * Rx Flow control is enabled,
254 * and Tx Flow control is disabled.
255 */
256 frctl_reg |= IXGBE_FCTRL_RFCE;
257 break;
258 case ixgbe_fc_tx_pause:
259 /*
260 * Tx Flow control is enabled, and Rx Flow control is disabled,
261 * by a software over-ride.
262 */
263 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
264 break;
265 case ixgbe_fc_full:
266 /*
267 * Flow control (both Rx and Tx) is enabled by a software
268 * over-ride.
269 */
270 frctl_reg |= IXGBE_FCTRL_RFCE;
271 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
272 break;
273 default:
274 /* We should never get here. The value should be 0-3. */
275 hw_dbg(hw, "Flow control param set incorrectly\n");
276 break;
277 }
278
279 /* Enable 802.3x based flow control settings. */
280 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
281 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
282
283 /*
284 * Check for invalid software configuration, zeros are completely
285 * invalid for all parameters used past this point, and if we enable
286 * flow control with zero water marks, we blast flow control packets.
287 */
288 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
289 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
290 return IXGBE_ERR_INVALID_LINK_SETTINGS;
291 }
292
293 /*
294 * We need to set up the Receive Threshold high and low water
295 * marks as well as (optionally) enabling the transmission of
296 * XON frames.
297 */
298 if (hw->fc.type & ixgbe_fc_tx_pause) {
299 if (hw->fc.send_xon) {
300 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
301 (hw->fc.low_water | IXGBE_FCRTL_XONE));
302 } else {
303 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
304 hw->fc.low_water);
305 }
306 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
307 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
308 }
309
310 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
311 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
312
313 return 0;
314}
315
316/**
208 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 317 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
209 * @hw: pointer to hardware structure 318 * @hw: pointer to hardware structure
210 * 319 *
@@ -248,8 +357,7 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
248 } 357 }
249 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 358 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
250 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 359 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
251 hw_dbg(hw, 360 hw_dbg(hw, "Autonegotiation did not complete.\n");
252 "Autonegotiation did not complete.\n");
253 } 361 }
254 } 362 }
255 } 363 }
@@ -259,8 +367,8 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
259 * case we get disconnected and then reconnected into a different hub 367 * case we get disconnected and then reconnected into a different hub
260 * or switch with different Flow Control capabilities. 368 * or switch with different Flow Control capabilities.
261 */ 369 */
262 hw->fc.type = hw->fc.original_type; 370 hw->fc.original_type = hw->fc.type;
263 ixgbe_setup_fc(hw, 0); 371 ixgbe_setup_fc_82598(hw, 0);
264 372
265 /* Add delay to filter out noises during initial link setup */ 373 /* Add delay to filter out noises during initial link setup */
266 msleep(50); 374 msleep(50);
@@ -273,20 +381,35 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
273 * @hw: pointer to hardware structure 381 * @hw: pointer to hardware structure
274 * @speed: pointer to link speed 382 * @speed: pointer to link speed
275 * @link_up: true is link is up, false otherwise 383 * @link_up: true is link is up, false otherwise
384 * @link_up_wait_to_complete: bool used to wait for link up or not
276 * 385 *
277 * Reads the links register to determine if link is up and the current speed 386 * Reads the links register to determine if link is up and the current speed
278 **/ 387 **/
279static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed, 388static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
280 bool *link_up) 389 ixgbe_link_speed *speed, bool *link_up,
390 bool link_up_wait_to_complete)
281{ 391{
282 u32 links_reg; 392 u32 links_reg;
393 u32 i;
283 394
284 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 395 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
285 396 if (link_up_wait_to_complete) {
286 if (links_reg & IXGBE_LINKS_UP) 397 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
287 *link_up = true; 398 if (links_reg & IXGBE_LINKS_UP) {
288 else 399 *link_up = true;
289 *link_up = false; 400 break;
401 } else {
402 *link_up = false;
403 }
404 msleep(100);
405 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
406 }
407 } else {
408 if (links_reg & IXGBE_LINKS_UP)
409 *link_up = true;
410 else
411 *link_up = false;
412 }
290 413
291 if (links_reg & IXGBE_LINKS_SPEED) 414 if (links_reg & IXGBE_LINKS_SPEED)
292 *speed = IXGBE_LINK_SPEED_10GB_FULL; 415 *speed = IXGBE_LINK_SPEED_10GB_FULL;
@@ -296,6 +419,7 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
296 return 0; 419 return 0;
297} 420}
298 421
422
299/** 423/**
300 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 424 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
301 * @hw: pointer to hardware structure 425 * @hw: pointer to hardware structure
@@ -306,18 +430,18 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
306 * Set the link speed in the AUTOC register and restarts link. 430 * Set the link speed in the AUTOC register and restarts link.
307 **/ 431 **/
308static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 432static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
309 u32 speed, bool autoneg, 433 ixgbe_link_speed speed, bool autoneg,
310 bool autoneg_wait_to_complete) 434 bool autoneg_wait_to_complete)
311{ 435{
312 s32 status = 0; 436 s32 status = 0;
313 437
314 /* If speed is 10G, then check for CX4 or XAUI. */ 438 /* If speed is 10G, then check for CX4 or XAUI. */
315 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 439 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
316 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) 440 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
317 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 441 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
318 else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) 442 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {
319 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 443 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
320 else if (autoneg) { 444 } else if (autoneg) {
321 /* BX mode - Autonegotiate 1G */ 445 /* BX mode - Autonegotiate 1G */
322 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 446 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
323 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 447 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
@@ -336,7 +460,7 @@ static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
336 * ixgbe_hw This will write the AUTOC register based on the new 460 * ixgbe_hw This will write the AUTOC register based on the new
337 * stored values 461 * stored values
338 */ 462 */
339 hw->mac.ops.setup_link(hw); 463 ixgbe_setup_mac_link_82598(hw);
340 } 464 }
341 465
342 return status; 466 return status;
@@ -354,18 +478,17 @@ static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
354 **/ 478 **/
355static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 479static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
356{ 480{
357 s32 status = 0; 481 s32 status;
358 482
359 /* Restart autonegotiation on PHY */ 483 /* Restart autonegotiation on PHY */
360 if (hw->phy.ops.setup_link) 484 status = hw->phy.ops.setup_link(hw);
361 status = hw->phy.ops.setup_link(hw);
362 485
363 /* Set MAC to KX/KX4 autoneg, which defaultis to Parallel detection */ 486 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
364 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 487 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
365 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 488 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
366 489
367 /* Set up MAC */ 490 /* Set up MAC */
368 hw->mac.ops.setup_link(hw); 491 ixgbe_setup_mac_link_82598(hw);
369 492
370 return status; 493 return status;
371} 494}
@@ -379,23 +502,23 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
379 * 502 *
380 * Sets the link speed in the AUTOC register in the MAC and restarts link. 503 * Sets the link speed in the AUTOC register in the MAC and restarts link.
381 **/ 504 **/
382static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed, 505static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
383 bool autoneg, 506 ixgbe_link_speed speed,
384 bool autoneg_wait_to_complete) 507 bool autoneg,
508 bool autoneg_wait_to_complete)
385{ 509{
386 s32 status = 0; 510 s32 status;
387 511
388 /* Setup the PHY according to input speed */ 512 /* Setup the PHY according to input speed */
389 if (hw->phy.ops.setup_link_speed) 513 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
390 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 514 autoneg_wait_to_complete);
391 autoneg_wait_to_complete);
392 515
393 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 516 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
394 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 517 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
395 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 518 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
396 519
397 /* Set up MAC */ 520 /* Set up MAC */
398 hw->mac.ops.setup_link(hw); 521 ixgbe_setup_mac_link_82598(hw);
399 522
400 return status; 523 return status;
401} 524}
@@ -404,7 +527,7 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
404 * ixgbe_reset_hw_82598 - Performs hardware reset 527 * ixgbe_reset_hw_82598 - Performs hardware reset
405 * @hw: pointer to hardware structure 528 * @hw: pointer to hardware structure
406 * 529 *
407 * Resets the hardware by reseting the transmit and receive units, masks and 530 * Resets the hardware by resetting the transmit and receive units, masks and
408 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 531 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
409 * reset. 532 * reset.
410 **/ 533 **/
@@ -418,35 +541,44 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
418 u8 analog_val; 541 u8 analog_val;
419 542
420 /* Call adapter stop to disable tx/rx and clear interrupts */ 543 /* Call adapter stop to disable tx/rx and clear interrupts */
421 ixgbe_stop_adapter(hw); 544 hw->mac.ops.stop_adapter(hw);
422 545
423 /* 546 /*
424 * Power up the Atlas TX lanes if they are currently powered down. 547 * Power up the Atlas Tx lanes if they are currently powered down.
425 * Atlas TX lanes are powered down for MAC loopback tests, but 548 * Atlas Tx lanes are powered down for MAC loopback tests, but
426 * they are not automatically restored on reset. 549 * they are not automatically restored on reset.
427 */ 550 */
428 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 551 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
429 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 552 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
430 /* Enable TX Atlas so packets can be transmitted again */ 553 /* Enable Tx Atlas so packets can be transmitted again */
431 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 554 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
555 &analog_val);
432 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 556 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
433 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, analog_val); 557 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
558 analog_val);
434 559
435 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &analog_val); 560 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
561 &analog_val);
436 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 562 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
437 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, analog_val); 563 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
564 analog_val);
438 565
439 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &analog_val); 566 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
567 &analog_val);
440 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 568 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
441 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, analog_val); 569 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
570 analog_val);
442 571
443 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &analog_val); 572 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
573 &analog_val);
444 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 574 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
445 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, analog_val); 575 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
576 analog_val);
446 } 577 }
447 578
448 /* Reset PHY */ 579 /* Reset PHY */
449 ixgbe_reset_phy(hw); 580 if (hw->phy.reset_disable == false)
581 hw->phy.ops.reset(hw);
450 582
451 /* 583 /*
452 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 584 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
@@ -499,29 +631,311 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
499 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 631 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
500 } else { 632 } else {
501 hw->mac.link_attach_type = 633 hw->mac.link_attach_type =
502 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 634 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
503 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 635 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
504 hw->mac.link_settings_loaded = true; 636 hw->mac.link_settings_loaded = true;
505 } 637 }
506 638
507 /* Store the permanent mac address */ 639 /* Store the permanent mac address */
508 ixgbe_get_mac_addr(hw, hw->mac.perm_addr); 640 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
509 641
510 return status; 642 return status;
511} 643}
512 644
645/**
646 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
647 * @hw: pointer to hardware struct
648 * @rar: receive address register index to associate with a VMDq index
649 * @vmdq: VMDq set index
650 **/
651s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
652{
653 u32 rar_high;
654
655 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
656 rar_high &= ~IXGBE_RAH_VIND_MASK;
657 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
658 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
659 return 0;
660}
661
662/**
663 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
664 * @hw: pointer to hardware struct
665 * @rar: receive address register index to associate with a VMDq index
666 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
667 **/
668static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
669{
670 u32 rar_high;
671 u32 rar_entries = hw->mac.num_rar_entries;
672
673 if (rar < rar_entries) {
674 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
675 if (rar_high & IXGBE_RAH_VIND_MASK) {
676 rar_high &= ~IXGBE_RAH_VIND_MASK;
677 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
678 }
679 } else {
680 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
681 }
682
683 return 0;
684}
685
686/**
687 * ixgbe_set_vfta_82598 - Set VLAN filter table
688 * @hw: pointer to hardware structure
689 * @vlan: VLAN id to write to VLAN filter
690 * @vind: VMDq output index that maps queue to VLAN id in VFTA
691 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
692 *
693 * Turn on/off specified VLAN in the VLAN filter table.
694 **/
695s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
696 bool vlan_on)
697{
698 u32 regindex;
699 u32 bitindex;
700 u32 bits;
701 u32 vftabyte;
702
703 if (vlan > 4095)
704 return IXGBE_ERR_PARAM;
705
706 /* Determine 32-bit word position in array */
707 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
708
709 /* Determine the location of the (VMD) queue index */
710 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
711 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
712
713 /* Set the nibble for VMD queue index */
714 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
715 bits &= (~(0x0F << bitindex));
716 bits |= (vind << bitindex);
717 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
718
719 /* Determine the location of the bit for this VLAN id */
720 bitindex = vlan & 0x1F; /* lower five bits */
721
722 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
723 if (vlan_on)
724 /* Turn on this VLAN id */
725 bits |= (1 << bitindex);
726 else
727 /* Turn off this VLAN id */
728 bits &= ~(1 << bitindex);
729 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
730
731 return 0;
732}
733
734/**
735 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
736 * @hw: pointer to hardware structure
737 *
738 * Clears the VLAN filer table, and the VMDq index associated with the filter
739 **/
740static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
741{
742 u32 offset;
743 u32 vlanbyte;
744
745 for (offset = 0; offset < hw->mac.vft_size; offset++)
746 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
747
748 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
749 for (offset = 0; offset < hw->mac.vft_size; offset++)
750 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
751 0);
752
753 return 0;
754}
755
756/**
757 * ixgbe_blink_led_start_82598 - Blink LED based on index.
758 * @hw: pointer to hardware structure
759 * @index: led number to blink
760 **/
761static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
762{
763 ixgbe_link_speed speed = 0;
764 bool link_up = 0;
765 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
766 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
767
768 /*
769 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
770 * force it if link is down.
771 */
772 hw->mac.ops.check_link(hw, &speed, &link_up, false);
773
774 if (!link_up) {
775 autoc_reg |= IXGBE_AUTOC_FLU;
776 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
777 msleep(10);
778 }
779
780 led_reg &= ~IXGBE_LED_MODE_MASK(index);
781 led_reg |= IXGBE_LED_BLINK(index);
782 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
783 IXGBE_WRITE_FLUSH(hw);
784
785 return 0;
786}
787
788/**
789 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
790 * @hw: pointer to hardware structure
791 * @index: led number to stop blinking
792 **/
793static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
794{
795 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
796 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
797
798 autoc_reg &= ~IXGBE_AUTOC_FLU;
799 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
800 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
801
802 led_reg &= ~IXGBE_LED_MODE_MASK(index);
803 led_reg &= ~IXGBE_LED_BLINK(index);
804 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
805 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
806 IXGBE_WRITE_FLUSH(hw);
807
808 return 0;
809}
810
811/**
812 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
813 * @hw: pointer to hardware structure
814 * @reg: analog register to read
815 * @val: read value
816 *
817 * Performs read operation to Atlas analog register specified.
818 **/
819s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
820{
821 u32 atlas_ctl;
822
823 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
824 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
825 IXGBE_WRITE_FLUSH(hw);
826 udelay(10);
827 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
828 *val = (u8)atlas_ctl;
829
830 return 0;
831}
832
833/**
834 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
835 * @hw: pointer to hardware structure
836 * @reg: atlas register to write
837 * @val: value to write
838 *
839 * Performs write operation to Atlas analog register specified.
840 **/
841s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
842{
843 u32 atlas_ctl;
844
845 atlas_ctl = (reg << 8) | val;
846 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
847 IXGBE_WRITE_FLUSH(hw);
848 udelay(10);
849
850 return 0;
851}
852
853/**
854 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
855 * @hw: pointer to hardware structure
856 *
857 * Determines physical layer capabilities of the current configuration.
858 **/
859s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
860{
861 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
862
863 switch (hw->device_id) {
864 case IXGBE_DEV_ID_82598EB_CX4:
865 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
866 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
867 break;
868 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
869 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
870 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
871 break;
872 case IXGBE_DEV_ID_82598EB_XF_LR:
873 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
874 break;
875
876 default:
877 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
878 break;
879 }
880
881 return physical_layer;
882}
883
513static struct ixgbe_mac_operations mac_ops_82598 = { 884static struct ixgbe_mac_operations mac_ops_82598 = {
514 .reset = &ixgbe_reset_hw_82598, 885 .init_hw = &ixgbe_init_hw_generic,
886 .reset_hw = &ixgbe_reset_hw_82598,
887 .start_hw = &ixgbe_start_hw_generic,
888 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
515 .get_media_type = &ixgbe_get_media_type_82598, 889 .get_media_type = &ixgbe_get_media_type_82598,
890 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
891 .get_mac_addr = &ixgbe_get_mac_addr_generic,
892 .stop_adapter = &ixgbe_stop_adapter_generic,
893 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
894 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
516 .setup_link = &ixgbe_setup_mac_link_82598, 895 .setup_link = &ixgbe_setup_mac_link_82598,
517 .check_link = &ixgbe_check_mac_link_82598,
518 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598, 896 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
519 .get_link_settings = &ixgbe_get_link_settings_82598, 897 .check_link = &ixgbe_check_mac_link_82598,
898 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
899 .led_on = &ixgbe_led_on_generic,
900 .led_off = &ixgbe_led_off_generic,
901 .blink_led_start = &ixgbe_blink_led_start_82598,
902 .blink_led_stop = &ixgbe_blink_led_stop_82598,
903 .set_rar = &ixgbe_set_rar_generic,
904 .clear_rar = &ixgbe_clear_rar_generic,
905 .set_vmdq = &ixgbe_set_vmdq_82598,
906 .clear_vmdq = &ixgbe_clear_vmdq_82598,
907 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
908 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
909 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
910 .enable_mc = &ixgbe_enable_mc_generic,
911 .disable_mc = &ixgbe_disable_mc_generic,
912 .clear_vfta = &ixgbe_clear_vfta_82598,
913 .set_vfta = &ixgbe_set_vfta_82598,
914 .setup_fc = &ixgbe_setup_fc_82598,
915};
916
917static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
918 .init_params = &ixgbe_init_eeprom_params_generic,
919 .read = &ixgbe_read_eeprom_generic,
920 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
921 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
922};
923
924static struct ixgbe_phy_operations phy_ops_82598 = {
925 .identify = &ixgbe_identify_phy_generic,
926 /* .identify_sfp = &ixgbe_identify_sfp_module_generic, */
927 .reset = &ixgbe_reset_phy_generic,
928 .read_reg = &ixgbe_read_phy_reg_generic,
929 .write_reg = &ixgbe_write_phy_reg_generic,
930 .setup_link = &ixgbe_setup_phy_link_generic,
931 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
520}; 932};
521 933
522struct ixgbe_info ixgbe_82598_info = { 934struct ixgbe_info ixgbe_82598_info = {
523 .mac = ixgbe_mac_82598EB, 935 .mac = ixgbe_mac_82598EB,
524 .get_invariants = &ixgbe_get_invariants_82598, 936 .get_invariants = &ixgbe_get_invariants_82598,
525 .mac_ops = &mac_ops_82598, 937 .mac_ops = &mac_ops_82598,
938 .eeprom_ops = &eeprom_ops_82598,
939 .phy_ops = &phy_ops_82598,
526}; 940};
527 941
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 00:04:45 -0500