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path: root/drivers/net/ixgb/ixgb_hw.h
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Diffstat (limited to 'drivers/net/ixgb/ixgb_hw.h')
-rw-r--r--drivers/net/ixgb/ixgb_hw.h250
1 files changed, 125 insertions, 125 deletions
diff --git a/drivers/net/ixgb/ixgb_hw.h b/drivers/net/ixgb/ixgb_hw.h
index 4f176ff2b786..39cfa47bea69 100644
--- a/drivers/net/ixgb/ixgb_hw.h
+++ b/drivers/net/ixgb/ixgb_hw.h
@@ -538,8 +538,8 @@ struct ixgb_rx_desc {
538 __le64 buff_addr; 538 __le64 buff_addr;
539 __le16 length; 539 __le16 length;
540 __le16 reserved; 540 __le16 reserved;
541 uint8_t status; 541 u8 status;
542 uint8_t errors; 542 u8 errors;
543 __le16 special; 543 __le16 special;
544}; 544};
545 545
@@ -570,8 +570,8 @@ struct ixgb_rx_desc {
570struct ixgb_tx_desc { 570struct ixgb_tx_desc {
571 __le64 buff_addr; 571 __le64 buff_addr;
572 __le32 cmd_type_len; 572 __le32 cmd_type_len;
573 uint8_t status; 573 u8 status;
574 uint8_t popts; 574 u8 popts;
575 __le16 vlan; 575 __le16 vlan;
576}; 576};
577 577
@@ -595,15 +595,15 @@ struct ixgb_tx_desc {
595#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */ 595#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */
596 596
597struct ixgb_context_desc { 597struct ixgb_context_desc {
598 uint8_t ipcss; 598 u8 ipcss;
599 uint8_t ipcso; 599 u8 ipcso;
600 __le16 ipcse; 600 __le16 ipcse;
601 uint8_t tucss; 601 u8 tucss;
602 uint8_t tucso; 602 u8 tucso;
603 __le16 tucse; 603 __le16 tucse;
604 __le32 cmd_type_len; 604 __le32 cmd_type_len;
605 uint8_t status; 605 u8 status;
606 uint8_t hdr_len; 606 u8 hdr_len;
607 __le16 mss; 607 __le16 mss;
608}; 608};
609 609
@@ -637,33 +637,33 @@ struct ixgb_context_desc {
637 637
638/* This structure takes a 64k flash and maps it for identification commands */ 638/* This structure takes a 64k flash and maps it for identification commands */
639struct ixgb_flash_buffer { 639struct ixgb_flash_buffer {
640 uint8_t manufacturer_id; 640 u8 manufacturer_id;
641 uint8_t device_id; 641 u8 device_id;
642 uint8_t filler1[0x2AA8]; 642 u8 filler1[0x2AA8];
643 uint8_t cmd2; 643 u8 cmd2;
644 uint8_t filler2[0x2AAA]; 644 u8 filler2[0x2AAA];
645 uint8_t cmd1; 645 u8 cmd1;
646 uint8_t filler3[0xAAAA]; 646 u8 filler3[0xAAAA];
647}; 647};
648 648
649/* 649/*
650 * This is a little-endian specific check. 650 * This is a little-endian specific check.
651 */ 651 */
652#define IS_MULTICAST(Address) \ 652#define IS_MULTICAST(Address) \
653 (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) 653 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
654 654
655/* 655/*
656 * Check whether an address is broadcast. 656 * Check whether an address is broadcast.
657 */ 657 */
658#define IS_BROADCAST(Address) \ 658#define IS_BROADCAST(Address) \
659 ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) 659 ((((u8 *)(Address))[0] == ((u8)0xff)) && (((u8 *)(Address))[1] == ((u8)0xff)))
660 660
661/* Flow control parameters */ 661/* Flow control parameters */
662struct ixgb_fc { 662struct ixgb_fc {
663 uint32_t high_water; /* Flow Control High-water */ 663 u32 high_water; /* Flow Control High-water */
664 uint32_t low_water; /* Flow Control Low-water */ 664 u32 low_water; /* Flow Control Low-water */
665 uint16_t pause_time; /* Flow Control Pause timer */ 665 u16 pause_time; /* Flow Control Pause timer */
666 boolean_t send_xon; /* Flow control send XON */ 666 bool send_xon; /* Flow control send XON */
667 ixgb_fc_type type; /* Type of flow control */ 667 ixgb_fc_type type; /* Type of flow control */
668}; 668};
669 669
@@ -685,139 +685,139 @@ struct ixgb_bus {
685}; 685};
686 686
687struct ixgb_hw { 687struct ixgb_hw {
688 uint8_t __iomem *hw_addr;/* Base Address of the hardware */ 688 u8 __iomem *hw_addr;/* Base Address of the hardware */
689 void *back; /* Pointer to OS-dependent struct */ 689 void *back; /* Pointer to OS-dependent struct */
690 struct ixgb_fc fc; /* Flow control parameters */ 690 struct ixgb_fc fc; /* Flow control parameters */
691 struct ixgb_bus bus; /* Bus parameters */ 691 struct ixgb_bus bus; /* Bus parameters */
692 uint32_t phy_id; /* Phy Identifier */ 692 u32 phy_id; /* Phy Identifier */
693 uint32_t phy_addr; /* XGMII address of Phy */ 693 u32 phy_addr; /* XGMII address of Phy */
694 ixgb_mac_type mac_type; /* Identifier for MAC controller */ 694 ixgb_mac_type mac_type; /* Identifier for MAC controller */
695 ixgb_phy_type phy_type; /* Transceiver/phy identifier */ 695 ixgb_phy_type phy_type; /* Transceiver/phy identifier */
696 uint32_t max_frame_size; /* Maximum frame size supported */ 696 u32 max_frame_size; /* Maximum frame size supported */
697 uint32_t mc_filter_type; /* Multicast filter hash type */ 697 u32 mc_filter_type; /* Multicast filter hash type */
698 uint32_t num_mc_addrs; /* Number of current Multicast addrs */ 698 u32 num_mc_addrs; /* Number of current Multicast addrs */
699 uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */ 699 u8 curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */
700 uint32_t num_tx_desc; /* Number of Transmit descriptors */ 700 u32 num_tx_desc; /* Number of Transmit descriptors */
701 uint32_t num_rx_desc; /* Number of Receive descriptors */ 701 u32 num_rx_desc; /* Number of Receive descriptors */
702 uint32_t rx_buffer_size; /* Size of Receive buffer */ 702 u32 rx_buffer_size; /* Size of Receive buffer */
703 boolean_t link_up; /* TRUE if link is valid */ 703 bool link_up; /* true if link is valid */
704 boolean_t adapter_stopped; /* State of adapter */ 704 bool adapter_stopped; /* State of adapter */
705 uint16_t device_id; /* device id from PCI configuration space */ 705 u16 device_id; /* device id from PCI configuration space */
706 uint16_t vendor_id; /* vendor id from PCI configuration space */ 706 u16 vendor_id; /* vendor id from PCI configuration space */
707 uint8_t revision_id; /* revision id from PCI configuration space */ 707 u8 revision_id; /* revision id from PCI configuration space */
708 uint16_t subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */ 708 u16 subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */
709 uint16_t subsystem_id; /* subsystem id from PCI configuration space */ 709 u16 subsystem_id; /* subsystem id from PCI configuration space */
710 uint32_t bar0; /* Base Address registers */ 710 u32 bar0; /* Base Address registers */
711 uint32_t bar1; 711 u32 bar1;
712 uint32_t bar2; 712 u32 bar2;
713 uint32_t bar3; 713 u32 bar3;
714 uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */ 714 u16 pci_cmd_word; /* PCI command register id from PCI configuration space */
715 __le16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ 715 __le16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */
716 unsigned long io_base; /* Our I/O mapped location */ 716 unsigned long io_base; /* Our I/O mapped location */
717 uint32_t lastLFC; 717 u32 lastLFC;
718 uint32_t lastRFC; 718 u32 lastRFC;
719}; 719};
720 720
721/* Statistics reported by the hardware */ 721/* Statistics reported by the hardware */
722struct ixgb_hw_stats { 722struct ixgb_hw_stats {
723 uint64_t tprl; 723 u64 tprl;
724 uint64_t tprh; 724 u64 tprh;
725 uint64_t gprcl; 725 u64 gprcl;
726 uint64_t gprch; 726 u64 gprch;
727 uint64_t bprcl; 727 u64 bprcl;
728 uint64_t bprch; 728 u64 bprch;
729 uint64_t mprcl; 729 u64 mprcl;
730 uint64_t mprch; 730 u64 mprch;
731 uint64_t uprcl; 731 u64 uprcl;
732 uint64_t uprch; 732 u64 uprch;
733 uint64_t vprcl; 733 u64 vprcl;
734 uint64_t vprch; 734 u64 vprch;
735 uint64_t jprcl; 735 u64 jprcl;
736 uint64_t jprch; 736 u64 jprch;
737 uint64_t gorcl; 737 u64 gorcl;
738 uint64_t gorch; 738 u64 gorch;
739 uint64_t torl; 739 u64 torl;
740 uint64_t torh; 740 u64 torh;
741 uint64_t rnbc; 741 u64 rnbc;
742 uint64_t ruc; 742 u64 ruc;
743 uint64_t roc; 743 u64 roc;
744 uint64_t rlec; 744 u64 rlec;
745 uint64_t crcerrs; 745 u64 crcerrs;
746 uint64_t icbc; 746 u64 icbc;
747 uint64_t ecbc; 747 u64 ecbc;
748 uint64_t mpc; 748 u64 mpc;
749 uint64_t tptl; 749 u64 tptl;
750 uint64_t tpth; 750 u64 tpth;
751 uint64_t gptcl; 751 u64 gptcl;
752 uint64_t gptch; 752 u64 gptch;
753 uint64_t bptcl; 753 u64 bptcl;
754 uint64_t bptch; 754 u64 bptch;
755 uint64_t mptcl; 755 u64 mptcl;
756 uint64_t mptch; 756 u64 mptch;
757 uint64_t uptcl; 757 u64 uptcl;
758 uint64_t uptch; 758 u64 uptch;
759 uint64_t vptcl; 759 u64 vptcl;
760 uint64_t vptch; 760 u64 vptch;
761 uint64_t jptcl; 761 u64 jptcl;
762 uint64_t jptch; 762 u64 jptch;
763 uint64_t gotcl; 763 u64 gotcl;
764 uint64_t gotch; 764 u64 gotch;
765 uint64_t totl; 765 u64 totl;
766 uint64_t toth; 766 u64 toth;
767 uint64_t dc; 767 u64 dc;
768 uint64_t plt64c; 768 u64 plt64c;
769 uint64_t tsctc; 769 u64 tsctc;
770 uint64_t tsctfc; 770 u64 tsctfc;
771 uint64_t ibic; 771 u64 ibic;
772 uint64_t rfc; 772 u64 rfc;
773 uint64_t lfc; 773 u64 lfc;
774 uint64_t pfrc; 774 u64 pfrc;
775 uint64_t pftc; 775 u64 pftc;
776 uint64_t mcfrc; 776 u64 mcfrc;
777 uint64_t mcftc; 777 u64 mcftc;
778 uint64_t xonrxc; 778 u64 xonrxc;
779 uint64_t xontxc; 779 u64 xontxc;
780 uint64_t xoffrxc; 780 u64 xoffrxc;
781 uint64_t xofftxc; 781 u64 xofftxc;
782 uint64_t rjc; 782 u64 rjc;
783}; 783};
784 784
785/* Function Prototypes */ 785/* Function Prototypes */
786extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw); 786extern bool ixgb_adapter_stop(struct ixgb_hw *hw);
787extern boolean_t ixgb_init_hw(struct ixgb_hw *hw); 787extern bool ixgb_init_hw(struct ixgb_hw *hw);
788extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw); 788extern bool ixgb_adapter_start(struct ixgb_hw *hw);
789extern void ixgb_check_for_link(struct ixgb_hw *hw); 789extern void ixgb_check_for_link(struct ixgb_hw *hw);
790extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw); 790extern bool ixgb_check_for_bad_link(struct ixgb_hw *hw);
791 791
792extern void ixgb_rar_set(struct ixgb_hw *hw, 792extern void ixgb_rar_set(struct ixgb_hw *hw,
793 uint8_t *addr, 793 u8 *addr,
794 uint32_t index); 794 u32 index);
795 795
796 796
797/* Filters (multicast, vlan, receive) */ 797/* Filters (multicast, vlan, receive) */
798extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, 798extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw,
799 uint8_t *mc_addr_list, 799 u8 *mc_addr_list,
800 uint32_t mc_addr_count, 800 u32 mc_addr_count,
801 uint32_t pad); 801 u32 pad);
802 802
803/* Vfta functions */ 803/* Vfta functions */
804extern void ixgb_write_vfta(struct ixgb_hw *hw, 804extern void ixgb_write_vfta(struct ixgb_hw *hw,
805 uint32_t offset, 805 u32 offset,
806 uint32_t value); 806 u32 value);
807 807
808/* Access functions to eeprom data */ 808/* Access functions to eeprom data */
809void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr); 809void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, u8 *mac_addr);
810uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw); 810u32 ixgb_get_ee_pba_number(struct ixgb_hw *hw);
811uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw); 811u16 ixgb_get_ee_device_id(struct ixgb_hw *hw);
812boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw); 812bool ixgb_get_eeprom_data(struct ixgb_hw *hw);
813__le16 ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index); 813__le16 ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index);
814 814
815/* Everything else */ 815/* Everything else */
816void ixgb_led_on(struct ixgb_hw *hw); 816void ixgb_led_on(struct ixgb_hw *hw);
817void ixgb_led_off(struct ixgb_hw *hw); 817void ixgb_led_off(struct ixgb_hw *hw);
818void ixgb_write_pci_cfg(struct ixgb_hw *hw, 818void ixgb_write_pci_cfg(struct ixgb_hw *hw,
819 uint32_t reg, 819 u32 reg,
820 uint16_t * value); 820 u16 * value);
821 821
822 822
823#endif /* _IXGB_HW_H_ */ 823#endif /* _IXGB_HW_H_ */