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path: root/drivers/net/ixgb/ixgb_hw.c
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Diffstat (limited to 'drivers/net/ixgb/ixgb_hw.c')
-rw-r--r--drivers/net/ixgb/ixgb_hw.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
index 2b1515574faf..acc6df7a6b38 100644
--- a/drivers/net/ixgb/ixgb_hw.c
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -83,7 +83,7 @@ static uint32_t ixgb_mac_reset(struct ixgb_hw *hw)
83#endif 83#endif
84 84
85 /* Delay a few ms just to allow the reset to complete */ 85 /* Delay a few ms just to allow the reset to complete */
86 msec_delay(IXGB_DELAY_AFTER_RESET); 86 msleep(IXGB_DELAY_AFTER_RESET);
87 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 87 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
88#ifdef DBG 88#ifdef DBG
89 /* Make sure the self-clearing global reset bit did self clear */ 89 /* Make sure the self-clearing global reset bit did self clear */
@@ -133,7 +133,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
133 */ 133 */
134 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 134 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
135 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 135 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
136 msec_delay(IXGB_DELAY_BEFORE_RESET); 136 msleep(IXGB_DELAY_BEFORE_RESET);
137 137
138 /* Issue a global reset to the MAC. This will reset the chip's 138 /* Issue a global reset to the MAC. This will reset the chip's
139 * transmit, receive, DMA, and link units. It will not effect 139 * transmit, receive, DMA, and link units. It will not effect
@@ -300,7 +300,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
300#endif 300#endif
301 301
302 /* Delay a few ms just to allow the reset to complete */ 302 /* Delay a few ms just to allow the reset to complete */
303 msec_delay(IXGB_DELAY_AFTER_EE_RESET); 303 msleep(IXGB_DELAY_AFTER_EE_RESET);
304 304
305 if (ixgb_get_eeprom_data(hw) == FALSE) { 305 if (ixgb_get_eeprom_data(hw) == FALSE) {
306 return(FALSE); 306 return(FALSE);