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-rw-r--r--drivers/net/igb/e1000_82575.c193
-rw-r--r--drivers/net/igb/e1000_82575.h6
-rw-r--r--drivers/net/igb/e1000_defines.h8
-rw-r--r--drivers/net/igb/e1000_hw.h18
-rw-r--r--drivers/net/igb/e1000_mac.c175
-rw-r--r--drivers/net/igb/e1000_mac.h3
-rw-r--r--drivers/net/igb/e1000_phy.c4
-rw-r--r--drivers/net/igb/e1000_regs.h1
-rw-r--r--drivers/net/igb/igb_ethtool.c65
-rw-r--r--drivers/net/igb/igb_main.c121
10 files changed, 307 insertions, 287 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index ac28dd5a4fd1..6158c0f3b205 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -53,7 +53,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
53static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 53static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 54static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 55static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56static s32 igb_configure_pcs_link_82575(struct e1000_hw *); 56static void igb_configure_pcs_link_82575(struct e1000_hw *);
57static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 57static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
58 u16 *); 58 u16 *);
59static s32 igb_get_phy_id_82575(struct e1000_hw *); 59static s32 igb_get_phy_id_82575(struct e1000_hw *);
@@ -61,6 +61,7 @@ static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
61static bool igb_sgmii_active_82575(struct e1000_hw *); 61static bool igb_sgmii_active_82575(struct e1000_hw *);
62static s32 igb_reset_init_script_82575(struct e1000_hw *); 62static s32 igb_reset_init_script_82575(struct e1000_hw *);
63static s32 igb_read_mac_addr_82575(struct e1000_hw *); 63static s32 igb_read_mac_addr_82575(struct e1000_hw *);
64static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
64 65
65static s32 igb_get_invariants_82575(struct e1000_hw *hw) 66static s32 igb_get_invariants_82575(struct e1000_hw *hw)
66{ 67{
@@ -84,6 +85,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
84 case E1000_DEV_ID_82576_FIBER: 85 case E1000_DEV_ID_82576_FIBER:
85 case E1000_DEV_ID_82576_SERDES: 86 case E1000_DEV_ID_82576_SERDES:
86 case E1000_DEV_ID_82576_QUAD_COPPER: 87 case E1000_DEV_ID_82576_QUAD_COPPER:
88 case E1000_DEV_ID_82576_SERDES_QUAD:
87 mac->type = e1000_82576; 89 mac->type = e1000_82576;
88 break; 90 break;
89 default: 91 default:
@@ -170,6 +172,10 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
170 size = 14; 172 size = 14;
171 nvm->word_size = 1 << size; 173 nvm->word_size = 1 << size;
172 174
175 /* if 82576 then initialize mailbox parameters */
176 if (mac->type == e1000_82576)
177 igb_init_mbx_params_pf(hw);
178
173 /* setup PHY parameters */ 179 /* setup PHY parameters */
174 if (phy->media_type != e1000_media_type_copper) { 180 if (phy->media_type != e1000_media_type_copper) {
175 phy->type = e1000_phy_none; 181 phy->type = e1000_phy_none;
@@ -219,10 +225,6 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
219 return -E1000_ERR_PHY; 225 return -E1000_ERR_PHY;
220 } 226 }
221 227
222 /* if 82576 then initialize mailbox parameters */
223 if (mac->type == e1000_82576)
224 igb_init_mbx_params_pf(hw);
225
226 return 0; 228 return 0;
227} 229}
228 230
@@ -764,98 +766,6 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
764} 766}
765 767
766/** 768/**
767 * igb_init_rx_addrs_82575 - Initialize receive address's
768 * @hw: pointer to the HW structure
769 * @rar_count: receive address registers
770 *
771 * Setups the receive address registers by setting the base receive address
772 * register to the devices MAC address and clearing all the other receive
773 * address registers to 0.
774 **/
775static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
776{
777 u32 i;
778 u8 addr[6] = {0,0,0,0,0,0};
779 /*
780 * This function is essentially the same as that of
781 * e1000_init_rx_addrs_generic. However it also takes care
782 * of the special case where the register offset of the
783 * second set of RARs begins elsewhere. This is implicitly taken care by
784 * function e1000_rar_set_generic.
785 */
786
787 hw_dbg("e1000_init_rx_addrs_82575");
788
789 /* Setup the receive address */
790 hw_dbg("Programming MAC Address into RAR[0]\n");
791 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
792
793 /* Zero out the other (rar_entry_count - 1) receive addresses */
794 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
795 for (i = 1; i < rar_count; i++)
796 hw->mac.ops.rar_set(hw, addr, i);
797}
798
799/**
800 * igb_update_mc_addr_list - Update Multicast addresses
801 * @hw: pointer to the HW structure
802 * @mc_addr_list: array of multicast addresses to program
803 * @mc_addr_count: number of multicast addresses to program
804 * @rar_used_count: the first RAR register free to program
805 * @rar_count: total number of supported Receive Address Registers
806 *
807 * Updates the Receive Address Registers and Multicast Table Array.
808 * The caller must have a packed mc_addr_list of multicast addresses.
809 * The parameter rar_count will usually be hw->mac.rar_entry_count
810 * unless there are workarounds that change this.
811 **/
812void igb_update_mc_addr_list(struct e1000_hw *hw,
813 u8 *mc_addr_list, u32 mc_addr_count,
814 u32 rar_used_count, u32 rar_count)
815{
816 u32 hash_value;
817 u32 i;
818 u8 addr[6] = {0,0,0,0,0,0};
819 /*
820 * This function is essentially the same as that of
821 * igb_update_mc_addr_list_generic. However it also takes care
822 * of the special case where the register offset of the
823 * second set of RARs begins elsewhere. This is implicitly taken care by
824 * function e1000_rar_set_generic.
825 */
826
827 /*
828 * Load the first set of multicast addresses into the exact
829 * filters (RAR). If there are not enough to fill the RAR
830 * array, clear the filters.
831 */
832 for (i = rar_used_count; i < rar_count; i++) {
833 if (mc_addr_count) {
834 igb_rar_set(hw, mc_addr_list, i);
835 mc_addr_count--;
836 mc_addr_list += ETH_ALEN;
837 } else {
838 igb_rar_set(hw, addr, i);
839 }
840 }
841
842 /* Clear the old settings from the MTA */
843 hw_dbg("Clearing MTA\n");
844 for (i = 0; i < hw->mac.mta_reg_count; i++) {
845 array_wr32(E1000_MTA, i, 0);
846 wrfl();
847 }
848
849 /* Load any remaining multicast addresses into the hash table. */
850 for (; mc_addr_count > 0; mc_addr_count--) {
851 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
852 hw_dbg("Hash value = 0x%03X\n", hash_value);
853 igb_mta_set(hw, hash_value);
854 mc_addr_list += ETH_ALEN;
855 }
856}
857
858/**
859 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down 769 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
860 * @hw: pointer to the HW structure 770 * @hw: pointer to the HW structure
861 * 771 *
@@ -866,9 +776,7 @@ void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
866{ 776{
867 u32 reg; 777 u32 reg;
868 778
869 if (hw->mac.type != e1000_82576 || 779 if (hw->phy.media_type != e1000_media_type_internal_serdes)
870 (hw->phy.media_type != e1000_media_type_fiber &&
871 hw->phy.media_type != e1000_media_type_internal_serdes))
872 return; 780 return;
873 781
874 /* if the management interface is not enabled, then power down */ 782 /* if the management interface is not enabled, then power down */
@@ -911,6 +819,12 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
911 if (ret_val) 819 if (ret_val)
912 hw_dbg("PCI-E Master disable polling has failed.\n"); 820 hw_dbg("PCI-E Master disable polling has failed.\n");
913 821
822 /* set the completion timeout for interface */
823 ret_val = igb_set_pcie_completion_timeout(hw);
824 if (ret_val) {
825 hw_dbg("PCI-E Set completion timeout has failed.\n");
826 }
827
914 hw_dbg("Masking off all interrupts\n"); 828 hw_dbg("Masking off all interrupts\n");
915 wr32(E1000_IMC, 0xffffffff); 829 wr32(E1000_IMC, 0xffffffff);
916 830
@@ -943,7 +857,8 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
943 wr32(E1000_IMC, 0xffffffff); 857 wr32(E1000_IMC, 0xffffffff);
944 icr = rd32(E1000_ICR); 858 icr = rd32(E1000_ICR);
945 859
946 igb_check_alt_mac_addr(hw); 860 /* Install any alternate MAC address into RAR0 */
861 ret_val = igb_check_alt_mac_addr(hw);
947 862
948 return ret_val; 863 return ret_val;
949} 864}
@@ -972,7 +887,8 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
972 igb_clear_vfta(hw); 887 igb_clear_vfta(hw);
973 888
974 /* Setup the receive address */ 889 /* Setup the receive address */
975 igb_init_rx_addrs_82575(hw, rar_count); 890 igb_init_rx_addrs(hw, rar_count);
891
976 /* Zero out the Multicast HASH table */ 892 /* Zero out the Multicast HASH table */
977 hw_dbg("Zeroing the MTA\n"); 893 hw_dbg("Zeroing the MTA\n");
978 for (i = 0; i < mac->mta_reg_count; i++) 894 for (i = 0; i < mac->mta_reg_count; i++)
@@ -1002,7 +918,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
1002 **/ 918 **/
1003static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 919static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1004{ 920{
1005 u32 ctrl, led_ctrl; 921 u32 ctrl;
1006 s32 ret_val; 922 s32 ret_val;
1007 bool link; 923 bool link;
1008 924
@@ -1017,11 +933,6 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1017 break; 933 break;
1018 case e1000_phy_igp_3: 934 case e1000_phy_igp_3:
1019 ret_val = igb_copper_link_setup_igp(hw); 935 ret_val = igb_copper_link_setup_igp(hw);
1020 /* Setup activity LED */
1021 led_ctrl = rd32(E1000_LEDCTL);
1022 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1023 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1024 wr32(E1000_LEDCTL, led_ctrl);
1025 break; 936 break;
1026 default: 937 default:
1027 ret_val = -E1000_ERR_PHY; 938 ret_val = -E1000_ERR_PHY;
@@ -1052,9 +963,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1052 } 963 }
1053 } 964 }
1054 965
1055 ret_val = igb_configure_pcs_link_82575(hw); 966 igb_configure_pcs_link_82575(hw);
1056 if (ret_val)
1057 goto out;
1058 967
1059 /* 968 /*
1060 * Check link status. Wait up to 100 microseconds for link to become 969 * Check link status. Wait up to 100 microseconds for link to become
@@ -1163,14 +1072,14 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1163 * independent interface (sgmii) is being used. Configures the link 1072 * independent interface (sgmii) is being used. Configures the link
1164 * for auto-negotiation or forces speed/duplex. 1073 * for auto-negotiation or forces speed/duplex.
1165 **/ 1074 **/
1166static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw) 1075static void igb_configure_pcs_link_82575(struct e1000_hw *hw)
1167{ 1076{
1168 struct e1000_mac_info *mac = &hw->mac; 1077 struct e1000_mac_info *mac = &hw->mac;
1169 u32 reg = 0; 1078 u32 reg = 0;
1170 1079
1171 if (hw->phy.media_type != e1000_media_type_copper || 1080 if (hw->phy.media_type != e1000_media_type_copper ||
1172 !(igb_sgmii_active_82575(hw))) 1081 !(igb_sgmii_active_82575(hw)))
1173 goto out; 1082 return;
1174 1083
1175 /* For SGMII, we need to issue a PCS autoneg restart */ 1084 /* For SGMII, we need to issue a PCS autoneg restart */
1176 reg = rd32(E1000_PCS_LCTL); 1085 reg = rd32(E1000_PCS_LCTL);
@@ -1213,9 +1122,6 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1213 reg); 1122 reg);
1214 } 1123 }
1215 wr32(E1000_PCS_LCTL, reg); 1124 wr32(E1000_PCS_LCTL, reg);
1216
1217out:
1218 return 0;
1219} 1125}
1220 1126
1221/** 1127/**
@@ -1229,10 +1135,6 @@ out:
1229static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1135static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1230{ 1136{
1231 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1137 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1232
1233 if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576)
1234 return false;
1235
1236 return dev_spec->sgmii_active; 1138 return dev_spec->sgmii_active;
1237} 1139}
1238 1140
@@ -1424,6 +1326,57 @@ void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1424} 1326}
1425 1327
1426/** 1328/**
1329 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1330 * @hw: pointer to the HW structure
1331 *
1332 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1333 * however the hardware default for these parts is 500us to 1ms which is less
1334 * than the 10ms recommended by the pci-e spec. To address this we need to
1335 * increase the value to either 10ms to 200ms for capability version 1 config,
1336 * or 16ms to 55ms for version 2.
1337 **/
1338static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1339{
1340 u32 gcr = rd32(E1000_GCR);
1341 s32 ret_val = 0;
1342 u16 pcie_devctl2;
1343
1344 /* only take action if timeout value is defaulted to 0 */
1345 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1346 goto out;
1347
1348 /*
1349 * if capababilities version is type 1 we can write the
1350 * timeout of 10ms to 200ms through the GCR register
1351 */
1352 if (!(gcr & E1000_GCR_CAP_VER2)) {
1353 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1354 goto out;
1355 }
1356
1357 /*
1358 * for version 2 capabilities we need to write the config space
1359 * directly in order to set the completion timeout value for
1360 * 16ms to 55ms
1361 */
1362 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1363 &pcie_devctl2);
1364 if (ret_val)
1365 goto out;
1366
1367 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1368
1369 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1370 &pcie_devctl2);
1371out:
1372 /* disable completion timeout resend */
1373 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1374
1375 wr32(E1000_GCR, gcr);
1376 return ret_val;
1377}
1378
1379/**
1427 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 1380 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1428 * @hw: pointer to the hardware struct 1381 * @hw: pointer to the hardware struct
1429 * @enable: state to enter, either enabled or disabled 1382 * @enable: state to enter, either enabled or disabled
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index 0f16abab2565..8a1e6597061f 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -28,10 +28,14 @@
28#ifndef _E1000_82575_H_ 28#ifndef _E1000_82575_H_
29#define _E1000_82575_H_ 29#define _E1000_82575_H_
30 30
31void igb_update_mc_addr_list(struct e1000_hw*, u8*, u32, u32, u32);
32extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 31extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
33extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); 32extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
34 33
34#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
35 (ID_LED_DEF1_DEF2 << 8) | \
36 (ID_LED_DEF1_DEF2 << 4) | \
37 (ID_LED_OFF1_ON2))
38
35#define E1000_RAR_ENTRIES_82575 16 39#define E1000_RAR_ENTRIES_82575 16
36#define E1000_RAR_ENTRIES_82576 24 40#define E1000_RAR_ENTRIES_82576 24
37 41
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 3bda3db73f1f..c85829355d50 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -435,6 +435,12 @@
435/* Flow Control */ 435/* Flow Control */
436#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 436#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
437 437
438/* PCI Express Control */
439#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
440#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
441#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
442#define E1000_GCR_CAP_VER2 0x00040000
443
438/* PHY Control Register */ 444/* PHY Control Register */
439#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 445#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
440#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 446#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
@@ -569,9 +575,11 @@
569 575
570/* PCI/PCI-X/PCI-EX Config space */ 576/* PCI/PCI-X/PCI-EX Config space */
571#define PCIE_LINK_STATUS 0x12 577#define PCIE_LINK_STATUS 0x12
578#define PCIE_DEVICE_CONTROL2 0x28
572 579
573#define PCIE_LINK_WIDTH_MASK 0x3F0 580#define PCIE_LINK_WIDTH_MASK 0x3F0
574#define PCIE_LINK_WIDTH_SHIFT 4 581#define PCIE_LINK_WIDTH_SHIFT 4
582#define PCIE_DEVICE_CONTROL2_16ms 0x0005
575 583
576#define PHY_REVISION_MASK 0xFFFFFFF0 584#define PHY_REVISION_MASK 0xFFFFFFF0
577#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 585#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h
index 68aac20c31ca..119869b1124d 100644
--- a/drivers/net/igb/e1000_hw.h
+++ b/drivers/net/igb/e1000_hw.h
@@ -42,6 +42,7 @@ struct e1000_hw;
42#define E1000_DEV_ID_82576_SERDES 0x10E7 42#define E1000_DEV_ID_82576_SERDES 0x10E7
43#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 43#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
44#define E1000_DEV_ID_82576_NS 0x150A 44#define E1000_DEV_ID_82576_NS 0x150A
45#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
45#define E1000_DEV_ID_82575EB_COPPER 0x10A7 46#define E1000_DEV_ID_82575EB_COPPER 0x10A7
46#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 47#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
47#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 48#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
@@ -61,8 +62,7 @@ enum e1000_mac_type {
61enum e1000_media_type { 62enum e1000_media_type {
62 e1000_media_type_unknown = 0, 63 e1000_media_type_unknown = 0,
63 e1000_media_type_copper = 1, 64 e1000_media_type_copper = 1,
64 e1000_media_type_fiber = 2, 65 e1000_media_type_internal_serdes = 2,
65 e1000_media_type_internal_serdes = 3,
66 e1000_num_media_types 66 e1000_num_media_types
67}; 67};
68 68
@@ -137,7 +137,7 @@ enum e1000_rev_polarity {
137 e1000_rev_polarity_undefined = 0xFF 137 e1000_rev_polarity_undefined = 0xFF
138}; 138};
139 139
140enum e1000_fc_type { 140enum e1000_fc_mode {
141 e1000_fc_none = 0, 141 e1000_fc_none = 0,
142 e1000_fc_rx_pause, 142 e1000_fc_rx_pause,
143 e1000_fc_tx_pause, 143 e1000_fc_tx_pause,
@@ -339,6 +339,10 @@ struct e1000_mac_info {
339 u16 ifs_ratio; 339 u16 ifs_ratio;
340 u16 ifs_step_size; 340 u16 ifs_step_size;
341 u16 mta_reg_count; 341 u16 mta_reg_count;
342
343 /* Maximum size of the MTA register table in all supported adapters */
344 #define MAX_MTA_REG 128
345 u32 mta_shadow[MAX_MTA_REG];
342 u16 rar_entry_count; 346 u16 rar_entry_count;
343 347
344 u8 forced_speed_duplex; 348 u8 forced_speed_duplex;
@@ -425,8 +429,8 @@ struct e1000_fc_info {
425 u16 pause_time; /* Flow control pause timer */ 429 u16 pause_time; /* Flow control pause timer */
426 bool send_xon; /* Flow control send XON */ 430 bool send_xon; /* Flow control send XON */
427 bool strict_ieee; /* Strict IEEE mode */ 431 bool strict_ieee; /* Strict IEEE mode */
428 enum e1000_fc_type type; /* Type of flow control */ 432 enum e1000_fc_mode current_mode; /* Type of flow control */
429 enum e1000_fc_type original_type; 433 enum e1000_fc_mode requested_mode;
430}; 434};
431 435
432struct e1000_mbx_operations { 436struct e1000_mbx_operations {
@@ -495,5 +499,7 @@ extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
495#else 499#else
496#define hw_dbg(format, arg...) 500#define hw_dbg(format, arg...)
497#endif 501#endif
498
499#endif 502#endif
503/* These functions must be implemented by drivers */
504s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
505s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index 472f3f124840..a0231cd079f1 100644
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -37,20 +37,6 @@
37static s32 igb_set_default_fc(struct e1000_hw *hw); 37static s32 igb_set_default_fc(struct e1000_hw *hw);
38static s32 igb_set_fc_watermarks(struct e1000_hw *hw); 38static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
39 39
40static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
41{
42 struct igb_adapter *adapter = hw->back;
43 u16 cap_offset;
44
45 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
46 if (!cap_offset)
47 return -E1000_ERR_CONFIG;
48
49 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
50
51 return 0;
52}
53
54/** 40/**
55 * igb_get_bus_info_pcie - Get PCIe bus information 41 * igb_get_bus_info_pcie - Get PCIe bus information
56 * @hw: pointer to the HW structure 42 * @hw: pointer to the HW structure
@@ -118,6 +104,31 @@ static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
118} 104}
119 105
120/** 106/**
107 * igb_init_rx_addrs - Initialize receive address's
108 * @hw: pointer to the HW structure
109 * @rar_count: receive address registers
110 *
111 * Setups the receive address registers by setting the base receive address
112 * register to the devices MAC address and clearing all the other receive
113 * address registers to 0.
114 **/
115void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
116{
117 u32 i;
118 u8 mac_addr[ETH_ALEN] = {0};
119
120 /* Setup the receive address */
121 hw_dbg("Programming MAC Address into RAR[0]\n");
122
123 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
124
125 /* Zero out the other (rar_entry_count - 1) receive addresses */
126 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
127 for (i = 1; i < rar_count; i++)
128 hw->mac.ops.rar_set(hw, mac_addr, i);
129}
130
131/**
121 * igb_vfta_set - enable or disable vlan in VLAN filter table 132 * igb_vfta_set - enable or disable vlan in VLAN filter table
122 * @hw: pointer to the HW structure 133 * @hw: pointer to the HW structure
123 * @vid: VLAN id to add or remove 134 * @vid: VLAN id to add or remove
@@ -275,6 +286,41 @@ void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
275} 286}
276 287
277/** 288/**
289 * igb_update_mc_addr_list - Update Multicast addresses
290 * @hw: pointer to the HW structure
291 * @mc_addr_list: array of multicast addresses to program
292 * @mc_addr_count: number of multicast addresses to program
293 *
294 * Updates entire Multicast Table Array.
295 * The caller must have a packed mc_addr_list of multicast addresses.
296 **/
297void igb_update_mc_addr_list(struct e1000_hw *hw,
298 u8 *mc_addr_list, u32 mc_addr_count)
299{
300 u32 hash_value, hash_bit, hash_reg;
301 int i;
302
303 /* clear mta_shadow */
304 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
305
306 /* update mta_shadow from mc_addr_list */
307 for (i = 0; (u32) i < mc_addr_count; i++) {
308 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
309
310 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
311 hash_bit = hash_value & 0x1F;
312
313 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
314 mc_addr_list += (ETH_ALEN);
315 }
316
317 /* replace the entire MTA table */
318 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
319 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
320 wrfl();
321}
322
323/**
278 * igb_hash_mc_addr - Generate a multicast hash value 324 * igb_hash_mc_addr - Generate a multicast hash value
279 * @hw: pointer to the HW structure 325 * @hw: pointer to the HW structure
280 * @mc_addr: pointer to a multicast address 326 * @mc_addr: pointer to a multicast address
@@ -490,18 +536,24 @@ s32 igb_setup_link(struct e1000_hw *hw)
490 if (igb_check_reset_block(hw)) 536 if (igb_check_reset_block(hw))
491 goto out; 537 goto out;
492 538
493 ret_val = igb_set_default_fc(hw); 539 /*
494 if (ret_val) 540 * If requested flow control is set to default, set flow control
495 goto out; 541 * based on the EEPROM flow control settings.
542 */
543 if (hw->fc.requested_mode == e1000_fc_default) {
544 ret_val = igb_set_default_fc(hw);
545 if (ret_val)
546 goto out;
547 }
496 548
497 /* 549 /*
498 * We want to save off the original Flow Control configuration just 550 * We want to save off the original Flow Control configuration just
499 * in case we get disconnected and then reconnected into a different 551 * in case we get disconnected and then reconnected into a different
500 * hub or switch with different Flow Control capabilities. 552 * hub or switch with different Flow Control capabilities.
501 */ 553 */
502 hw->fc.original_type = hw->fc.type; 554 hw->fc.current_mode = hw->fc.requested_mode;
503 555
504 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type); 556 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
505 557
506 /* Call the necessary media_type subroutine to configure the link. */ 558 /* Call the necessary media_type subroutine to configure the link. */
507 ret_val = hw->mac.ops.setup_physical_interface(hw); 559 ret_val = hw->mac.ops.setup_physical_interface(hw);
@@ -568,7 +620,7 @@ static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
568 * ability to transmit pause frames is not enabled, then these 620 * ability to transmit pause frames is not enabled, then these
569 * registers will be set to 0. 621 * registers will be set to 0.
570 */ 622 */
571 if (hw->fc.type & e1000_fc_tx_pause) { 623 if (hw->fc.current_mode & e1000_fc_tx_pause) {
572 /* 624 /*
573 * We need to set up the Receive Threshold high and low water 625 * We need to set up the Receive Threshold high and low water
574 * marks as well as (optionally) enabling the transmission of 626 * marks as well as (optionally) enabling the transmission of
@@ -615,12 +667,12 @@ static s32 igb_set_default_fc(struct e1000_hw *hw)
615 } 667 }
616 668
617 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 669 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
618 hw->fc.type = e1000_fc_none; 670 hw->fc.requested_mode = e1000_fc_none;
619 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 671 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
620 NVM_WORD0F_ASM_DIR) 672 NVM_WORD0F_ASM_DIR)
621 hw->fc.type = e1000_fc_tx_pause; 673 hw->fc.requested_mode = e1000_fc_tx_pause;
622 else 674 else
623 hw->fc.type = e1000_fc_full; 675 hw->fc.requested_mode = e1000_fc_full;
624 676
625out: 677out:
626 return ret_val; 678 return ret_val;
@@ -650,7 +702,7 @@ s32 igb_force_mac_fc(struct e1000_hw *hw)
650 * receive flow control. 702 * receive flow control.
651 * 703 *
652 * The "Case" statement below enables/disable flow control 704 * The "Case" statement below enables/disable flow control
653 * according to the "hw->fc.type" parameter. 705 * according to the "hw->fc.current_mode" parameter.
654 * 706 *
655 * The possible values of the "fc" parameter are: 707 * The possible values of the "fc" parameter are:
656 * 0: Flow control is completely disabled 708 * 0: Flow control is completely disabled
@@ -661,9 +713,9 @@ s32 igb_force_mac_fc(struct e1000_hw *hw)
661 * 3: Both Rx and TX flow control (symmetric) is enabled. 713 * 3: Both Rx and TX flow control (symmetric) is enabled.
662 * other: No other values should be possible at this point. 714 * other: No other values should be possible at this point.
663 */ 715 */
664 hw_dbg("hw->fc.type = %u\n", hw->fc.type); 716 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
665 717
666 switch (hw->fc.type) { 718 switch (hw->fc.current_mode) {
667 case e1000_fc_none: 719 case e1000_fc_none:
668 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 720 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
669 break; 721 break;
@@ -713,8 +765,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
713 * configuration of the MAC to match the "fc" parameter. 765 * configuration of the MAC to match the "fc" parameter.
714 */ 766 */
715 if (mac->autoneg_failed) { 767 if (mac->autoneg_failed) {
716 if (hw->phy.media_type == e1000_media_type_fiber || 768 if (hw->phy.media_type == e1000_media_type_internal_serdes)
717 hw->phy.media_type == e1000_media_type_internal_serdes)
718 ret_val = igb_force_mac_fc(hw); 769 ret_val = igb_force_mac_fc(hw);
719 } else { 770 } else {
720 if (hw->phy.media_type == e1000_media_type_copper) 771 if (hw->phy.media_type == e1000_media_type_copper)
@@ -812,11 +863,11 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
812 * ONLY. Hence, we must now check to see if we need to 863 * ONLY. Hence, we must now check to see if we need to
813 * turn OFF the TRANSMISSION of PAUSE frames. 864 * turn OFF the TRANSMISSION of PAUSE frames.
814 */ 865 */
815 if (hw->fc.original_type == e1000_fc_full) { 866 if (hw->fc.requested_mode == e1000_fc_full) {
816 hw->fc.type = e1000_fc_full; 867 hw->fc.current_mode = e1000_fc_full;
817 hw_dbg("Flow Control = FULL.\r\n"); 868 hw_dbg("Flow Control = FULL.\r\n");
818 } else { 869 } else {
819 hw->fc.type = e1000_fc_rx_pause; 870 hw->fc.current_mode = e1000_fc_rx_pause;
820 hw_dbg("Flow Control = " 871 hw_dbg("Flow Control = "
821 "RX PAUSE frames only.\r\n"); 872 "RX PAUSE frames only.\r\n");
822 } 873 }
@@ -833,7 +884,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
833 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 884 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
834 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 885 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
835 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 886 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
836 hw->fc.type = e1000_fc_tx_pause; 887 hw->fc.current_mode = e1000_fc_tx_pause;
837 hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); 888 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
838 } 889 }
839 /* 890 /*
@@ -848,7 +899,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
848 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 899 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
849 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 900 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
850 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 901 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
851 hw->fc.type = e1000_fc_rx_pause; 902 hw->fc.current_mode = e1000_fc_rx_pause;
852 hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); 903 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
853 } 904 }
854 /* 905 /*
@@ -872,13 +923,13 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
872 * be asked to delay transmission of packets than asking 923 * be asked to delay transmission of packets than asking
873 * our link partner to pause transmission of frames. 924 * our link partner to pause transmission of frames.
874 */ 925 */
875 else if ((hw->fc.original_type == e1000_fc_none || 926 else if ((hw->fc.requested_mode == e1000_fc_none ||
876 hw->fc.original_type == e1000_fc_tx_pause) || 927 hw->fc.requested_mode == e1000_fc_tx_pause) ||
877 hw->fc.strict_ieee) { 928 hw->fc.strict_ieee) {
878 hw->fc.type = e1000_fc_none; 929 hw->fc.current_mode = e1000_fc_none;
879 hw_dbg("Flow Control = NONE.\r\n"); 930 hw_dbg("Flow Control = NONE.\r\n");
880 } else { 931 } else {
881 hw->fc.type = e1000_fc_rx_pause; 932 hw->fc.current_mode = e1000_fc_rx_pause;
882 hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); 933 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
883 } 934 }
884 935
@@ -894,7 +945,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
894 } 945 }
895 946
896 if (duplex == HALF_DUPLEX) 947 if (duplex == HALF_DUPLEX)
897 hw->fc.type = e1000_fc_none; 948 hw->fc.current_mode = e1000_fc_none;
898 949
899 /* 950 /*
900 * Now we call a subroutine to actually force the MAC 951 * Now we call a subroutine to actually force the MAC
@@ -1065,9 +1116,17 @@ static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1065 goto out; 1116 goto out;
1066 } 1117 }
1067 1118
1068 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1119 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1069 *data = ID_LED_DEFAULT; 1120 switch(hw->phy.media_type) {
1070 1121 case e1000_media_type_internal_serdes:
1122 *data = ID_LED_DEFAULT_82575_SERDES;
1123 break;
1124 case e1000_media_type_copper:
1125 default:
1126 *data = ID_LED_DEFAULT;
1127 break;
1128 }
1129 }
1071out: 1130out:
1072 return ret_val; 1131 return ret_val;
1073} 1132}
@@ -1161,22 +1220,16 @@ s32 igb_blink_led(struct e1000_hw *hw)
1161 u32 ledctl_blink = 0; 1220 u32 ledctl_blink = 0;
1162 u32 i; 1221 u32 i;
1163 1222
1164 if (hw->phy.media_type == e1000_media_type_fiber) { 1223 /*
1165 /* always blink LED0 for PCI-E fiber */ 1224 * set the blink bit for each LED that's "on" (0x0E)
1166 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1225 * in ledctl_mode2
1167 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1226 */
1168 } else { 1227 ledctl_blink = hw->mac.ledctl_mode2;
1169 /* 1228 for (i = 0; i < 4; i++)
1170 * set the blink bit for each LED that's "on" (0x0E) 1229 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1171 * in ledctl_mode2 1230 E1000_LEDCTL_MODE_LED_ON)
1172 */ 1231 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1173 ledctl_blink = hw->mac.ledctl_mode2; 1232 (i * 8));
1174 for (i = 0; i < 4; i++)
1175 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1176 E1000_LEDCTL_MODE_LED_ON)
1177 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1178 (i * 8));
1179 }
1180 1233
1181 wr32(E1000_LEDCTL, ledctl_blink); 1234 wr32(E1000_LEDCTL, ledctl_blink);
1182 1235
@@ -1191,15 +1244,7 @@ s32 igb_blink_led(struct e1000_hw *hw)
1191 **/ 1244 **/
1192s32 igb_led_off(struct e1000_hw *hw) 1245s32 igb_led_off(struct e1000_hw *hw)
1193{ 1246{
1194 u32 ctrl;
1195
1196 switch (hw->phy.media_type) { 1247 switch (hw->phy.media_type) {
1197 case e1000_media_type_fiber:
1198 ctrl = rd32(E1000_CTRL);
1199 ctrl |= E1000_CTRL_SWDPIN0;
1200 ctrl |= E1000_CTRL_SWDPIO0;
1201 wr32(E1000_CTRL, ctrl);
1202 break;
1203 case e1000_media_type_copper: 1248 case e1000_media_type_copper:
1204 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); 1249 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1205 break; 1250 break;
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h
index 1d690b4c9ae4..7518af8cbbf5 100644
--- a/drivers/net/igb/e1000_mac.h
+++ b/drivers/net/igb/e1000_mac.h
@@ -51,6 +51,8 @@ s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
51 u16 *duplex); 51 u16 *duplex);
52s32 igb_id_led_init(struct e1000_hw *hw); 52s32 igb_id_led_init(struct e1000_hw *hw);
53s32 igb_led_off(struct e1000_hw *hw); 53s32 igb_led_off(struct e1000_hw *hw);
54void igb_update_mc_addr_list(struct e1000_hw *hw,
55 u8 *mc_addr_list, u32 mc_addr_count);
54s32 igb_setup_link(struct e1000_hw *hw); 56s32 igb_setup_link(struct e1000_hw *hw);
55s32 igb_validate_mdi_setting(struct e1000_hw *hw); 57s32 igb_validate_mdi_setting(struct e1000_hw *hw);
56s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, 58s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
@@ -60,6 +62,7 @@ void igb_clear_hw_cntrs_base(struct e1000_hw *hw);
60void igb_clear_vfta(struct e1000_hw *hw); 62void igb_clear_vfta(struct e1000_hw *hw);
61s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add); 63s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add);
62void igb_config_collision_dist(struct e1000_hw *hw); 64void igb_config_collision_dist(struct e1000_hw *hw);
65void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
63void igb_mta_set(struct e1000_hw *hw, u32 hash_value); 66void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
64void igb_put_hw_semaphore(struct e1000_hw *hw); 67void igb_put_hw_semaphore(struct e1000_hw *hw);
65void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); 68void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c
index f50fac25be40..c1f4da630420 100644
--- a/drivers/net/igb/e1000_phy.c
+++ b/drivers/net/igb/e1000_phy.c
@@ -735,7 +735,7 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
735 * other: No software override. The flow control configuration 735 * other: No software override. The flow control configuration
736 * in the EEPROM is used. 736 * in the EEPROM is used.
737 */ 737 */
738 switch (hw->fc.type) { 738 switch (hw->fc.current_mode) {
739 case e1000_fc_none: 739 case e1000_fc_none:
740 /* 740 /*
741 * Flow control (RX & TX) is completely disabled by a 741 * Flow control (RX & TX) is completely disabled by a
@@ -992,7 +992,7 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
992 u32 ctrl; 992 u32 ctrl;
993 993
994 /* Turn off flow control when forcing speed/duplex */ 994 /* Turn off flow control when forcing speed/duplex */
995 hw->fc.type = e1000_fc_none; 995 hw->fc.current_mode = e1000_fc_none;
996 996
997 /* Force speed/duplex on the mac */ 997 /* Force speed/duplex on the mac */
998 ctrl = rd32(E1000_CTRL); 998 ctrl = rd32(E1000_CTRL);
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index 6e5924511e40..345d1442d6d6 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -305,6 +305,7 @@ enum {
305#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 305#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
306#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ 306#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
307#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 307#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
308#define E1000_GCR 0x05B00 /* PCI-Ex Control */
308#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 309#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
309#define E1000_SWSM 0x05B50 /* SW Semaphore */ 310#define E1000_SWSM 0x05B50 /* SW Semaphore */
310#define E1000_FWSM 0x05B54 /* FW Semaphore */ 311#define E1000_FWSM 0x05B54 /* FW Semaphore */
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index 9598ac09f4b8..114ccab1f2be 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -168,8 +168,7 @@ static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
168 ecmd->duplex = -1; 168 ecmd->duplex = -1;
169 } 169 }
170 170
171 ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) || 171 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
172 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
173 return 0; 172 return 0;
174} 173}
175 174
@@ -191,23 +190,20 @@ static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
191 190
192 if (ecmd->autoneg == AUTONEG_ENABLE) { 191 if (ecmd->autoneg == AUTONEG_ENABLE) {
193 hw->mac.autoneg = 1; 192 hw->mac.autoneg = 1;
194 if (hw->phy.media_type == e1000_media_type_fiber) 193 hw->phy.autoneg_advertised = ecmd->advertising |
195 hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full | 194 ADVERTISED_TP |
196 ADVERTISED_FIBRE | 195 ADVERTISED_Autoneg;
197 ADVERTISED_Autoneg;
198 else
199 hw->phy.autoneg_advertised = ecmd->advertising |
200 ADVERTISED_TP |
201 ADVERTISED_Autoneg;
202 ecmd->advertising = hw->phy.autoneg_advertised; 196 ecmd->advertising = hw->phy.autoneg_advertised;
203 } else 197 if (adapter->fc_autoneg)
198 hw->fc.requested_mode = e1000_fc_default;
199 } else {
204 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) { 200 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
205 clear_bit(__IGB_RESETTING, &adapter->state); 201 clear_bit(__IGB_RESETTING, &adapter->state);
206 return -EINVAL; 202 return -EINVAL;
207 } 203 }
204 }
208 205
209 /* reset the link */ 206 /* reset the link */
210
211 if (netif_running(adapter->netdev)) { 207 if (netif_running(adapter->netdev)) {
212 igb_down(adapter); 208 igb_down(adapter);
213 igb_up(adapter); 209 igb_up(adapter);
@@ -227,11 +223,11 @@ static void igb_get_pauseparam(struct net_device *netdev,
227 pause->autoneg = 223 pause->autoneg =
228 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 224 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
229 225
230 if (hw->fc.type == e1000_fc_rx_pause) 226 if (hw->fc.current_mode == e1000_fc_rx_pause)
231 pause->rx_pause = 1; 227 pause->rx_pause = 1;
232 else if (hw->fc.type == e1000_fc_tx_pause) 228 else if (hw->fc.current_mode == e1000_fc_tx_pause)
233 pause->tx_pause = 1; 229 pause->tx_pause = 1;
234 else if (hw->fc.type == e1000_fc_full) { 230 else if (hw->fc.current_mode == e1000_fc_full) {
235 pause->rx_pause = 1; 231 pause->rx_pause = 1;
236 pause->tx_pause = 1; 232 pause->tx_pause = 1;
237 } 233 }
@@ -249,26 +245,28 @@ static int igb_set_pauseparam(struct net_device *netdev,
249 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 245 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
250 msleep(1); 246 msleep(1);
251 247
252 if (pause->rx_pause && pause->tx_pause)
253 hw->fc.type = e1000_fc_full;
254 else if (pause->rx_pause && !pause->tx_pause)
255 hw->fc.type = e1000_fc_rx_pause;
256 else if (!pause->rx_pause && pause->tx_pause)
257 hw->fc.type = e1000_fc_tx_pause;
258 else if (!pause->rx_pause && !pause->tx_pause)
259 hw->fc.type = e1000_fc_none;
260
261 hw->fc.original_type = hw->fc.type;
262
263 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 248 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
249 hw->fc.requested_mode = e1000_fc_default;
264 if (netif_running(adapter->netdev)) { 250 if (netif_running(adapter->netdev)) {
265 igb_down(adapter); 251 igb_down(adapter);
266 igb_up(adapter); 252 igb_up(adapter);
267 } else 253 } else
268 igb_reset(adapter); 254 igb_reset(adapter);
269 } else 255 } else {
270 retval = ((hw->phy.media_type == e1000_media_type_fiber) ? 256 if (pause->rx_pause && pause->tx_pause)
271 igb_setup_link(hw) : igb_force_mac_fc(hw)); 257 hw->fc.requested_mode = e1000_fc_full;
258 else if (pause->rx_pause && !pause->tx_pause)
259 hw->fc.requested_mode = e1000_fc_rx_pause;
260 else if (!pause->rx_pause && pause->tx_pause)
261 hw->fc.requested_mode = e1000_fc_tx_pause;
262 else if (!pause->rx_pause && !pause->tx_pause)
263 hw->fc.requested_mode = e1000_fc_none;
264
265 hw->fc.current_mode = hw->fc.requested_mode;
266
267 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
268 igb_force_mac_fc(hw) : igb_setup_link(hw));
269 }
272 270
273 clear_bit(__IGB_RESETTING, &adapter->state); 271 clear_bit(__IGB_RESETTING, &adapter->state);
274 return retval; 272 return retval;
@@ -1483,8 +1481,7 @@ static int igb_setup_loopback_test(struct igb_adapter *adapter)
1483 struct e1000_hw *hw = &adapter->hw; 1481 struct e1000_hw *hw = &adapter->hw;
1484 u32 reg; 1482 u32 reg;
1485 1483
1486 if (hw->phy.media_type == e1000_media_type_fiber || 1484 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1487 hw->phy.media_type == e1000_media_type_internal_serdes) {
1488 reg = rd32(E1000_RCTL); 1485 reg = rd32(E1000_RCTL);
1489 reg |= E1000_RCTL_LBM_TCVR; 1486 reg |= E1000_RCTL_LBM_TCVR;
1490 wr32(E1000_RCTL, reg); 1487 wr32(E1000_RCTL, reg);
@@ -1843,7 +1840,6 @@ static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1843static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1840static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1844{ 1841{
1845 struct igb_adapter *adapter = netdev_priv(netdev); 1842 struct igb_adapter *adapter = netdev_priv(netdev);
1846 struct e1000_hw *hw = &adapter->hw;
1847 1843
1848 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 1844 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1849 return -EOPNOTSUPP; 1845 return -EOPNOTSUPP;
@@ -1852,11 +1848,6 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1852 !device_can_wakeup(&adapter->pdev->dev)) 1848 !device_can_wakeup(&adapter->pdev->dev))
1853 return wol->wolopts ? -EOPNOTSUPP : 0; 1849 return wol->wolopts ? -EOPNOTSUPP : 0;
1854 1850
1855 switch (hw->device_id) {
1856 default:
1857 break;
1858 }
1859
1860 /* these settings will always override what we currently have */ 1851 /* these settings will always override what we currently have */
1861 adapter->wol = 0; 1852 adapter->wol = 0;
1862 1853
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index adb09d32625d..fb3273517587 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -65,6 +65,7 @@ static struct pci_device_id igb_pci_tbl[] = {
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
@@ -127,7 +128,7 @@ static void igb_restore_vlan(struct igb_adapter *);
127static void igb_ping_all_vfs(struct igb_adapter *); 128static void igb_ping_all_vfs(struct igb_adapter *);
128static void igb_msg_task(struct igb_adapter *); 129static void igb_msg_task(struct igb_adapter *);
129static int igb_rcv_msg_from_vf(struct igb_adapter *, u32); 130static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
130static void igb_set_mc_list_pools(struct igb_adapter *, int, u16); 131static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
131static void igb_vmm_control(struct igb_adapter *); 132static void igb_vmm_control(struct igb_adapter *);
132static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *); 133static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
133static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 134static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
@@ -1129,7 +1130,7 @@ void igb_reset(struct igb_adapter *adapter)
1129 } 1130 }
1130 fc->pause_time = 0xFFFF; 1131 fc->pause_time = 0xFFFF;
1131 fc->send_xon = 1; 1132 fc->send_xon = 1;
1132 fc->type = fc->original_type; 1133 fc->current_mode = fc->requested_mode;
1133 1134
1134 /* disable receive for all VFs and wait one second */ 1135 /* disable receive for all VFs and wait one second */
1135 if (adapter->vfs_allocated_count) { 1136 if (adapter->vfs_allocated_count) {
@@ -1426,8 +1427,8 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1426 hw->mac.autoneg = true; 1427 hw->mac.autoneg = true;
1427 hw->phy.autoneg_advertised = 0x2f; 1428 hw->phy.autoneg_advertised = 0x2f;
1428 1429
1429 hw->fc.original_type = e1000_fc_default; 1430 hw->fc.requested_mode = e1000_fc_default;
1430 hw->fc.type = e1000_fc_default; 1431 hw->fc.current_mode = e1000_fc_default;
1431 1432
1432 adapter->itr_setting = IGB_DEFAULT_ITR; 1433 adapter->itr_setting = IGB_DEFAULT_ITR;
1433 adapter->itr = IGB_START_ITR; 1434 adapter->itr = IGB_START_ITR;
@@ -2535,7 +2536,6 @@ static void igb_set_multi(struct net_device *netdev)
2535{ 2536{
2536 struct igb_adapter *adapter = netdev_priv(netdev); 2537 struct igb_adapter *adapter = netdev_priv(netdev);
2537 struct e1000_hw *hw = &adapter->hw; 2538 struct e1000_hw *hw = &adapter->hw;
2538 struct e1000_mac_info *mac = &hw->mac;
2539 struct dev_mc_list *mc_ptr; 2539 struct dev_mc_list *mc_ptr;
2540 u8 *mta_list = NULL; 2540 u8 *mta_list = NULL;
2541 u32 rctl; 2541 u32 rctl;
@@ -2558,13 +2558,18 @@ static void igb_set_multi(struct net_device *netdev)
2558 } 2558 }
2559 wr32(E1000_RCTL, rctl); 2559 wr32(E1000_RCTL, rctl);
2560 2560
2561 if (netdev->mc_count) { 2561 if (!netdev->mc_count) {
2562 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); 2562 /* nothing to program, so clear mc list */
2563 if (!mta_list) { 2563 igb_update_mc_addr_list(hw, NULL, 0);
2564 dev_err(&adapter->pdev->dev, 2564 igb_restore_vf_multicasts(adapter);
2565 "failed to allocate multicast filter list\n"); 2565 return;
2566 return; 2566 }
2567 } 2567
2568 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2569 if (!mta_list) {
2570 dev_err(&adapter->pdev->dev,
2571 "failed to allocate multicast filter list\n");
2572 return;
2568 } 2573 }
2569 2574
2570 /* The shared function expects a packed array of only addresses. */ 2575 /* The shared function expects a packed array of only addresses. */
@@ -2576,14 +2581,9 @@ static void igb_set_multi(struct net_device *netdev)
2576 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); 2581 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2577 mc_ptr = mc_ptr->next; 2582 mc_ptr = mc_ptr->next;
2578 } 2583 }
2579 igb_update_mc_addr_list(hw, mta_list, i, 2584 igb_update_mc_addr_list(hw, mta_list, i);
2580 adapter->vfs_allocated_count + 1,
2581 mac->rar_entry_count);
2582
2583 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2584 igb_restore_vf_multicasts(adapter);
2585
2586 kfree(mta_list); 2585 kfree(mta_list);
2586 igb_restore_vf_multicasts(adapter);
2587} 2587}
2588 2588
2589/* Need to wait a few seconds after link up to get diagnostic information from 2589/* Need to wait a few seconds after link up to get diagnostic information from
@@ -2618,10 +2618,6 @@ static bool igb_has_link(struct igb_adapter *adapter)
2618 link_active = true; 2618 link_active = true;
2619 } 2619 }
2620 break; 2620 break;
2621 case e1000_media_type_fiber:
2622 ret_val = hw->mac.ops.check_for_link(hw);
2623 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2624 break;
2625 case e1000_media_type_internal_serdes: 2621 case e1000_media_type_internal_serdes:
2626 ret_val = hw->mac.ops.check_for_link(hw); 2622 ret_val = hw->mac.ops.check_for_link(hw);
2627 link_active = hw->mac.serdes_has_link; 2623 link_active = hw->mac.serdes_has_link;
@@ -4542,6 +4538,20 @@ static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4542 adapter->hw_csum_good++; 4538 adapter->hw_csum_good++;
4543} 4539}
4544 4540
4541static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4542 union e1000_adv_rx_desc *rx_desc)
4543{
4544 /* HW will not DMA in data larger than the given buffer, even if it
4545 * parses the (NFS, of course) header to be larger. In that case, it
4546 * fills the header buffer and spills the rest into the page.
4547 */
4548 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4549 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4550 if (hlen > adapter->rx_ps_hdr_size)
4551 hlen = adapter->rx_ps_hdr_size;
4552 return hlen;
4553}
4554
4545static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring, 4555static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4546 int *work_done, int budget) 4556 int *work_done, int budget)
4547{ 4557{
@@ -4556,7 +4566,8 @@ static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4556 int cleaned_count = 0; 4566 int cleaned_count = 0;
4557 unsigned int total_bytes = 0, total_packets = 0; 4567 unsigned int total_bytes = 0, total_packets = 0;
4558 unsigned int i; 4568 unsigned int i;
4559 u32 length, hlen, staterr; 4569 u32 staterr;
4570 u16 length;
4560 4571
4561 i = rx_ring->next_to_clean; 4572 i = rx_ring->next_to_clean;
4562 buffer_info = &rx_ring->buffer_info[i]; 4573 buffer_info = &rx_ring->buffer_info[i];
@@ -4593,17 +4604,8 @@ static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4593 goto send_up; 4604 goto send_up;
4594 } 4605 }
4595 4606
4596 /* HW will not DMA in data larger than the given buffer, even 4607 if (buffer_info->dma) {
4597 * if it parses the (NFS, of course) header to be larger. In 4608 u16 hlen = igb_get_hlen(adapter, rx_desc);
4598 * that case, it fills the header buffer and spills the rest
4599 * into the page.
4600 */
4601 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4602 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4603 if (hlen > adapter->rx_ps_hdr_size)
4604 hlen = adapter->rx_ps_hdr_size;
4605
4606 if (!skb_shinfo(skb)->nr_frags) {
4607 pci_unmap_single(pdev, buffer_info->dma, 4609 pci_unmap_single(pdev, buffer_info->dma,
4608 adapter->rx_ps_hdr_size, 4610 adapter->rx_ps_hdr_size,
4609 PCI_DMA_FROMDEVICE); 4611 PCI_DMA_FROMDEVICE);
@@ -5033,6 +5035,34 @@ static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5033 } 5035 }
5034} 5036}
5035 5037
5038s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5039{
5040 struct igb_adapter *adapter = hw->back;
5041 u16 cap_offset;
5042
5043 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5044 if (!cap_offset)
5045 return -E1000_ERR_CONFIG;
5046
5047 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5048
5049 return 0;
5050}
5051
5052s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5053{
5054 struct igb_adapter *adapter = hw->back;
5055 u16 cap_offset;
5056
5057 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5058 if (!cap_offset)
5059 return -E1000_ERR_CONFIG;
5060
5061 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5062
5063 return 0;
5064}
5065
5036static void igb_vlan_rx_register(struct net_device *netdev, 5066static void igb_vlan_rx_register(struct net_device *netdev,
5037 struct vlan_group *grp) 5067 struct vlan_group *grp)
5038{ 5068{
@@ -5136,14 +5166,6 @@ int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5136 5166
5137 mac->autoneg = 0; 5167 mac->autoneg = 0;
5138 5168
5139 /* Fiber NICs only allow 1000 gbps Full duplex */
5140 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5141 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5142 dev_err(&adapter->pdev->dev,
5143 "Unsupported Speed/Duplex configuration\n");
5144 return -EINVAL;
5145 }
5146
5147 switch (spddplx) { 5169 switch (spddplx) {
5148 case SPEED_10 + DUPLEX_HALF: 5170 case SPEED_10 + DUPLEX_HALF:
5149 mac->forced_speed_duplex = ADVERTISE_10_HALF; 5171 mac->forced_speed_duplex = ADVERTISE_10_HALF;
@@ -5452,19 +5474,6 @@ static void igb_io_resume(struct pci_dev *pdev)
5452 igb_get_hw_control(adapter); 5474 igb_get_hw_control(adapter);
5453} 5475}
5454 5476
5455static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5456 int entry_count, u16 total_rar_filters)
5457{
5458 struct e1000_hw *hw = &adapter->hw;
5459 int i = adapter->vfs_allocated_count + 1;
5460
5461 if ((i + entry_count) < total_rar_filters)
5462 total_rar_filters = i + entry_count;
5463
5464 for (; i < total_rar_filters; i++)
5465 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5466}
5467
5468static int igb_set_vf_mac(struct igb_adapter *adapter, 5477static int igb_set_vf_mac(struct igb_adapter *adapter,
5469 int vf, unsigned char *mac_addr) 5478 int vf, unsigned char *mac_addr)
5470{ 5479{