11 files changed, 710 insertions, 48 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index 0a2368fa6bc6..6b256c275e10 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -64,7 +64,14 @@ static s32  igb_reset_init_script_82575(struct e1000_hw *);
 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
+static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
+static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
+static s32  igb_update_nvm_checksum_with_offset(struct e1000_hw *hw,
+                                                u16 offset);
+static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
+                                                u16 offset);
+static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
+static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
 static const u16 e1000_82580_rxpbs_table[] =
        { 36, 72, 144, 1, 2, 4, 8, 16,
          35, 70, 140 };
@@ -129,6 +136,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
                break;
        case E1000_DEV_ID_82580_COPPER:
        case E1000_DEV_ID_82580_FIBER:
+        case E1000_DEV_ID_82580_QUAD_FIBER:
        case E1000_DEV_ID_82580_SERDES:
        case E1000_DEV_ID_82580_SGMII:
        case E1000_DEV_ID_82580_COPPER_DUAL:
@@ -194,7 +202,11 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
        mac->arc_subsystem_valid =
                (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
                        ? true : false;
+        /* enable EEE on i350 parts */
+        if (mac->type == e1000_i350)
+                dev_spec->eee_disable = false;
+        else
+                dev_spec->eee_disable = true;
        /* physical interface link setup */
        mac->ops.setup_physical_interface =
                (hw->phy.media_type == e1000_media_type_copper)
@@ -232,14 +244,42 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
         */
        size += NVM_WORD_SIZE_BASE_SHIFT;
-        /* EEPROM access above 16k is unsupported */
-        if (size > 14)
-                size = 14;
        nvm->word_size = 1 << size;
+        if (nvm->word_size == (1 << 15))
+                nvm->page_size = 128;
-        /* if 82576 then initialize mailbox parameters */
+        /* NVM Function Pointers */
-        if (mac->type == e1000_82576)
+        nvm->ops.acquire = igb_acquire_nvm_82575;
+        if (nvm->word_size < (1 << 15))
+                nvm->ops.read = igb_read_nvm_eerd;
+        else
+                nvm->ops.read = igb_read_nvm_spi;
+        nvm->ops.release = igb_release_nvm_82575;
+        switch (hw->mac.type) {
+        case e1000_82580:
+                nvm->ops.validate = igb_validate_nvm_checksum_82580;
+                nvm->ops.update = igb_update_nvm_checksum_82580;
+                break;
+        case e1000_i350:
+                nvm->ops.validate = igb_validate_nvm_checksum_i350;
+                nvm->ops.update = igb_update_nvm_checksum_i350;
+                break;
+        default:
+                nvm->ops.validate = igb_validate_nvm_checksum;
+                nvm->ops.update = igb_update_nvm_checksum;
+        }
+        nvm->ops.write = igb_write_nvm_spi;
+        /* if part supports SR-IOV then initialize mailbox parameters */
+        switch (mac->type) {
+        case e1000_82576:
+        case e1000_i350:
                igb_init_mbx_params_pf(hw);
+                break;
+        default:
+                break;
+        }
        /* setup PHY parameters */
        if (phy->media_type != e1000_media_type_copper) {
@@ -1747,6 +1787,248 @@ u16 igb_rxpbs_adjust_82580(u32 data)
        return ret_val;
 }
+/**
+ *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
+ *  checksum
+ *  @hw: pointer to the HW structure
+ *  @offset: offset in words of the checksum protected region
+ *
+ *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
+ *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
+ **/
+s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
+{
+        s32 ret_val = 0;
+        u16 checksum = 0;
+        u16 i, nvm_data;
+        for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
+                ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
+                if (ret_val) {
+                        hw_dbg("NVM Read Error\n");
+                        goto out;
+                }
+                checksum += nvm_data;
+        }
+        if (checksum != (u16) NVM_SUM) {
+                hw_dbg("NVM Checksum Invalid\n");
+                ret_val = -E1000_ERR_NVM;
+                goto out;
+        }
+out:
+        return ret_val;
+}
+/**
+ *  igb_update_nvm_checksum_with_offset - Update EEPROM
+ *  checksum
+ *  @hw: pointer to the HW structure
+ *  @offset: offset in words of the checksum protected region
+ *
+ *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
+ *  up to the checksum.  Then calculates the EEPROM checksum and writes the
+ *  value to the EEPROM.
+ **/
+s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
+{
+        s32 ret_val;
+        u16 checksum = 0;
+        u16 i, nvm_data;
+        for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
+                ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
+                if (ret_val) {
+                        hw_dbg("NVM Read Error while updating checksum.\n");
+                        goto out;
+                }
+                checksum += nvm_data;
+        }
+        checksum = (u16) NVM_SUM - checksum;
+        ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
+                                &checksum);
+        if (ret_val)
+                hw_dbg("NVM Write Error while updating checksum.\n");
+out:
+        return ret_val;
+}
+/**
+ *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Calculates the EEPROM section checksum by reading/adding each word of
+ *  the EEPROM and then verifies that the sum of the EEPROM is
+ *  equal to 0xBABA.
+ **/
+static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
+{
+        s32 ret_val = 0;
+        u16 eeprom_regions_count = 1;
+        u16 j, nvm_data;
+        u16 nvm_offset;
+        ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
+        if (ret_val) {
+                hw_dbg("NVM Read Error\n");
+                goto out;
+        }
+        if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
+                /* if chekcsums compatibility bit is set validate checksums
+                 * for all 4 ports. */
+                eeprom_regions_count = 4;
+        }
+        for (j = 0; j < eeprom_regions_count; j++) {
+                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
+                ret_val = igb_validate_nvm_checksum_with_offset(hw,
+                                                                nvm_offset);
+                if (ret_val != 0)
+                        goto out;
+        }
+out:
+        return ret_val;
+}
+/**
+ *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Updates the EEPROM section checksums for all 4 ports by reading/adding
+ *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
+ *  checksum and writes the value to the EEPROM.
+ **/
+static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
+{
+        s32 ret_val;
+        u16 j, nvm_data;
+        u16 nvm_offset;
+        ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
+        if (ret_val) {
+                hw_dbg("NVM Read Error while updating checksum"
+                        " compatibility bit.\n");
+                goto out;
+        }
+        if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
+                /* set compatibility bit to validate checksums appropriately */
+                nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
+                ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
+                                        &nvm_data);
+                if (ret_val) {
+                        hw_dbg("NVM Write Error while updating checksum"
+                                " compatibility bit.\n");
+                        goto out;
+                }
+        }
+        for (j = 0; j < 4; j++) {
+                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
+                ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
+                if (ret_val)
+                        goto out;
+        }
+out:
+        return ret_val;
+}
+/**
+ *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Calculates the EEPROM section checksum by reading/adding each word of
+ *  the EEPROM and then verifies that the sum of the EEPROM is
+ *  equal to 0xBABA.
+ **/
+static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
+{
+        s32 ret_val = 0;
+        u16 j;
+        u16 nvm_offset;
+        for (j = 0; j < 4; j++) {
+                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
+                ret_val = igb_validate_nvm_checksum_with_offset(hw,
+                                                                nvm_offset);
+                if (ret_val != 0)
+                        goto out;
+        }
+out:
+        return ret_val;
+}
+/**
+ *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Updates the EEPROM section checksums for all 4 ports by reading/adding
+ *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
+ *  checksum and writes the value to the EEPROM.
+ **/
+static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
+{
+        s32 ret_val = 0;
+        u16 j;
+        u16 nvm_offset;
+        for (j = 0; j < 4; j++) {
+                nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
+                ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
+                if (ret_val != 0)
+                        goto out;
+        }
+out:
+        return ret_val;
+}
+/**
+ *  igb_set_eee_i350 - Enable/disable EEE support
+ *  @hw: pointer to the HW structure
+ *
+ *  Enable/disable EEE based on setting in dev_spec structure.
+ *
+ **/
+s32 igb_set_eee_i350(struct e1000_hw *hw)
+{
+        s32 ret_val = 0;
+        u32 ipcnfg, eeer, ctrl_ext;
+        ctrl_ext = rd32(E1000_CTRL_EXT);
+        if ((hw->mac.type != e1000_i350) ||
+            (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
+                goto out;
+        ipcnfg = rd32(E1000_IPCNFG);
+        eeer = rd32(E1000_EEER);
+        /* enable or disable per user setting */
+        if (!(hw->dev_spec._82575.eee_disable)) {
+                ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
+                        E1000_IPCNFG_EEE_100M_AN);
+                eeer |= (E1000_EEER_TX_LPI_EN |
+                        E1000_EEER_RX_LPI_EN |
+                        E1000_EEER_LPI_FC);
+        } else {
+                ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
+                        E1000_IPCNFG_EEE_100M_AN);
+                eeer &= ~(E1000_EEER_TX_LPI_EN |
+                        E1000_EEER_RX_LPI_EN |
+                        E1000_EEER_LPI_FC);
+        }
+        wr32(E1000_IPCNFG, ipcnfg);
+        wr32(E1000_EEER, eeer);
+out:
+        return ret_val;
+}
 static struct e1000_mac_operations e1000_mac_ops_82575 = {
        .init_hw              = igb_init_hw_82575,
        .check_for_link       = igb_check_for_link_82575,
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index 1d01af2472e7..dd6df3498998 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -251,5 +251,6 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
 void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
 u16 igb_rxpbs_adjust_82580(u32 data);
+s32 igb_set_eee_i350(struct e1000_hw *);
 #endif
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 6319ed902bc0..6b80d40110ca 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -51,6 +51,7 @@
 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX  0x00400000
 #define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
+#define E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000
 #define E1000_CTRL_EXT_EIAME          0x01000000
 #define E1000_CTRL_EXT_IRCA           0x00000001
 /* Interrupt delay cancellation */
@@ -110,6 +111,7 @@
 /* Management Control */
 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
+#define E1000_MANC_EN_BMC2OS     0x10000000 /* OSBMC is Enabled or not */
 /* Enable Neighbor Discovery Filtering */
 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
@@ -286,7 +288,34 @@
 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
-/* Transmit Arbitration Count */
+/* DMA Coalescing register fields */
+#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coalescing
+                                                        * Watchdog Timer */
+#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coalescing Receive
+                                                        * Threshold */
+#define E1000_DMACR_DMACTHR_SHIFT       16
+#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe
+                                                        * transactions */
+#define E1000_DMACR_DMAC_LX_SHIFT       28
+#define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
+#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coalescing Transmit
+                                                        * Threshold */
+#define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
+#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Receive Traffic Rate
+                                                        * Threshold */
+#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rcv packet rate in
+                                                        * current window */
+#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rcv Traffic
+                                                        * Current Cnt */
+#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* Flow ctrl Rcv Threshold
+                                                        * High val */
+#define E1000_FCRTC_RTH_COAL_SHIFT      4
+#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision */
 /* SerDes Control */
 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
@@ -565,6 +594,8 @@
 #define NVM_INIT_CONTROL3_PORT_A   0x0024
 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 #define NVM_CHECKSUM_REG           0x003F
+#define NVM_COMPATIBILITY_REG_3    0x0003
+#define NVM_COMPATIBILITY_BIT_MASK 0x8000
 #define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
 #define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
@@ -599,6 +630,7 @@
 /* NVM Commands - SPI */
 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
+#define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
@@ -757,6 +789,17 @@
 #define E1000_MDIC_ERROR     0x40000000
 #define E1000_MDIC_DEST      0x80000000
+/* Thermal Sensor */
+#define E1000_THSTAT_PWR_DOWN       0x00000001 /* Power Down Event */
+#define E1000_THSTAT_LINK_THROTTLE  0x00000002 /* Link Speed Throttle Event */
+/* Energy Efficient Ethernet */
+#define E1000_IPCNFG_EEE_1G_AN       0x00000008  /* EEE Enable 1G AN */
+#define E1000_IPCNFG_EEE_100M_AN     0x00000004  /* EEE Enable 100M AN */
+#define E1000_EEER_TX_LPI_EN         0x00010000  /* EEE Tx LPI Enable */
+#define E1000_EEER_RX_LPI_EN         0x00020000  /* EEE Rx LPI Enable */
+#define E1000_EEER_LPI_FC            0x00040000  /* EEE Enable on FC */
 /* SerDes Control */
 #define E1000_GEN_CTL_READY             0x80000000
 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
@@ -770,4 +813,11 @@
 #define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision based
                                                      on DMA coal */
+/* Tx Rate-Scheduler Config fields */
+#define E1000_RTTBCNRC_RS_ENA           0x80000000
+#define E1000_RTTBCNRC_RF_DEC_MASK      0x00003FFF
+#define E1000_RTTBCNRC_RF_INT_SHIFT     14
+#define E1000_RTTBCNRC_RF_INT_MASK      \
+        (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
 #endif
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h
index e2638afb8cdc..27153e8d7b16 100644
--- a/drivers/net/igb/e1000_hw.h
+++ b/drivers/net/igb/e1000_hw.h
@@ -54,6 +54,7 @@ struct e1000_hw;
 #define E1000_DEV_ID_82580_SERDES             0x1510
 #define E1000_DEV_ID_82580_SGMII              0x1511
 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
+#define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
 #define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
 #define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
 #define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
@@ -247,6 +248,10 @@ struct e1000_hw_stats {
        u64 scvpc;
        u64 hrmpc;
        u64 doosync;
+        u64 o2bgptc;
+        u64 o2bspc;
+        u64 b2ospc;
+        u64 b2ogprc;
 };
 struct e1000_phy_stats {
@@ -331,6 +336,8 @@ struct e1000_nvm_operations {
        s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
        void (*release)(struct e1000_hw *);
        s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
+        s32  (*update)(struct e1000_hw *);
+        s32  (*validate)(struct e1000_hw *);
 };
 struct e1000_info {
@@ -417,7 +424,6 @@ struct e1000_phy_info {
 struct e1000_nvm_info {
        struct e1000_nvm_operations ops;
        enum e1000_nvm_type type;
        enum e1000_nvm_override override;
@@ -483,6 +489,7 @@ struct e1000_mbx_info {
 struct e1000_dev_spec_82575 {
        bool sgmii_active;
        bool global_device_reset;
+        bool eee_disable;
 };
 struct e1000_hw {
diff --git a/drivers/net/igb/e1000_mbx.c b/drivers/net/igb/e1000_mbx.c
index c474cdb70047..78d48c7fa859 100644
--- a/drivers/net/igb/e1000_mbx.c
+++ b/drivers/net/igb/e1000_mbx.c
@@ -422,26 +422,24 @@ s32 igb_init_mbx_params_pf(struct e1000_hw *hw)
 {
        struct e1000_mbx_info *mbx = &hw->mbx;
-        if (hw->mac.type == e1000_82576) {
+        mbx->timeout = 0;
-                mbx->timeout = 0;
+        mbx->usec_delay = 0;
-                mbx->usec_delay = 0;
+        mbx->size = E1000_VFMAILBOX_SIZE;
-                mbx->size = E1000_VFMAILBOX_SIZE;
+        mbx->ops.read = igb_read_mbx_pf;
-                mbx->ops.read = igb_read_mbx_pf;
+        mbx->ops.write = igb_write_mbx_pf;
-                mbx->ops.write = igb_write_mbx_pf;
+        mbx->ops.read_posted = igb_read_posted_mbx;
-                mbx->ops.read_posted = igb_read_posted_mbx;
+        mbx->ops.write_posted = igb_write_posted_mbx;
-                mbx->ops.write_posted = igb_write_posted_mbx;
+        mbx->ops.check_for_msg = igb_check_for_msg_pf;
-                mbx->ops.check_for_msg = igb_check_for_msg_pf;
+        mbx->ops.check_for_ack = igb_check_for_ack_pf;
-                mbx->ops.check_for_ack = igb_check_for_ack_pf;
+        mbx->ops.check_for_rst = igb_check_for_rst_pf;
-                mbx->ops.check_for_rst = igb_check_for_rst_pf;
+        mbx->stats.msgs_tx = 0;
-                mbx->stats.msgs_tx = 0;
+        mbx->stats.msgs_rx = 0;
-                mbx->stats.msgs_rx = 0;
+        mbx->stats.reqs = 0;
-                mbx->stats.reqs = 0;
+        mbx->stats.acks = 0;
-                mbx->stats.acks = 0;
+        mbx->stats.rsts = 0;
-                mbx->stats.rsts = 0;
-        }
        return 0;
 }
diff --git a/drivers/net/igb/e1000_nvm.c b/drivers/net/igb/e1000_nvm.c
index 6b5cc2cc453d..75bf36a4baee 100644
--- a/drivers/net/igb/e1000_nvm.c
+++ b/drivers/net/igb/e1000_nvm.c
@@ -318,6 +318,68 @@ out:
 }
 /**
+ *  igb_read_nvm_spi - Read EEPROM's using SPI
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of word in the EEPROM to read
+ *  @words: number of words to read
+ *  @data: word read from the EEPROM
+ *
+ *  Reads a 16 bit word from the EEPROM.
+ **/
+s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
+{
+        struct e1000_nvm_info *nvm = &hw->nvm;
+        u32 i = 0;
+        s32 ret_val;
+        u16 word_in;
+        u8 read_opcode = NVM_READ_OPCODE_SPI;
+        /*
+         * A check for invalid values:  offset too large, too many words,
+         * and not enough words.
+         */
+        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
+            (words == 0)) {
+                hw_dbg("nvm parameter(s) out of bounds\n");
+                ret_val = -E1000_ERR_NVM;
+                goto out;
+        }
+        ret_val = nvm->ops.acquire(hw);
+        if (ret_val)
+                goto out;
+        ret_val = igb_ready_nvm_eeprom(hw);
+        if (ret_val)
+                goto release;
+        igb_standby_nvm(hw);
+        if ((nvm->address_bits == 8) && (offset >= 128))
+                read_opcode |= NVM_A8_OPCODE_SPI;
+        /* Send the READ command (opcode + addr) */
+        igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
+        igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
+        /*
+         * Read the data.  SPI NVMs increment the address with each byte
+         * read and will roll over if reading beyond the end.  This allows
+         * us to read the whole NVM from any offset
+         */
+        for (i = 0; i < words; i++) {
+                word_in = igb_shift_in_eec_bits(hw, 16);
+                data[i] = (word_in >> 8) | (word_in << 8);
+        }
+release:
+        nvm->ops.release(hw);
+out:
+        return ret_val;
+}
+/**
 *  igb_read_nvm_eerd - Reads EEPROM using EERD register
 *  @hw: pointer to the HW structure
 *  @offset: offset of word in the EEPROM to read
@@ -353,7 +415,7 @@ s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
                        break;
                data[i] = (rd32(E1000_EERD) >>
-                           E1000_NVM_RW_REG_DATA);
+                        E1000_NVM_RW_REG_DATA);
        }
 out:
diff --git a/drivers/net/igb/e1000_nvm.h b/drivers/net/igb/e1000_nvm.h
index 29c956a84bd0..7f43564c4bcc 100644
--- a/drivers/net/igb/e1000_nvm.h
+++ b/drivers/net/igb/e1000_nvm.h
@@ -35,6 +35,7 @@ s32  igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
 s32  igb_read_part_string(struct e1000_hw *hw, u8 *part_num,
                          u32 part_num_size);
 s32  igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+s32  igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 s32  igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 s32  igb_validate_nvm_checksum(struct e1000_hw *hw);
 s32  igb_update_nvm_checksum(struct e1000_hw *hw);
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index 8ac83c5190d5..958ca3bda482 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -106,6 +106,19 @@
 #define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
+/* DMA Coalescing registers */
+#define E1000_DMACR             0x02508 /* Control Register */
+#define E1000_DMCTXTH           0x03550 /* Transmit Threshold */
+#define E1000_DMCTLX            0x02514 /* Time to Lx Request */
+#define E1000_DMCRTRH           0x05DD0 /* Receive Packet Rate Threshold */
+#define E1000_DMCCNT            0x05DD4 /* Current Rx Count */
+#define E1000_FCRTC             0x02170 /* Flow Control Rx high watermark */
+#define E1000_PCIEMISC          0x05BB8 /* PCIE misc config register */
+/* TX Rate Limit Registers */
+#define E1000_RTTDQSEL  0x3604  /* Tx Desc Plane Queue Select - WO */
+#define E1000_RTTBCNRC  0x36B0  /* Tx BCN Rate-Scheduler Config - WO */
 /* Split and Replication RX Control - RW */
 #define E1000_RXPBS    0x02404  /* Rx Packet Buffer Size - RW */
 /*
@@ -324,4 +337,18 @@
 /* DMA Coalescing registers */
 #define E1000_PCIEMISC          0x05BB8 /* PCIE misc config register */
+/* Energy Efficient Ethernet "EEE" register */
+#define E1000_IPCNFG  0x0E38  /* Internal PHY Configuration */
+#define E1000_EEER    0x0E30  /* Energy Efficient Ethernet */
+/* Thermal Sensor Register */
+#define E1000_THSTAT    0x08110 /* Thermal Sensor Status */
+/* OS2BMC Registers */
+#define E1000_B2OSPC    0x08FE0 /* BMC2OS packets sent by BMC */
+#define E1000_B2OGPRC   0x04158 /* BMC2OS packets received by host */
+#define E1000_O2BGPTC   0x08FE4 /* OS2BMC packets received by BMC */
+#define E1000_O2BSPC    0x0415C /* OS2BMC packets transmitted by host */
 #endif
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h
index 92a4ef09e55c..1c687e298d5e 100644
--- a/drivers/net/igb/igb.h
+++ b/drivers/net/igb/igb.h
@@ -77,6 +77,7 @@ struct vf_data_storage {
        unsigned long last_nack;
        u16 pf_vlan; /* When set, guest VLAN config not allowed. */
        u16 pf_qos;
+        u16 tx_rate;
 };
 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
@@ -323,6 +324,7 @@ struct igb_adapter {
        u16 rx_ring_count;
        unsigned int vfs_allocated_count;
        struct vf_data_storage *vf_data;
+        int vf_rate_link_speed;
        u32 rss_queues;
        u32 wvbr;
 };
@@ -331,6 +333,12 @@ struct igb_adapter {
 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 #define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
+#define IGB_FLAG_DMAC              (1 << 4)
+/* DMA Coalescing defines */
+#define IGB_MIN_TXPBSIZE           20408
+#define IGB_TX_BUF_4096            4096
+#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */
 #define IGB_82576_TSYNC_SHIFT 19
 #define IGB_82580_TSYNC_SHIFT 24
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index a70e16bcfa7e..d976733bbcc2 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -86,6 +86,10 @@ static const struct igb_stats igb_gstrings_stats[] = {
        IGB_STAT("tx_smbus", stats.mgptc),
        IGB_STAT("rx_smbus", stats.mgprc),
        IGB_STAT("dropped_smbus", stats.mgpdc),
+        IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
+        IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
+        IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
+        IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
 };
 #define IGB_NETDEV_STAT(_net_stat) { \
@@ -603,7 +607,10 @@ static void igb_get_regs(struct net_device *netdev,
        regs_buff[548] = rd32(E1000_TDFT);
        regs_buff[549] = rd32(E1000_TDFHS);
        regs_buff[550] = rd32(E1000_TDFPC);
+        regs_buff[551] = adapter->stats.o2bgptc;
+        regs_buff[552] = adapter->stats.b2ospc;
+        regs_buff[553] = adapter->stats.o2bspc;
+        regs_buff[554] = adapter->stats.b2ogprc;
 }
 static int igb_get_eeprom_len(struct net_device *netdev)
@@ -714,7 +721,7 @@ static int igb_set_eeprom(struct net_device *netdev,
        /* Update the checksum over the first part of the EEPROM if needed
         * and flush shadow RAM for 82573 controllers */
        if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
-                igb_update_nvm_checksum(hw);
+                hw->nvm.ops.update(hw);
        kfree(eeprom_buff);
        return ret_val;
@@ -727,8 +734,9 @@ static void igb_get_drvinfo(struct net_device *netdev,
        char firmware_version[32];
        u16 eeprom_data;
-        strncpy(drvinfo->driver,  igb_driver_name, 32);
+        strncpy(drvinfo->driver,  igb_driver_name, sizeof(drvinfo->driver) - 1);
-        strncpy(drvinfo->version, igb_driver_version, 32);
+        strncpy(drvinfo->version, igb_driver_version,
+                sizeof(drvinfo->version) - 1);
        /* EEPROM image version # is reported as firmware version # for
         * 82575 controllers */
@@ -738,8 +746,10 @@ static void igb_get_drvinfo(struct net_device *netdev,
                (eeprom_data & 0x0FF0) >> 4,
                eeprom_data & 0x000F);
-        strncpy(drvinfo->fw_version, firmware_version, 32);
+        strncpy(drvinfo->fw_version, firmware_version,
-        strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+                sizeof(drvinfo->fw_version) - 1);
+        strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
+                sizeof(drvinfo->bus_info) - 1);
        drvinfo->n_stats = IGB_STATS_LEN;
        drvinfo->testinfo_len = IGB_TEST_LEN;
        drvinfo->regdump_len = igb_get_regs_len(netdev);
@@ -1070,7 +1080,7 @@ static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
                {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
        for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
                wr32(reg, (_test[pat] & write));
-                val = rd32(reg);
+                val = rd32(reg) & mask;
                if (val != (_test[pat] & write & mask)) {
                        dev_err(&adapter->pdev->dev, "pattern test reg %04X "
                                "failed: got 0x%08X expected 0x%08X\n",
@@ -1999,6 +2009,12 @@ static int igb_set_coalesce(struct net_device *netdev,
        if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
                return -EINVAL;
+        /* If ITR is disabled, disable DMAC */
+        if (ec->rx_coalesce_usecs == 0) {
+                if (adapter->flags & IGB_FLAG_DMAC)
+                        adapter->flags &= ~IGB_FLAG_DMAC;
+        }
        /* convert to rate of irq's per second */
        if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
                adapter->rx_itr_setting = ec->rx_coalesce_usecs;
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 58c665b7513d..3d850af0cdda 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -50,12 +50,17 @@
 #endif
 #include "igb.h"
-#define DRV_VERSION "2.1.0-k2"
+#define MAJ 3
+#define MIN 0
+#define BUILD 6
+#define KFIX 2
+#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
+__stringify(BUILD) "-k" __stringify(KFIX)
 char igb_driver_name[] = "igb";
 char igb_driver_version[] = DRV_VERSION;
 static const char igb_driver_string[] =
                                "Intel(R) Gigabit Ethernet Network Driver";
-static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
+static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
 static const struct e1000_info *igb_info_tbl[] = {
        [board_82575] = &e1000_82575_info,
@@ -68,6 +73,7 @@ static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
+        { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
@@ -100,6 +106,7 @@ static void igb_free_all_rx_resources(struct igb_adapter *);
 static void igb_setup_mrqc(struct igb_adapter *);
 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 static void __devexit igb_remove(struct pci_dev *pdev);
+static void igb_init_hw_timer(struct igb_adapter *adapter);
 static int igb_sw_init(struct igb_adapter *);
 static int igb_open(struct net_device *);
 static int igb_close(struct net_device *);
@@ -149,6 +156,7 @@ static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
                                 struct ifla_vf_info *ivi);
+static void igb_check_vf_rate_limit(struct igb_adapter *);
 #ifdef CONFIG_PM
 static int igb_suspend(struct pci_dev *, pm_message_t);
@@ -1672,7 +1680,58 @@ void igb_reset(struct igb_adapter *adapter)
        if (hw->mac.ops.init_hw(hw))
                dev_err(&pdev->dev, "Hardware Error\n");
+        if (hw->mac.type > e1000_82580) {
+                if (adapter->flags & IGB_FLAG_DMAC) {
+                        u32 reg;
+                        /*
+                         * DMA Coalescing high water mark needs to be higher
+                         * than * the * Rx threshold.  The Rx threshold is
+                         * currently * pba - 6, so we * should use a high water
+                         * mark of pba * - 4. */
+                        hwm = (pba - 4) << 10;
+                        reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
+                               & E1000_DMACR_DMACTHR_MASK);
+                        /* transition to L0x or L1 if available..*/
+                        reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
+                        /* watchdog timer= +-1000 usec in 32usec intervals */
+                        reg |= (1000 >> 5);
+                        wr32(E1000_DMACR, reg);
+                        /* no lower threshold to disable coalescing(smart fifb)
+                         * -UTRESH=0*/
+                        wr32(E1000_DMCRTRH, 0);
+                        /* set hwm to PBA -  2 * max frame size */
+                        wr32(E1000_FCRTC, hwm);
+                        /*
+                         * This sets the time to wait before requesting tran-
+                         * sition to * low power state to number of usecs needed
+                         * to receive 1 512 * byte frame at gigabit line rate
+                         */
+                        reg = rd32(E1000_DMCTLX);
+                        reg |= IGB_DMCTLX_DCFLUSH_DIS;
+                        /* Delay 255 usec before entering Lx state. */
+                        reg |= 0xFF;
+                        wr32(E1000_DMCTLX, reg);
+                        /* free space in Tx packet buffer to wake from DMAC */
+                        wr32(E1000_DMCTXTH,
+                             (IGB_MIN_TXPBSIZE -
+                             (IGB_TX_BUF_4096 + adapter->max_frame_size))
+                             >> 6);
+                        /* make low power state decision controlled by DMAC */
+                        reg = rd32(E1000_PCIEMISC);
+                        reg |= E1000_PCIEMISC_LX_DECISION;
+                        wr32(E1000_PCIEMISC, reg);
+                } /* end if IGB_FLAG_DMAC set */
+        }
        if (hw->mac.type == e1000_82580) {
                u32 reg = rd32(E1000_PCIEMISC);
                wr32(E1000_PCIEMISC,
@@ -1882,7 +1941,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
        hw->mac.ops.reset_hw(hw);
        /* make sure the NVM is good */
-        if (igb_validate_nvm_checksum(hw) < 0) {
+        if (hw->nvm.ops.validate(hw) < 0) {
                dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
                err = -EIO;
                goto err_eeprom;
@@ -1990,6 +2049,9 @@ static int __devinit igb_probe(struct pci_dev *pdev,
        }
 #endif
+        /* do hw tstamp init after resetting */
+        igb_init_hw_timer(adapter);
        dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
        /* print bus type/speed/width info */
        dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
@@ -2012,7 +2074,13 @@ static int __devinit igb_probe(struct pci_dev *pdev,
                adapter->msix_entries ? "MSI-X" :
                (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
                adapter->num_rx_queues, adapter->num_tx_queues);
+        switch (hw->mac.type) {
+        case e1000_i350:
+                igb_set_eee_i350(hw);
+                break;
+        default:
+                break;
+        }
        return 0;
 err_register:
@@ -2149,6 +2217,9 @@ static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
                        random_ether_addr(mac_addr);
                        igb_set_vf_mac(adapter, i, mac_addr);
                }
+                /* DMA Coalescing is not supported in IOV mode. */
+                if (adapter->flags & IGB_FLAG_DMAC)
+                        adapter->flags &= ~IGB_FLAG_DMAC;
        }
 #endif /* CONFIG_PCI_IOV */
 }
@@ -2286,9 +2357,19 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
        spin_lock_init(&adapter->stats64_lock);
 #ifdef CONFIG_PCI_IOV
-        if (hw->mac.type == e1000_82576)
+        switch (hw->mac.type) {
-                adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs;
+        case e1000_82576:
+        case e1000_i350:
+                if (max_vfs > 7) {
+                        dev_warn(&pdev->dev,
+                                 "Maximum of 7 VFs per PF, using max\n");
+                        adapter->vfs_allocated_count = 7;
+                } else
+                        adapter->vfs_allocated_count = max_vfs;
+                break;
+        default:
+                break;
+        }
 #endif /* CONFIG_PCI_IOV */
        adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
@@ -2307,12 +2388,14 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
                return -ENOMEM;
        }
-        igb_init_hw_timer(adapter);
        igb_probe_vfs(adapter);
        /* Explicitly disable IRQ since the NIC can be in any state. */
        igb_irq_disable(adapter);
+        if (hw->mac.type == e1000_i350)
+                adapter->flags &= ~IGB_FLAG_DMAC;
        set_bit(__IGB_DOWN, &adapter->state);
        return 0;
 }
@@ -3467,7 +3550,7 @@ static void igb_watchdog_task(struct work_struct *work)
                                                   watchdog_task);
        struct e1000_hw *hw = &adapter->hw;
        struct net_device *netdev = adapter->netdev;
-        u32 link;
+        u32 link, ctrl_ext, thstat;
        int i;
        link = igb_has_link(adapter);
@@ -3491,6 +3574,25 @@ static void igb_watchdog_task(struct work_struct *work)
                               ((ctrl & E1000_CTRL_RFCE) ?  "RX" :
                               ((ctrl & E1000_CTRL_TFCE) ?  "TX" : "None")));
+                        /* check for thermal sensor event on i350,
+                         * copper only */
+                        if (hw->mac.type == e1000_i350) {
+                                thstat = rd32(E1000_THSTAT);
+                                ctrl_ext = rd32(E1000_CTRL_EXT);
+                                if ((hw->phy.media_type ==
+                                     e1000_media_type_copper) && !(ctrl_ext &
+                                     E1000_CTRL_EXT_LINK_MODE_SGMII)) {
+                                        if (thstat &
+                                            E1000_THSTAT_LINK_THROTTLE) {
+                                                printk(KERN_INFO "igb: %s The "
+                                                       "network adapter link "
+                                                       "speed was downshifted "
+                                                       "because it "
+                                                       "overheated.\n",
+                                                       netdev->name);
+                                        }
+                                }
+                        }
                        /* adjust timeout factor according to speed/duplex */
                        adapter->tx_timeout_factor = 1;
                        switch (adapter->link_speed) {
@@ -3505,6 +3607,7 @@ static void igb_watchdog_task(struct work_struct *work)
                        netif_carrier_on(netdev);
                        igb_ping_all_vfs(adapter);
+                        igb_check_vf_rate_limit(adapter);
                        /* link state has changed, schedule phy info update */
                        if (!test_bit(__IGB_DOWN, &adapter->state))
@@ -3515,6 +3618,22 @@ static void igb_watchdog_task(struct work_struct *work)
                if (netif_carrier_ok(netdev)) {
                        adapter->link_speed = 0;
                        adapter->link_duplex = 0;
+                        /* check for thermal sensor event on i350
+                         * copper only*/
+                        if (hw->mac.type == e1000_i350) {
+                                thstat = rd32(E1000_THSTAT);
+                                ctrl_ext = rd32(E1000_CTRL_EXT);
+                                if ((hw->phy.media_type ==
+                                     e1000_media_type_copper) && !(ctrl_ext &
+                                     E1000_CTRL_EXT_LINK_MODE_SGMII)) {
+                                        if (thstat & E1000_THSTAT_PWR_DOWN) {
+                                                printk(KERN_ERR "igb: %s The "
+                                                "network adapter was stopped "
+                                                "because it overheated.\n",
+                                                netdev->name);
+                                        }
+                                }
+                        }
                        /* Links status message must follow this format */
                        printk(KERN_INFO "igb: %s NIC Link is Down\n",
                               netdev->name);
@@ -4547,6 +4666,15 @@ void igb_update_stats(struct igb_adapter *adapter,
        adapter->stats.mgptc += rd32(E1000_MGTPTC);
        adapter->stats.mgprc += rd32(E1000_MGTPRC);
        adapter->stats.mgpdc += rd32(E1000_MGTPDC);
+        /* OS2BMC Stats */
+        reg = rd32(E1000_MANC);
+        if (reg & E1000_MANC_EN_BMC2OS) {
+                adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
+                adapter->stats.o2bspc += rd32(E1000_O2BSPC);
+                adapter->stats.b2ospc += rd32(E1000_B2OSPC);
+                adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
+        }
 }
 static irqreturn_t igb_msix_other(int irq, void *data)
@@ -6593,9 +6721,91 @@ static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
        return igb_set_vf_mac(adapter, vf, mac);
 }
+static int igb_link_mbps(int internal_link_speed)
+{
+        switch (internal_link_speed) {
+        case SPEED_100:
+                return 100;
+        case SPEED_1000:
+                return 1000;
+        default:
+                return 0;
+        }
+}
+static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
+                                  int link_speed)
+{
+        int rf_dec, rf_int;
+        u32 bcnrc_val;
+        if (tx_rate != 0) {
+                /* Calculate the rate factor values to set */
+                rf_int = link_speed / tx_rate;
+                rf_dec = (link_speed - (rf_int * tx_rate));
+                rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
+                bcnrc_val = E1000_RTTBCNRC_RS_ENA;
+                bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
+                               E1000_RTTBCNRC_RF_INT_MASK);
+                bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
+        } else {
+                bcnrc_val = 0;
+        }
+        wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
+        wr32(E1000_RTTBCNRC, bcnrc_val);
+}
+static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
+{
+        int actual_link_speed, i;
+        bool reset_rate = false;
+        /* VF TX rate limit was not set or not supported */
+        if ((adapter->vf_rate_link_speed == 0) ||
+            (adapter->hw.mac.type != e1000_82576))
+                return;
+        actual_link_speed = igb_link_mbps(adapter->link_speed);
+        if (actual_link_speed != adapter->vf_rate_link_speed) {
+                reset_rate = true;
+                adapter->vf_rate_link_speed = 0;
+                dev_info(&adapter->pdev->dev,
+                         "Link speed has been changed. VF Transmit "
+                         "rate is disabled\n");
+        }
+        for (i = 0; i < adapter->vfs_allocated_count; i++) {
+                if (reset_rate)
+                        adapter->vf_data[i].tx_rate = 0;
+                igb_set_vf_rate_limit(&adapter->hw, i,
+                                      adapter->vf_data[i].tx_rate,
+                                      actual_link_speed);
+        }
+}
 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
 {
-        return -EOPNOTSUPP;
+        struct igb_adapter *adapter = netdev_priv(netdev);
+        struct e1000_hw *hw = &adapter->hw;
+        int actual_link_speed;
+        if (hw->mac.type != e1000_82576)
+                return -EOPNOTSUPP;
+        actual_link_speed = igb_link_mbps(adapter->link_speed);
+        if ((vf >= adapter->vfs_allocated_count) ||
+            (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
+            (tx_rate < 0) || (tx_rate > actual_link_speed))
+                return -EINVAL;
+        adapter->vf_rate_link_speed = actual_link_speed;
+        adapter->vf_data[vf].tx_rate = (u16)tx_rate;
+        igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
+        return 0;
 }
 static int igb_ndo_get_vf_config(struct net_device *netdev,
@@ -6606,7 +6816,7 @@ static int igb_ndo_get_vf_config(struct net_device *netdev,
                return -EINVAL;
        ivi->vf = vf;
        memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
-        ivi->tx_rate = 0;
+        ivi->tx_rate = adapter->vf_data[vf].tx_rate;
        ivi->vlan = adapter->vf_data[vf].pf_vlan;
        ivi->qos = adapter->vf_data[vf].pf_qos;
        return 0;