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-rw-r--r--drivers/net/igb/e1000_82575.c446
-rw-r--r--drivers/net/igb/e1000_82575.h36
-rw-r--r--drivers/net/igb/e1000_defines.h38
-rw-r--r--drivers/net/igb/e1000_hw.h16
-rw-r--r--drivers/net/igb/e1000_mac.c144
-rw-r--r--drivers/net/igb/e1000_mac.h1
-rw-r--r--drivers/net/igb/e1000_nvm.c52
-rw-r--r--drivers/net/igb/e1000_phy.c138
-rw-r--r--drivers/net/igb/e1000_regs.h9
-rw-r--r--drivers/net/igb/igb.h51
-rw-r--r--drivers/net/igb/igb_ethtool.c203
-rw-r--r--drivers/net/igb/igb_main.c1284
12 files changed, 1626 insertions, 792 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index cda3ec879090..e098f234770f 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation. 4 Copyright(c) 2007 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -31,6 +31,7 @@
31 31
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <linux/if_ether.h>
34 35
35#include "e1000_mac.h" 36#include "e1000_mac.h"
36#include "e1000_82575.h" 37#include "e1000_82575.h"
@@ -45,7 +46,6 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *); 46static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 47static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 48static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32);
49static s32 igb_reset_hw_82575(struct e1000_hw *); 49static s32 igb_reset_hw_82575(struct e1000_hw *);
50static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 50static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51static s32 igb_setup_copper_link_82575(struct e1000_hw *); 51static s32 igb_setup_copper_link_82575(struct e1000_hw *);
@@ -84,6 +84,12 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
84 case E1000_DEV_ID_82575GB_QUAD_COPPER: 84 case E1000_DEV_ID_82575GB_QUAD_COPPER:
85 mac->type = e1000_82575; 85 mac->type = e1000_82575;
86 break; 86 break;
87 case E1000_DEV_ID_82576:
88 case E1000_DEV_ID_82576_FIBER:
89 case E1000_DEV_ID_82576_SERDES:
90 case E1000_DEV_ID_82576_QUAD_COPPER:
91 mac->type = e1000_82576;
92 break;
87 default: 93 default:
88 return -E1000_ERR_MAC_INIT; 94 return -E1000_ERR_MAC_INIT;
89 break; 95 break;
@@ -128,6 +134,8 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
128 mac->mta_reg_count = 128; 134 mac->mta_reg_count = 128;
129 /* Set rar entry count */ 135 /* Set rar entry count */
130 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 136 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
137 if (mac->type == e1000_82576)
138 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
131 /* Set if part includes ASF firmware */ 139 /* Set if part includes ASF firmware */
132 mac->asf_firmware_present = true; 140 mac->asf_firmware_present = true;
133 /* Set if manageability features are enabled. */ 141 /* Set if manageability features are enabled. */
@@ -171,6 +179,10 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
171 * for setting word_size. 179 * for setting word_size.
172 */ 180 */
173 size += NVM_WORD_SIZE_BASE_SHIFT; 181 size += NVM_WORD_SIZE_BASE_SHIFT;
182
183 /* EEPROM access above 16k is unsupported */
184 if (size > 14)
185 size = 14;
174 nvm->word_size = 1 << size; 186 nvm->word_size = 1 << size;
175 187
176 /* setup PHY parameters */ 188 /* setup PHY parameters */
@@ -222,7 +234,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
222} 234}
223 235
224/** 236/**
225 * e1000_acquire_phy_82575 - Acquire rights to access PHY 237 * igb_acquire_phy_82575 - Acquire rights to access PHY
226 * @hw: pointer to the HW structure 238 * @hw: pointer to the HW structure
227 * 239 *
228 * Acquire access rights to the correct PHY. This is a 240 * Acquire access rights to the correct PHY. This is a
@@ -238,7 +250,7 @@ static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
238} 250}
239 251
240/** 252/**
241 * e1000_release_phy_82575 - Release rights to access PHY 253 * igb_release_phy_82575 - Release rights to access PHY
242 * @hw: pointer to the HW structure 254 * @hw: pointer to the HW structure
243 * 255 *
244 * A wrapper to release access rights to the correct PHY. This is a 256 * A wrapper to release access rights to the correct PHY. This is a
@@ -253,7 +265,7 @@ static void igb_release_phy_82575(struct e1000_hw *hw)
253} 265}
254 266
255/** 267/**
256 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 268 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
257 * @hw: pointer to the HW structure 269 * @hw: pointer to the HW structure
258 * @offset: register offset to be read 270 * @offset: register offset to be read
259 * @data: pointer to the read data 271 * @data: pointer to the read data
@@ -268,7 +280,7 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
268 u32 i, i2ccmd = 0; 280 u32 i, i2ccmd = 0;
269 281
270 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 282 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
271 hw_dbg(hw, "PHY Address %u is out of range\n", offset); 283 hw_dbg("PHY Address %u is out of range\n", offset);
272 return -E1000_ERR_PARAM; 284 return -E1000_ERR_PARAM;
273 } 285 }
274 286
@@ -291,11 +303,11 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
291 break; 303 break;
292 } 304 }
293 if (!(i2ccmd & E1000_I2CCMD_READY)) { 305 if (!(i2ccmd & E1000_I2CCMD_READY)) {
294 hw_dbg(hw, "I2CCMD Read did not complete\n"); 306 hw_dbg("I2CCMD Read did not complete\n");
295 return -E1000_ERR_PHY; 307 return -E1000_ERR_PHY;
296 } 308 }
297 if (i2ccmd & E1000_I2CCMD_ERROR) { 309 if (i2ccmd & E1000_I2CCMD_ERROR) {
298 hw_dbg(hw, "I2CCMD Error bit set\n"); 310 hw_dbg("I2CCMD Error bit set\n");
299 return -E1000_ERR_PHY; 311 return -E1000_ERR_PHY;
300 } 312 }
301 313
@@ -306,7 +318,7 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
306} 318}
307 319
308/** 320/**
309 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 321 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
310 * @hw: pointer to the HW structure 322 * @hw: pointer to the HW structure
311 * @offset: register offset to write to 323 * @offset: register offset to write to
312 * @data: data to write at register offset 324 * @data: data to write at register offset
@@ -322,7 +334,7 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
322 u16 phy_data_swapped; 334 u16 phy_data_swapped;
323 335
324 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 336 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
325 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 337 hw_dbg("PHY Address %d is out of range\n", offset);
326 return -E1000_ERR_PARAM; 338 return -E1000_ERR_PARAM;
327 } 339 }
328 340
@@ -349,11 +361,11 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
349 break; 361 break;
350 } 362 }
351 if (!(i2ccmd & E1000_I2CCMD_READY)) { 363 if (!(i2ccmd & E1000_I2CCMD_READY)) {
352 hw_dbg(hw, "I2CCMD Write did not complete\n"); 364 hw_dbg("I2CCMD Write did not complete\n");
353 return -E1000_ERR_PHY; 365 return -E1000_ERR_PHY;
354 } 366 }
355 if (i2ccmd & E1000_I2CCMD_ERROR) { 367 if (i2ccmd & E1000_I2CCMD_ERROR) {
356 hw_dbg(hw, "I2CCMD Error bit set\n"); 368 hw_dbg("I2CCMD Error bit set\n");
357 return -E1000_ERR_PHY; 369 return -E1000_ERR_PHY;
358 } 370 }
359 371
@@ -361,10 +373,10 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
361} 373}
362 374
363/** 375/**
364 * e1000_get_phy_id_82575 - Retreive PHY addr and id 376 * igb_get_phy_id_82575 - Retrieve PHY addr and id
365 * @hw: pointer to the HW structure 377 * @hw: pointer to the HW structure
366 * 378 *
367 * Retreives the PHY address and ID for both PHY's which do and do not use 379 * Retrieves the PHY address and ID for both PHY's which do and do not use
368 * sgmi interface. 380 * sgmi interface.
369 **/ 381 **/
370static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 382static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
@@ -393,9 +405,8 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
393 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 405 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
394 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 406 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
395 if (ret_val == 0) { 407 if (ret_val == 0) {
396 hw_dbg(hw, "Vendor ID 0x%08X read at address %u\n", 408 hw_dbg("Vendor ID 0x%08X read at address %u\n",
397 phy_id, 409 phy_id, phy->addr);
398 phy->addr);
399 /* 410 /*
400 * At the time of this writing, The M88 part is 411 * At the time of this writing, The M88 part is
401 * the only supported SGMII PHY product. 412 * the only supported SGMII PHY product.
@@ -403,8 +414,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
403 if (phy_id == M88_VENDOR) 414 if (phy_id == M88_VENDOR)
404 break; 415 break;
405 } else { 416 } else {
406 hw_dbg(hw, "PHY address %u was unreadable\n", 417 hw_dbg("PHY address %u was unreadable\n", phy->addr);
407 phy->addr);
408 } 418 }
409 } 419 }
410 420
@@ -422,7 +432,7 @@ out:
422} 432}
423 433
424/** 434/**
425 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 435 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
426 * @hw: pointer to the HW structure 436 * @hw: pointer to the HW structure
427 * 437 *
428 * Resets the PHY using the serial gigabit media independent interface. 438 * Resets the PHY using the serial gigabit media independent interface.
@@ -436,7 +446,7 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
436 * available to us at this time. 446 * available to us at this time.
437 */ 447 */
438 448
439 hw_dbg(hw, "Soft resetting SGMII attached PHY...\n"); 449 hw_dbg("Soft resetting SGMII attached PHY...\n");
440 450
441 /* 451 /*
442 * SFP documentation requires the following to configure the SPF module 452 * SFP documentation requires the following to configure the SPF module
@@ -453,7 +463,7 @@ out:
453} 463}
454 464
455/** 465/**
456 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 466 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
457 * @hw: pointer to the HW structure 467 * @hw: pointer to the HW structure
458 * @active: true to enable LPLU, false to disable 468 * @active: true to enable LPLU, false to disable
459 * 469 *
@@ -471,34 +481,29 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
471 s32 ret_val; 481 s32 ret_val;
472 u16 data; 482 u16 data;
473 483
474 ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 484 ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
475 &data);
476 if (ret_val) 485 if (ret_val)
477 goto out; 486 goto out;
478 487
479 if (active) { 488 if (active) {
480 data |= IGP02E1000_PM_D0_LPLU; 489 data |= IGP02E1000_PM_D0_LPLU;
481 ret_val = hw->phy.ops.write_phy_reg(hw, 490 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
482 IGP02E1000_PHY_POWER_MGMT, 491 data);
483 data);
484 if (ret_val) 492 if (ret_val)
485 goto out; 493 goto out;
486 494
487 /* When LPLU is enabled, we should disable SmartSpeed */ 495 /* When LPLU is enabled, we should disable SmartSpeed */
488 ret_val = hw->phy.ops.read_phy_reg(hw, 496 ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
489 IGP01E1000_PHY_PORT_CONFIG, 497 &data);
490 &data);
491 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 498 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
492 ret_val = hw->phy.ops.write_phy_reg(hw, 499 ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
493 IGP01E1000_PHY_PORT_CONFIG, 500 data);
494 data);
495 if (ret_val) 501 if (ret_val)
496 goto out; 502 goto out;
497 } else { 503 } else {
498 data &= ~IGP02E1000_PM_D0_LPLU; 504 data &= ~IGP02E1000_PM_D0_LPLU;
499 ret_val = hw->phy.ops.write_phy_reg(hw, 505 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
500 IGP02E1000_PHY_POWER_MGMT, 506 data);
501 data);
502 /* 507 /*
503 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 508 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
504 * during Dx states where the power conservation is most 509 * during Dx states where the power conservation is most
@@ -506,29 +511,25 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
506 * SmartSpeed, so performance is maintained. 511 * SmartSpeed, so performance is maintained.
507 */ 512 */
508 if (phy->smart_speed == e1000_smart_speed_on) { 513 if (phy->smart_speed == e1000_smart_speed_on) {
509 ret_val = hw->phy.ops.read_phy_reg(hw, 514 ret_val = phy->ops.read_phy_reg(hw,
510 IGP01E1000_PHY_PORT_CONFIG, 515 IGP01E1000_PHY_PORT_CONFIG, &data);
511 &data);
512 if (ret_val) 516 if (ret_val)
513 goto out; 517 goto out;
514 518
515 data |= IGP01E1000_PSCFR_SMART_SPEED; 519 data |= IGP01E1000_PSCFR_SMART_SPEED;
516 ret_val = hw->phy.ops.write_phy_reg(hw, 520 ret_val = phy->ops.write_phy_reg(hw,
517 IGP01E1000_PHY_PORT_CONFIG, 521 IGP01E1000_PHY_PORT_CONFIG, data);
518 data);
519 if (ret_val) 522 if (ret_val)
520 goto out; 523 goto out;
521 } else if (phy->smart_speed == e1000_smart_speed_off) { 524 } else if (phy->smart_speed == e1000_smart_speed_off) {
522 ret_val = hw->phy.ops.read_phy_reg(hw, 525 ret_val = phy->ops.read_phy_reg(hw,
523 IGP01E1000_PHY_PORT_CONFIG, 526 IGP01E1000_PHY_PORT_CONFIG, &data);
524 &data);
525 if (ret_val) 527 if (ret_val)
526 goto out; 528 goto out;
527 529
528 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 530 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
529 ret_val = hw->phy.ops.write_phy_reg(hw, 531 ret_val = phy->ops.write_phy_reg(hw,
530 IGP01E1000_PHY_PORT_CONFIG, 532 IGP01E1000_PHY_PORT_CONFIG, data);
531 data);
532 if (ret_val) 533 if (ret_val)
533 goto out; 534 goto out;
534 } 535 }
@@ -539,10 +540,10 @@ out:
539} 540}
540 541
541/** 542/**
542 * e1000_acquire_nvm_82575 - Request for access to EEPROM 543 * igb_acquire_nvm_82575 - Request for access to EEPROM
543 * @hw: pointer to the HW structure 544 * @hw: pointer to the HW structure
544 * 545 *
545 * Acquire the necessary semaphores for exclussive access to the EEPROM. 546 * Acquire the necessary semaphores for exclusive access to the EEPROM.
546 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 547 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
547 * Return successful if access grant bit set, else clear the request for 548 * Return successful if access grant bit set, else clear the request for
548 * EEPROM access and return -E1000_ERR_NVM (-1). 549 * EEPROM access and return -E1000_ERR_NVM (-1).
@@ -565,7 +566,7 @@ out:
565} 566}
566 567
567/** 568/**
568 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 569 * igb_release_nvm_82575 - Release exclusive access to EEPROM
569 * @hw: pointer to the HW structure 570 * @hw: pointer to the HW structure
570 * 571 *
571 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 572 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
@@ -578,7 +579,7 @@ static void igb_release_nvm_82575(struct e1000_hw *hw)
578} 579}
579 580
580/** 581/**
581 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 582 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
582 * @hw: pointer to the HW structure 583 * @hw: pointer to the HW structure
583 * @mask: specifies which semaphore to acquire 584 * @mask: specifies which semaphore to acquire
584 * 585 *
@@ -613,7 +614,7 @@ static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
613 } 614 }
614 615
615 if (i == timeout) { 616 if (i == timeout) {
616 hw_dbg(hw, "Can't access resource, SW_FW_SYNC timeout.\n"); 617 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
617 ret_val = -E1000_ERR_SWFW_SYNC; 618 ret_val = -E1000_ERR_SWFW_SYNC;
618 goto out; 619 goto out;
619 } 620 }
@@ -628,7 +629,7 @@ out:
628} 629}
629 630
630/** 631/**
631 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 632 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
632 * @hw: pointer to the HW structure 633 * @hw: pointer to the HW structure
633 * @mask: specifies which semaphore to acquire 634 * @mask: specifies which semaphore to acquire
634 * 635 *
@@ -650,7 +651,7 @@ static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
650} 651}
651 652
652/** 653/**
653 * e1000_get_cfg_done_82575 - Read config done bit 654 * igb_get_cfg_done_82575 - Read config done bit
654 * @hw: pointer to the HW structure 655 * @hw: pointer to the HW structure
655 * 656 *
656 * Read the management control register for the config done bit for 657 * Read the management control register for the config done bit for
@@ -675,7 +676,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
675 timeout--; 676 timeout--;
676 } 677 }
677 if (!timeout) 678 if (!timeout)
678 hw_dbg(hw, "MNG configuration cycle has not completed.\n"); 679 hw_dbg("MNG configuration cycle has not completed.\n");
679 680
680 /* If EEPROM is not marked present, init the PHY manually */ 681 /* If EEPROM is not marked present, init the PHY manually */
681 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 682 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
@@ -686,7 +687,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
686} 687}
687 688
688/** 689/**
689 * e1000_check_for_link_82575 - Check for link 690 * igb_check_for_link_82575 - Check for link
690 * @hw: pointer to the HW structure 691 * @hw: pointer to the HW structure
691 * 692 *
692 * If sgmii is enabled, then use the pcs register to determine link, otherwise 693 * If sgmii is enabled, then use the pcs register to determine link, otherwise
@@ -701,20 +702,19 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw)
701 if ((hw->phy.media_type != e1000_media_type_copper) || 702 if ((hw->phy.media_type != e1000_media_type_copper) ||
702 (igb_sgmii_active_82575(hw))) 703 (igb_sgmii_active_82575(hw)))
703 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 704 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
704 &duplex); 705 &duplex);
705 else 706 else
706 ret_val = igb_check_for_copper_link(hw); 707 ret_val = igb_check_for_copper_link(hw);
707 708
708 return ret_val; 709 return ret_val;
709} 710}
710
711/** 711/**
712 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 712 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
713 * @hw: pointer to the HW structure 713 * @hw: pointer to the HW structure
714 * @speed: stores the current speed 714 * @speed: stores the current speed
715 * @duplex: stores the current duplex 715 * @duplex: stores the current duplex
716 * 716 *
717 * Using the physical coding sub-layer (PCS), retreive the current speed and 717 * Using the physical coding sub-layer (PCS), retrieve the current speed and
718 * duplex, then store the values in the pointers provided. 718 * duplex, then store the values in the pointers provided.
719 **/ 719 **/
720static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 720static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
@@ -764,24 +764,135 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
764} 764}
765 765
766/** 766/**
767 * e1000_rar_set_82575 - Set receive address register 767 * igb_init_rx_addrs_82575 - Initialize receive address's
768 * @hw: pointer to the HW structure 768 * @hw: pointer to the HW structure
769 * @addr: pointer to the receive address 769 * @rar_count: receive address registers
770 * @index: receive address array register
771 * 770 *
772 * Sets the receive address array register at index to the address passed 771 * Setups the receive address registers by setting the base receive address
773 * in by addr. 772 * register to the devices MAC address and clearing all the other receive
773 * address registers to 0.
774 **/ 774 **/
775static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index) 775static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
776{ 776{
777 if (index < E1000_RAR_ENTRIES_82575) 777 u32 i;
778 igb_rar_set(hw, addr, index); 778 u8 addr[6] = {0,0,0,0,0,0};
779 /*
780 * This function is essentially the same as that of
781 * e1000_init_rx_addrs_generic. However it also takes care
782 * of the special case where the register offset of the
783 * second set of RARs begins elsewhere. This is implicitly taken care by
784 * function e1000_rar_set_generic.
785 */
786
787 hw_dbg("e1000_init_rx_addrs_82575");
788
789 /* Setup the receive address */
790 hw_dbg("Programming MAC Address into RAR[0]\n");
791 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
792
793 /* Zero out the other (rar_entry_count - 1) receive addresses */
794 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
795 for (i = 1; i < rar_count; i++)
796 hw->mac.ops.rar_set(hw, addr, i);
797}
798
799/**
800 * igb_update_mc_addr_list_82575 - Update Multicast addresses
801 * @hw: pointer to the HW structure
802 * @mc_addr_list: array of multicast addresses to program
803 * @mc_addr_count: number of multicast addresses to program
804 * @rar_used_count: the first RAR register free to program
805 * @rar_count: total number of supported Receive Address Registers
806 *
807 * Updates the Receive Address Registers and Multicast Table Array.
808 * The caller must have a packed mc_addr_list of multicast addresses.
809 * The parameter rar_count will usually be hw->mac.rar_entry_count
810 * unless there are workarounds that change this.
811 **/
812void igb_update_mc_addr_list_82575(struct e1000_hw *hw,
813 u8 *mc_addr_list, u32 mc_addr_count,
814 u32 rar_used_count, u32 rar_count)
815{
816 u32 hash_value;
817 u32 i;
818 u8 addr[6] = {0,0,0,0,0,0};
819 /*
820 * This function is essentially the same as that of
821 * igb_update_mc_addr_list_generic. However it also takes care
822 * of the special case where the register offset of the
823 * second set of RARs begins elsewhere. This is implicitly taken care by
824 * function e1000_rar_set_generic.
825 */
826
827 /*
828 * Load the first set of multicast addresses into the exact
829 * filters (RAR). If there are not enough to fill the RAR
830 * array, clear the filters.
831 */
832 for (i = rar_used_count; i < rar_count; i++) {
833 if (mc_addr_count) {
834 igb_rar_set(hw, mc_addr_list, i);
835 mc_addr_count--;
836 mc_addr_list += ETH_ALEN;
837 } else {
838 igb_rar_set(hw, addr, i);
839 }
840 }
841
842 /* Clear the old settings from the MTA */
843 hw_dbg("Clearing MTA\n");
844 for (i = 0; i < hw->mac.mta_reg_count; i++) {
845 array_wr32(E1000_MTA, i, 0);
846 wrfl();
847 }
848
849 /* Load any remaining multicast addresses into the hash table. */
850 for (; mc_addr_count > 0; mc_addr_count--) {
851 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
852 hw_dbg("Hash value = 0x%03X\n", hash_value);
853 hw->mac.ops.mta_set(hw, hash_value);
854 mc_addr_list += ETH_ALEN;
855 }
856}
857
858/**
859 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
860 * @hw: pointer to the HW structure
861 *
862 * In the case of fiber serdes, shut down optics and PCS on driver unload
863 * when management pass thru is not enabled.
864 **/
865void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
866{
867 u32 reg;
868
869 if (hw->mac.type != e1000_82576 ||
870 (hw->phy.media_type != e1000_media_type_fiber &&
871 hw->phy.media_type != e1000_media_type_internal_serdes))
872 return;
873
874 /* if the management interface is not enabled, then power down */
875 if (!igb_enable_mng_pass_thru(hw)) {
876 /* Disable PCS to turn off link */
877 reg = rd32(E1000_PCS_CFG0);
878 reg &= ~E1000_PCS_CFG_PCS_EN;
879 wr32(E1000_PCS_CFG0, reg);
880
881 /* shutdown the laser */
882 reg = rd32(E1000_CTRL_EXT);
883 reg |= E1000_CTRL_EXT_SDP7_DATA;
884 wr32(E1000_CTRL_EXT, reg);
885
886 /* flush the write to verify completion */
887 wrfl();
888 msleep(1);
889 }
779 890
780 return; 891 return;
781} 892}
782 893
783/** 894/**
784 * e1000_reset_hw_82575 - Reset hardware 895 * igb_reset_hw_82575 - Reset hardware
785 * @hw: pointer to the HW structure 896 * @hw: pointer to the HW structure
786 * 897 *
787 * This resets the hardware into a known state. This is a 898 * This resets the hardware into a known state. This is a
@@ -798,9 +909,9 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
798 */ 909 */
799 ret_val = igb_disable_pcie_master(hw); 910 ret_val = igb_disable_pcie_master(hw);
800 if (ret_val) 911 if (ret_val)
801 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); 912 hw_dbg("PCI-E Master disable polling has failed.\n");
802 913
803 hw_dbg(hw, "Masking off all interrupts\n"); 914 hw_dbg("Masking off all interrupts\n");
804 wr32(E1000_IMC, 0xffffffff); 915 wr32(E1000_IMC, 0xffffffff);
805 916
806 wr32(E1000_RCTL, 0); 917 wr32(E1000_RCTL, 0);
@@ -811,7 +922,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
811 922
812 ctrl = rd32(E1000_CTRL); 923 ctrl = rd32(E1000_CTRL);
813 924
814 hw_dbg(hw, "Issuing a global reset to MAC\n"); 925 hw_dbg("Issuing a global reset to MAC\n");
815 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 926 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
816 927
817 ret_val = igb_get_auto_rd_done(hw); 928 ret_val = igb_get_auto_rd_done(hw);
@@ -821,7 +932,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
821 * return with an error. This can happen in situations 932 * return with an error. This can happen in situations
822 * where there is no eeprom and prevents getting link. 933 * where there is no eeprom and prevents getting link.
823 */ 934 */
824 hw_dbg(hw, "Auto Read Done did not complete\n"); 935 hw_dbg("Auto Read Done did not complete\n");
825 } 936 }
826 937
827 /* If EEPROM is not present, run manual init scripts */ 938 /* If EEPROM is not present, run manual init scripts */
@@ -838,7 +949,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
838} 949}
839 950
840/** 951/**
841 * e1000_init_hw_82575 - Initialize hardware 952 * igb_init_hw_82575 - Initialize hardware
842 * @hw: pointer to the HW structure 953 * @hw: pointer to the HW structure
843 * 954 *
844 * This inits the hardware readying it for operation. 955 * This inits the hardware readying it for operation.
@@ -852,18 +963,18 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
852 /* Initialize identification LED */ 963 /* Initialize identification LED */
853 ret_val = igb_id_led_init(hw); 964 ret_val = igb_id_led_init(hw);
854 if (ret_val) { 965 if (ret_val) {
855 hw_dbg(hw, "Error initializing identification LED\n"); 966 hw_dbg("Error initializing identification LED\n");
856 /* This is not fatal and we should not stop init due to this */ 967 /* This is not fatal and we should not stop init due to this */
857 } 968 }
858 969
859 /* Disabling VLAN filtering */ 970 /* Disabling VLAN filtering */
860 hw_dbg(hw, "Initializing the IEEE VLAN\n"); 971 hw_dbg("Initializing the IEEE VLAN\n");
861 igb_clear_vfta(hw); 972 igb_clear_vfta(hw);
862 973
863 /* Setup the receive address */ 974 /* Setup the receive address */
864 igb_init_rx_addrs(hw, rar_count); 975 igb_init_rx_addrs_82575(hw, rar_count);
865 /* Zero out the Multicast HASH table */ 976 /* Zero out the Multicast HASH table */
866 hw_dbg(hw, "Zeroing the MTA\n"); 977 hw_dbg("Zeroing the MTA\n");
867 for (i = 0; i < mac->mta_reg_count; i++) 978 for (i = 0; i < mac->mta_reg_count; i++)
868 array_wr32(E1000_MTA, i, 0); 979 array_wr32(E1000_MTA, i, 0);
869 980
@@ -882,7 +993,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
882} 993}
883 994
884/** 995/**
885 * e1000_setup_copper_link_82575 - Configure copper link settings 996 * igb_setup_copper_link_82575 - Configure copper link settings
886 * @hw: pointer to the HW structure 997 * @hw: pointer to the HW structure
887 * 998 *
888 * Configures the link for auto-neg or forced speed and duplex. Then we check 999 * Configures the link for auto-neg or forced speed and duplex. Then we check
@@ -933,10 +1044,10 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
933 * PHY will be set to 10H, 10F, 100H or 100F 1044 * PHY will be set to 10H, 10F, 100H or 100F
934 * depending on user settings. 1045 * depending on user settings.
935 */ 1046 */
936 hw_dbg(hw, "Forcing Speed and Duplex\n"); 1047 hw_dbg("Forcing Speed and Duplex\n");
937 ret_val = igb_phy_force_speed_duplex(hw); 1048 ret_val = igb_phy_force_speed_duplex(hw);
938 if (ret_val) { 1049 if (ret_val) {
939 hw_dbg(hw, "Error Forcing Speed and Duplex\n"); 1050 hw_dbg("Error Forcing Speed and Duplex\n");
940 goto out; 1051 goto out;
941 } 1052 }
942 } 1053 }
@@ -949,20 +1060,17 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
949 * Check link status. Wait up to 100 microseconds for link to become 1060 * Check link status. Wait up to 100 microseconds for link to become
950 * valid. 1061 * valid.
951 */ 1062 */
952 ret_val = igb_phy_has_link(hw, 1063 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
953 COPPER_LINK_UP_LIMIT,
954 10,
955 &link);
956 if (ret_val) 1064 if (ret_val)
957 goto out; 1065 goto out;
958 1066
959 if (link) { 1067 if (link) {
960 hw_dbg(hw, "Valid link established!!!\n"); 1068 hw_dbg("Valid link established!!!\n");
961 /* Config the MAC and PHY after link is up */ 1069 /* Config the MAC and PHY after link is up */
962 igb_config_collision_dist(hw); 1070 igb_config_collision_dist(hw);
963 ret_val = igb_config_fc_after_link_up(hw); 1071 ret_val = igb_config_fc_after_link_up(hw);
964 } else { 1072 } else {
965 hw_dbg(hw, "Unable to establish link!!!\n"); 1073 hw_dbg("Unable to establish link!!!\n");
966 } 1074 }
967 1075
968out: 1076out:
@@ -970,7 +1078,7 @@ out:
970} 1078}
971 1079
972/** 1080/**
973 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1081 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
974 * @hw: pointer to the HW structure 1082 * @hw: pointer to the HW structure
975 * 1083 *
976 * Configures speed and duplex for fiber and serdes links. 1084 * Configures speed and duplex for fiber and serdes links.
@@ -1018,7 +1126,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1018 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1126 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1019 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1127 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1020 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1128 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1021 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1129 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1022 } else { 1130 } else {
1023 /* Set PCS register for forced speed */ 1131 /* Set PCS register for forced speed */
1024 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1132 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
@@ -1026,7 +1134,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1026 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1134 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1027 E1000_PCS_LCTL_FSD | /* Force Speed */ 1135 E1000_PCS_LCTL_FSD | /* Force Speed */
1028 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1136 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1029 hw_dbg(hw, "Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1137 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1030 } 1138 }
1031 wr32(E1000_PCS_LCTL, reg); 1139 wr32(E1000_PCS_LCTL, reg);
1032 1140
@@ -1034,7 +1142,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1034} 1142}
1035 1143
1036/** 1144/**
1037 * e1000_configure_pcs_link_82575 - Configure PCS link 1145 * igb_configure_pcs_link_82575 - Configure PCS link
1038 * @hw: pointer to the HW structure 1146 * @hw: pointer to the HW structure
1039 * 1147 *
1040 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1148 * Configure the physical coding sub-layer (PCS) link. The PCS link is
@@ -1067,7 +1175,7 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1067 */ 1175 */
1068 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1176 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1069 } else { 1177 } else {
1070 /* Set PCS regiseter for forced speed */ 1178 /* Set PCS register for forced speed */
1071 1179
1072 /* Turn off bits for full duplex, speed, and autoneg */ 1180 /* Turn off bits for full duplex, speed, and autoneg */
1073 reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1181 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
@@ -1088,8 +1196,7 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1088 E1000_PCS_LCTL_FORCE_LINK | 1196 E1000_PCS_LCTL_FORCE_LINK |
1089 E1000_PCS_LCTL_FLV_LINK_UP; 1197 E1000_PCS_LCTL_FLV_LINK_UP;
1090 1198
1091 hw_dbg(hw, 1199 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1092 "Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1093 reg); 1200 reg);
1094 } 1201 }
1095 wr32(E1000_PCS_LCTL, reg); 1202 wr32(E1000_PCS_LCTL, reg);
@@ -1099,7 +1206,7 @@ out:
1099} 1206}
1100 1207
1101/** 1208/**
1102 * e1000_sgmii_active_82575 - Return sgmii state 1209 * igb_sgmii_active_82575 - Return sgmii state
1103 * @hw: pointer to the HW structure 1210 * @hw: pointer to the HW structure
1104 * 1211 *
1105 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1212 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
@@ -1125,7 +1232,71 @@ out:
1125} 1232}
1126 1233
1127/** 1234/**
1128 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1235 * igb_translate_register_82576 - Translate the proper register offset
1236 * @reg: e1000 register to be read
1237 *
1238 * Registers in 82576 are located in different offsets than other adapters
1239 * even though they function in the same manner. This function takes in
1240 * the name of the register to read and returns the correct offset for
1241 * 82576 silicon.
1242 **/
1243u32 igb_translate_register_82576(u32 reg)
1244{
1245 /*
1246 * Some of the Kawela registers are located at different
1247 * offsets than they are in older adapters.
1248 * Despite the difference in location, the registers
1249 * function in the same manner.
1250 */
1251 switch (reg) {
1252 case E1000_TDBAL(0):
1253 reg = 0x0E000;
1254 break;
1255 case E1000_TDBAH(0):
1256 reg = 0x0E004;
1257 break;
1258 case E1000_TDLEN(0):
1259 reg = 0x0E008;
1260 break;
1261 case E1000_TDH(0):
1262 reg = 0x0E010;
1263 break;
1264 case E1000_TDT(0):
1265 reg = 0x0E018;
1266 break;
1267 case E1000_TXDCTL(0):
1268 reg = 0x0E028;
1269 break;
1270 case E1000_RDBAL(0):
1271 reg = 0x0C000;
1272 break;
1273 case E1000_RDBAH(0):
1274 reg = 0x0C004;
1275 break;
1276 case E1000_RDLEN(0):
1277 reg = 0x0C008;
1278 break;
1279 case E1000_RDH(0):
1280 reg = 0x0C010;
1281 break;
1282 case E1000_RDT(0):
1283 reg = 0x0C018;
1284 break;
1285 case E1000_RXDCTL(0):
1286 reg = 0x0C028;
1287 break;
1288 case E1000_SRRCTL(0):
1289 reg = 0x0C00C;
1290 break;
1291 default:
1292 break;
1293 }
1294
1295 return reg;
1296}
1297
1298/**
1299 * igb_reset_init_script_82575 - Inits HW defaults after reset
1129 * @hw: pointer to the HW structure 1300 * @hw: pointer to the HW structure
1130 * 1301 *
1131 * Inits recommended HW defaults after a reset when there is no EEPROM 1302 * Inits recommended HW defaults after a reset when there is no EEPROM
@@ -1134,7 +1305,7 @@ out:
1134static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1305static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1135{ 1306{
1136 if (hw->mac.type == e1000_82575) { 1307 if (hw->mac.type == e1000_82575) {
1137 hw_dbg(hw, "Running reset init script for 82575\n"); 1308 hw_dbg("Running reset init script for 82575\n");
1138 /* SerDes configuration via SERDESCTRL */ 1309 /* SerDes configuration via SERDESCTRL */
1139 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1310 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1140 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1311 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
@@ -1161,7 +1332,7 @@ static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1161} 1332}
1162 1333
1163/** 1334/**
1164 * e1000_read_mac_addr_82575 - Read device MAC address 1335 * igb_read_mac_addr_82575 - Read device MAC address
1165 * @hw: pointer to the HW structure 1336 * @hw: pointer to the HW structure
1166 **/ 1337 **/
1167static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1338static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
@@ -1175,7 +1346,7 @@ static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1175} 1346}
1176 1347
1177/** 1348/**
1178 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1349 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1179 * @hw: pointer to the HW structure 1350 * @hw: pointer to the HW structure
1180 * 1351 *
1181 * Clears the hardware counters by reading the counter registers. 1352 * Clears the hardware counters by reading the counter registers.
@@ -1238,11 +1409,84 @@ static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1238 temp = rd32(E1000_SCVPC); 1409 temp = rd32(E1000_SCVPC);
1239} 1410}
1240 1411
1412/**
1413 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1414 * @hw: pointer to the HW structure
1415 *
1416 * After rx enable if managability is enabled then there is likely some
1417 * bad data at the start of the fifo and possibly in the DMA fifo. This
1418 * function clears the fifos and flushes any packets that came in as rx was
1419 * being enabled.
1420 **/
1421void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1422{
1423 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1424 int i, ms_wait;
1425
1426 if (hw->mac.type != e1000_82575 ||
1427 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1428 return;
1429
1430 /* Disable all RX queues */
1431 for (i = 0; i < 4; i++) {
1432 rxdctl[i] = rd32(E1000_RXDCTL(i));
1433 wr32(E1000_RXDCTL(i),
1434 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1435 }
1436 /* Poll all queues to verify they have shut down */
1437 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1438 msleep(1);
1439 rx_enabled = 0;
1440 for (i = 0; i < 4; i++)
1441 rx_enabled |= rd32(E1000_RXDCTL(i));
1442 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1443 break;
1444 }
1445
1446 if (ms_wait == 10)
1447 hw_dbg("Queue disable timed out after 10ms\n");
1448
1449 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1450 * incoming packets are rejected. Set enable and wait 2ms so that
1451 * any packet that was coming in as RCTL.EN was set is flushed
1452 */
1453 rfctl = rd32(E1000_RFCTL);
1454 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1455
1456 rlpml = rd32(E1000_RLPML);
1457 wr32(E1000_RLPML, 0);
1458
1459 rctl = rd32(E1000_RCTL);
1460 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1461 temp_rctl |= E1000_RCTL_LPE;
1462
1463 wr32(E1000_RCTL, temp_rctl);
1464 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1465 wrfl();
1466 msleep(2);
1467
1468 /* Enable RX queues that were previously enabled and restore our
1469 * previous state
1470 */
1471 for (i = 0; i < 4; i++)
1472 wr32(E1000_RXDCTL(i), rxdctl[i]);
1473 wr32(E1000_RCTL, rctl);
1474 wrfl();
1475
1476 wr32(E1000_RLPML, rlpml);
1477 wr32(E1000_RFCTL, rfctl);
1478
1479 /* Flush receive errors generated by workaround */
1480 rd32(E1000_ROC);
1481 rd32(E1000_RNBC);
1482 rd32(E1000_MPC);
1483}
1484
1241static struct e1000_mac_operations e1000_mac_ops_82575 = { 1485static struct e1000_mac_operations e1000_mac_ops_82575 = {
1242 .reset_hw = igb_reset_hw_82575, 1486 .reset_hw = igb_reset_hw_82575,
1243 .init_hw = igb_init_hw_82575, 1487 .init_hw = igb_init_hw_82575,
1244 .check_for_link = igb_check_for_link_82575, 1488 .check_for_link = igb_check_for_link_82575,
1245 .rar_set = igb_rar_set_82575, 1489 .rar_set = igb_rar_set,
1246 .read_mac_addr = igb_read_mac_addr_82575, 1490 .read_mac_addr = igb_read_mac_addr_82575,
1247 .get_speed_and_duplex = igb_get_speed_and_duplex_copper, 1491 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1248}; 1492};
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index 76ea846663db..2f848e578a24 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation. 4 Copyright(c) 2007 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -28,7 +28,13 @@
28#ifndef _E1000_82575_H_ 28#ifndef _E1000_82575_H_
29#define _E1000_82575_H_ 29#define _E1000_82575_H_
30 30
31u32 igb_translate_register_82576(u32 reg);
32void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32);
33extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
34extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
35
31#define E1000_RAR_ENTRIES_82575 16 36#define E1000_RAR_ENTRIES_82575 16
37#define E1000_RAR_ENTRIES_82576 24
32 38
33/* SRRCTL bit definitions */ 39/* SRRCTL bit definitions */
34#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 40#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
@@ -56,7 +62,7 @@
56#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 62#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
57#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 63#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
58 64
59/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */ 65/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
60 66
61/* Receive Descriptor - Advanced */ 67/* Receive Descriptor - Advanced */
62union e1000_adv_rx_desc { 68union e1000_adv_rx_desc {
@@ -93,6 +99,8 @@ union e1000_adv_rx_desc {
93/* RSS Hash results */ 99/* RSS Hash results */
94 100
95/* RSS Packet Types as indicated in the receive descriptor */ 101/* RSS Packet Types as indicated in the receive descriptor */
102#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
103#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
96 104
97/* Transmit Descriptor - Advanced */ 105/* Transmit Descriptor - Advanced */
98union e1000_adv_tx_desc { 106union e1000_adv_tx_desc {
@@ -142,9 +150,25 @@ struct e1000_adv_tx_context_desc {
142#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 150#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
143 151
144/* Direct Cache Access (DCA) definitions */ 152/* Direct Cache Access (DCA) definitions */
145 153#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
146 154#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
147 155
148#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */ 156#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
157#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
158
159#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
160#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
161#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
162#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
163
164#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
165#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
166#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
167
168/* Additional DCA related definitions, note change in position of CPUID */
169#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
170#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
171#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
172#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
149 173
150#endif 174#endif
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 8da9ffedc425..afdba3c9073c 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel(R) Gigabit Ethernet Linux driver 3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation. 4 Copyright(c) 2007 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -90,13 +90,18 @@
90#define E1000_I2CCMD_ERROR 0x80000000 90#define E1000_I2CCMD_ERROR 0x80000000
91#define E1000_MAX_SGMII_PHY_REG_ADDR 255 91#define E1000_MAX_SGMII_PHY_REG_ADDR 255
92#define E1000_I2CCMD_PHY_TIMEOUT 200 92#define E1000_I2CCMD_PHY_TIMEOUT 200
93#define E1000_IVAR_VALID 0x80
94#define E1000_GPIE_NSICR 0x00000001
95#define E1000_GPIE_MSIX_MODE 0x00000010
96#define E1000_GPIE_EIAME 0x40000000
97#define E1000_GPIE_PBA 0x80000000
93 98
94/* Receive Decriptor bit definitions */ 99/* Receive Descriptor bit definitions */
95#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 100#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
96#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 101#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
97#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 102#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
98#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 103#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
99#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 104#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
100#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 105#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
101#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 106#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
102#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 107#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
@@ -213,6 +218,7 @@
213/* Device Control */ 218/* Device Control */
214#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 219#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
215#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 220#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
221#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
216#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 222#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 223#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
218#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 224#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
@@ -244,6 +250,7 @@
244 */ 250 */
245 251
246#define E1000_CONNSW_ENRGSRC 0x4 252#define E1000_CONNSW_ENRGSRC 0x4
253#define E1000_PCS_CFG_PCS_EN 8
247#define E1000_PCS_LCTL_FLV_LINK_UP 1 254#define E1000_PCS_LCTL_FLV_LINK_UP 1
248#define E1000_PCS_LCTL_FSV_100 2 255#define E1000_PCS_LCTL_FSV_100 2
249#define E1000_PCS_LCTL_FSV_1000 4 256#define E1000_PCS_LCTL_FSV_1000 4
@@ -253,6 +260,7 @@
253#define E1000_PCS_LCTL_AN_ENABLE 0x10000 260#define E1000_PCS_LCTL_AN_ENABLE 0x10000
254#define E1000_PCS_LCTL_AN_RESTART 0x20000 261#define E1000_PCS_LCTL_AN_RESTART 0x20000
255#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 262#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
263#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
256 264
257#define E1000_PCS_LSTS_LINK_OK 1 265#define E1000_PCS_LSTS_LINK_OK 1
258#define E1000_PCS_LSTS_SPEED_100 2 266#define E1000_PCS_LSTS_SPEED_100 2
@@ -340,6 +348,7 @@
340#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 348#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
341 349
342/* Header split receive */ 350/* Header split receive */
351#define E1000_RFCTL_LEF 0x00040000
343 352
344/* Collision related configuration parameters */ 353/* Collision related configuration parameters */
345#define E1000_COLLISION_THRESHOLD 15 354#define E1000_COLLISION_THRESHOLD 15
@@ -359,6 +368,7 @@
359#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 368#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
360#define E1000_PBA_24K 0x0018 369#define E1000_PBA_24K 0x0018
361#define E1000_PBA_34K 0x0022 370#define E1000_PBA_34K 0x0022
371#define E1000_PBA_64K 0x0040 /* 64KB */
362 372
363#define IFS_MAX 80 373#define IFS_MAX 80
364#define IFS_MIN 40 374#define IFS_MIN 40
@@ -379,7 +389,7 @@
379#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 389#define E1000_ICR_RXO 0x00000040 /* rx overrun */
380#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 390#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
381#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 391#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
382#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 392#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
383#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 393#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
384#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 394#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
385#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 395#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
@@ -443,12 +453,6 @@
443#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 453#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
444#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 454#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
445#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 455#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
446/* queue 0 Rx descriptor FIFO parity error */
447/* queue 0 Tx descriptor FIFO parity error */
448/* host arb read buffer parity error */
449/* packet buffer parity error */
450/* queue 1 Rx descriptor FIFO parity error */
451/* queue 1 Tx descriptor FIFO parity error */
452 456
453/* Extended Interrupt Mask Set */ 457/* Extended Interrupt Mask Set */
454#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 458#define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
@@ -457,12 +461,6 @@
457/* Interrupt Cause Set */ 461/* Interrupt Cause Set */
458#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 462#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
459#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 463#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
460/* queue 0 Rx descriptor FIFO parity error */
461/* queue 0 Tx descriptor FIFO parity error */
462/* host arb read buffer parity error */
463/* packet buffer parity error */
464/* queue 1 Rx descriptor FIFO parity error */
465/* queue 1 Tx descriptor FIFO parity error */
466 464
467/* Extended Interrupt Cause Set */ 465/* Extended Interrupt Cause Set */
468 466
@@ -539,6 +537,7 @@
539/* PHY Control Register */ 537/* PHY Control Register */
540#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 538#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
541#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 539#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
540#define MII_CR_POWER_DOWN 0x0800 /* Power down */
542#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 541#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
543#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 542#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
544#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 543#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
@@ -567,7 +566,6 @@
567/* 1000BASE-T Control Register */ 566/* 1000BASE-T Control Register */
568#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 567#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
569#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 568#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
570 /* 0=DTE device */
571#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 569#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
572 /* 0=Configure PHY as Slave */ 570 /* 0=Configure PHY as Slave */
573#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 571#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
@@ -581,7 +579,7 @@
581/* PHY 1000 MII Register/Bit Definitions */ 579/* PHY 1000 MII Register/Bit Definitions */
582/* PHY Registers defined by IEEE */ 580/* PHY Registers defined by IEEE */
583#define PHY_CONTROL 0x00 /* Control Register */ 581#define PHY_CONTROL 0x00 /* Control Register */
584#define PHY_STATUS 0x01 /* Status Regiser */ 582#define PHY_STATUS 0x01 /* Status Register */
585#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 583#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
586#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 584#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
587#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 585#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
@@ -708,8 +706,8 @@
708/* Auto crossover enabled all speeds */ 706/* Auto crossover enabled all speeds */
709#define M88E1000_PSCR_AUTO_X_MODE 0x0060 707#define M88E1000_PSCR_AUTO_X_MODE 0x0060
710/* 708/*
711 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold 709 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
712 * 0=Normal 10BASE-T RX Threshold 710 * 0=Normal 10BASE-T Rx Threshold
713 */ 711 */
714/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 712/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
715#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 713#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h
index 7b2c70a3b8cc..19fa4ee96f2e 100644
--- a/drivers/net/igb/e1000_hw.h
+++ b/drivers/net/igb/e1000_hw.h
@@ -38,6 +38,10 @@
38 38
39struct e1000_hw; 39struct e1000_hw;
40 40
41#define E1000_DEV_ID_82576 0x10C9
42#define E1000_DEV_ID_82576_FIBER 0x10E6
43#define E1000_DEV_ID_82576_SERDES 0x10E7
44#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
41#define E1000_DEV_ID_82575EB_COPPER 0x10A7 45#define E1000_DEV_ID_82575EB_COPPER 0x10A7
42#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 46#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
43#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 47#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
@@ -50,6 +54,7 @@ struct e1000_hw;
50enum e1000_mac_type { 54enum e1000_mac_type {
51 e1000_undefined = 0, 55 e1000_undefined = 0,
52 e1000_82575, 56 e1000_82575,
57 e1000_82576,
53 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 58 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
54}; 59};
55 60
@@ -410,14 +415,17 @@ struct e1000_mac_operations {
410 s32 (*check_for_link)(struct e1000_hw *); 415 s32 (*check_for_link)(struct e1000_hw *);
411 s32 (*reset_hw)(struct e1000_hw *); 416 s32 (*reset_hw)(struct e1000_hw *);
412 s32 (*init_hw)(struct e1000_hw *); 417 s32 (*init_hw)(struct e1000_hw *);
418 bool (*check_mng_mode)(struct e1000_hw *);
413 s32 (*setup_physical_interface)(struct e1000_hw *); 419 s32 (*setup_physical_interface)(struct e1000_hw *);
414 void (*rar_set)(struct e1000_hw *, u8 *, u32); 420 void (*rar_set)(struct e1000_hw *, u8 *, u32);
415 s32 (*read_mac_addr)(struct e1000_hw *); 421 s32 (*read_mac_addr)(struct e1000_hw *);
416 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); 422 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
423 void (*mta_set)(struct e1000_hw *, u32);
417}; 424};
418 425
419struct e1000_phy_operations { 426struct e1000_phy_operations {
420 s32 (*acquire_phy)(struct e1000_hw *); 427 s32 (*acquire_phy)(struct e1000_hw *);
428 s32 (*check_reset_block)(struct e1000_hw *);
421 s32 (*force_speed_duplex)(struct e1000_hw *); 429 s32 (*force_speed_duplex)(struct e1000_hw *);
422 s32 (*get_cfg_done)(struct e1000_hw *hw); 430 s32 (*get_cfg_done)(struct e1000_hw *hw);
423 s32 (*get_cable_length)(struct e1000_hw *); 431 s32 (*get_cable_length)(struct e1000_hw *);
@@ -586,14 +594,10 @@ struct e1000_hw {
586 594
587#ifdef DEBUG 595#ifdef DEBUG
588extern char *igb_get_hw_dev_name(struct e1000_hw *hw); 596extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
589#define hw_dbg(hw, format, arg...) \ 597#define hw_dbg(format, arg...) \
590 printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg) 598 printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
591#else 599#else
592static inline int __attribute__ ((format (printf, 2, 3))) 600#define hw_dbg(format, arg...)
593hw_dbg(struct e1000_hw *hw, const char *format, ...)
594{
595 return 0;
596}
597#endif 601#endif
598 602
599#endif 603#endif
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index 3e84a3f0c1d8..20408aa1f916 100644
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -36,10 +36,9 @@
36 36
37static s32 igb_set_default_fc(struct e1000_hw *hw); 37static s32 igb_set_default_fc(struct e1000_hw *hw);
38static s32 igb_set_fc_watermarks(struct e1000_hw *hw); 38static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
39static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
40 39
41/** 40/**
42 * e1000_remove_device - Free device specific structure 41 * igb_remove_device - Free device specific structure
43 * @hw: pointer to the HW structure 42 * @hw: pointer to the HW structure
44 * 43 *
45 * If a device specific structure was allocated, this function will 44 * If a device specific structure was allocated, this function will
@@ -73,7 +72,7 @@ static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
73} 72}
74 73
75/** 74/**
76 * e1000_get_bus_info_pcie - Get PCIe bus information 75 * igb_get_bus_info_pcie - Get PCIe bus information
77 * @hw: pointer to the HW structure 76 * @hw: pointer to the HW structure
78 * 77 *
79 * Determines and stores the system bus information for a particular 78 * Determines and stores the system bus information for a particular
@@ -113,7 +112,7 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
113} 112}
114 113
115/** 114/**
116 * e1000_clear_vfta - Clear VLAN filter table 115 * igb_clear_vfta - Clear VLAN filter table
117 * @hw: pointer to the HW structure 116 * @hw: pointer to the HW structure
118 * 117 *
119 * Clears the register array which contains the VLAN filter table by 118 * Clears the register array which contains the VLAN filter table by
@@ -130,7 +129,7 @@ void igb_clear_vfta(struct e1000_hw *hw)
130} 129}
131 130
132/** 131/**
133 * e1000_write_vfta - Write value to VLAN filter table 132 * igb_write_vfta - Write value to VLAN filter table
134 * @hw: pointer to the HW structure 133 * @hw: pointer to the HW structure
135 * @offset: register offset in VLAN filter table 134 * @offset: register offset in VLAN filter table
136 * @value: register value written to VLAN filter table 135 * @value: register value written to VLAN filter table
@@ -145,7 +144,7 @@ void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
145} 144}
146 145
147/** 146/**
148 * e1000_init_rx_addrs - Initialize receive address's 147 * igb_init_rx_addrs - Initialize receive address's
149 * @hw: pointer to the HW structure 148 * @hw: pointer to the HW structure
150 * @rar_count: receive address registers 149 * @rar_count: receive address registers
151 * 150 *
@@ -158,12 +157,12 @@ void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
158 u32 i; 157 u32 i;
159 158
160 /* Setup the receive address */ 159 /* Setup the receive address */
161 hw_dbg(hw, "Programming MAC Address into RAR[0]\n"); 160 hw_dbg("Programming MAC Address into RAR[0]\n");
162 161
163 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 162 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
164 163
165 /* Zero out the other (rar_entry_count - 1) receive addresses */ 164 /* Zero out the other (rar_entry_count - 1) receive addresses */
166 hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1); 165 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
167 for (i = 1; i < rar_count; i++) { 166 for (i = 1; i < rar_count; i++) {
168 array_wr32(E1000_RA, (i << 1), 0); 167 array_wr32(E1000_RA, (i << 1), 0);
169 wrfl(); 168 wrfl();
@@ -173,7 +172,7 @@ void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
173} 172}
174 173
175/** 174/**
176 * e1000_check_alt_mac_addr - Check for alternate MAC addr 175 * igb_check_alt_mac_addr - Check for alternate MAC addr
177 * @hw: pointer to the HW structure 176 * @hw: pointer to the HW structure
178 * 177 *
179 * Checks the nvm for an alternate MAC address. An alternate MAC address 178 * Checks the nvm for an alternate MAC address. An alternate MAC address
@@ -193,7 +192,7 @@ s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
193 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 192 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
194 &nvm_alt_mac_addr_offset); 193 &nvm_alt_mac_addr_offset);
195 if (ret_val) { 194 if (ret_val) {
196 hw_dbg(hw, "NVM Read Error\n"); 195 hw_dbg("NVM Read Error\n");
197 goto out; 196 goto out;
198 } 197 }
199 198
@@ -209,7 +208,7 @@ s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
209 offset = nvm_alt_mac_addr_offset + (i >> 1); 208 offset = nvm_alt_mac_addr_offset + (i >> 1);
210 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); 209 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
211 if (ret_val) { 210 if (ret_val) {
212 hw_dbg(hw, "NVM Read Error\n"); 211 hw_dbg("NVM Read Error\n");
213 goto out; 212 goto out;
214 } 213 }
215 214
@@ -233,7 +232,7 @@ out:
233} 232}
234 233
235/** 234/**
236 * e1000_rar_set - Set receive address register 235 * igb_rar_set - Set receive address register
237 * @hw: pointer to the HW structure 236 * @hw: pointer to the HW structure
238 * @addr: pointer to the receive address 237 * @addr: pointer to the receive address
239 * @index: receive address array register 238 * @index: receive address array register
@@ -263,7 +262,7 @@ void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
263} 262}
264 263
265/** 264/**
266 * e1000_mta_set - Set multicast filter table address 265 * igb_mta_set - Set multicast filter table address
267 * @hw: pointer to the HW structure 266 * @hw: pointer to the HW structure
268 * @hash_value: determines the MTA register and bit to set 267 * @hash_value: determines the MTA register and bit to set
269 * 268 *
@@ -298,7 +297,7 @@ static void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
298} 297}
299 298
300/** 299/**
301 * e1000_update_mc_addr_list - Update Multicast addresses 300 * igb_update_mc_addr_list - Update Multicast addresses
302 * @hw: pointer to the HW structure 301 * @hw: pointer to the HW structure
303 * @mc_addr_list: array of multicast addresses to program 302 * @mc_addr_list: array of multicast addresses to program
304 * @mc_addr_count: number of multicast addresses to program 303 * @mc_addr_count: number of multicast addresses to program
@@ -336,7 +335,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
336 } 335 }
337 336
338 /* Clear the old settings from the MTA */ 337 /* Clear the old settings from the MTA */
339 hw_dbg(hw, "Clearing MTA\n"); 338 hw_dbg("Clearing MTA\n");
340 for (i = 0; i < hw->mac.mta_reg_count; i++) { 339 for (i = 0; i < hw->mac.mta_reg_count; i++) {
341 array_wr32(E1000_MTA, i, 0); 340 array_wr32(E1000_MTA, i, 0);
342 wrfl(); 341 wrfl();
@@ -345,14 +344,14 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
345 /* Load any remaining multicast addresses into the hash table. */ 344 /* Load any remaining multicast addresses into the hash table. */
346 for (; mc_addr_count > 0; mc_addr_count--) { 345 for (; mc_addr_count > 0; mc_addr_count--) {
347 hash_value = igb_hash_mc_addr(hw, mc_addr_list); 346 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
348 hw_dbg(hw, "Hash value = 0x%03X\n", hash_value); 347 hw_dbg("Hash value = 0x%03X\n", hash_value);
349 igb_mta_set(hw, hash_value); 348 igb_mta_set(hw, hash_value);
350 mc_addr_list += ETH_ALEN; 349 mc_addr_list += ETH_ALEN;
351 } 350 }
352} 351}
353 352
354/** 353/**
355 * e1000_hash_mc_addr - Generate a multicast hash value 354 * igb_hash_mc_addr - Generate a multicast hash value
356 * @hw: pointer to the HW structure 355 * @hw: pointer to the HW structure
357 * @mc_addr: pointer to a multicast address 356 * @mc_addr: pointer to a multicast address
358 * 357 *
@@ -360,7 +359,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
360 * the multicast filter table array address and new table value. See 359 * the multicast filter table array address and new table value. See
361 * igb_mta_set() 360 * igb_mta_set()
362 **/ 361 **/
363static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 362u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
364{ 363{
365 u32 hash_value, hash_mask; 364 u32 hash_value, hash_mask;
366 u8 bit_shift = 0; 365 u8 bit_shift = 0;
@@ -423,7 +422,7 @@ static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
423} 422}
424 423
425/** 424/**
426 * e1000_clear_hw_cntrs_base - Clear base hardware counters 425 * igb_clear_hw_cntrs_base - Clear base hardware counters
427 * @hw: pointer to the HW structure 426 * @hw: pointer to the HW structure
428 * 427 *
429 * Clears the base hardware counters by reading the counter registers. 428 * Clears the base hardware counters by reading the counter registers.
@@ -472,7 +471,7 @@ void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
472} 471}
473 472
474/** 473/**
475 * e1000_check_for_copper_link - Check for link (Copper) 474 * igb_check_for_copper_link - Check for link (Copper)
476 * @hw: pointer to the HW structure 475 * @hw: pointer to the HW structure
477 * 476 *
478 * Checks to see of the link status of the hardware has changed. If a 477 * Checks to see of the link status of the hardware has changed. If a
@@ -540,14 +539,14 @@ s32 igb_check_for_copper_link(struct e1000_hw *hw)
540 */ 539 */
541 ret_val = igb_config_fc_after_link_up(hw); 540 ret_val = igb_config_fc_after_link_up(hw);
542 if (ret_val) 541 if (ret_val)
543 hw_dbg(hw, "Error configuring flow control\n"); 542 hw_dbg("Error configuring flow control\n");
544 543
545out: 544out:
546 return ret_val; 545 return ret_val;
547} 546}
548 547
549/** 548/**
550 * e1000_setup_link - Setup flow control and link settings 549 * igb_setup_link - Setup flow control and link settings
551 * @hw: pointer to the HW structure 550 * @hw: pointer to the HW structure
552 * 551 *
553 * Determines which flow control settings to use, then configures flow 552 * Determines which flow control settings to use, then configures flow
@@ -578,7 +577,7 @@ s32 igb_setup_link(struct e1000_hw *hw)
578 */ 577 */
579 hw->fc.original_type = hw->fc.type; 578 hw->fc.original_type = hw->fc.type;
580 579
581 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type); 580 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type);
582 581
583 /* Call the necessary media_type subroutine to configure the link. */ 582 /* Call the necessary media_type subroutine to configure the link. */
584 ret_val = hw->mac.ops.setup_physical_interface(hw); 583 ret_val = hw->mac.ops.setup_physical_interface(hw);
@@ -591,8 +590,7 @@ s32 igb_setup_link(struct e1000_hw *hw)
591 * control is disabled, because it does not hurt anything to 590 * control is disabled, because it does not hurt anything to
592 * initialize these registers. 591 * initialize these registers.
593 */ 592 */
594 hw_dbg(hw, 593 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
595 "Initializing the Flow Control address, type and timer regs\n");
596 wr32(E1000_FCT, FLOW_CONTROL_TYPE); 594 wr32(E1000_FCT, FLOW_CONTROL_TYPE);
597 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 595 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
598 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 596 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
@@ -606,7 +604,7 @@ out:
606} 604}
607 605
608/** 606/**
609 * e1000_config_collision_dist - Configure collision distance 607 * igb_config_collision_dist - Configure collision distance
610 * @hw: pointer to the HW structure 608 * @hw: pointer to the HW structure
611 * 609 *
612 * Configures the collision distance to the default value and is used 610 * Configures the collision distance to the default value and is used
@@ -627,7 +625,7 @@ void igb_config_collision_dist(struct e1000_hw *hw)
627} 625}
628 626
629/** 627/**
630 * e1000_set_fc_watermarks - Set flow control high/low watermarks 628 * igb_set_fc_watermarks - Set flow control high/low watermarks
631 * @hw: pointer to the HW structure 629 * @hw: pointer to the HW structure
632 * 630 *
633 * Sets the flow control high/low threshold (watermark) registers. If 631 * Sets the flow control high/low threshold (watermark) registers. If
@@ -665,7 +663,7 @@ static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
665} 663}
666 664
667/** 665/**
668 * e1000_set_default_fc - Set flow control default values 666 * igb_set_default_fc - Set flow control default values
669 * @hw: pointer to the HW structure 667 * @hw: pointer to the HW structure
670 * 668 *
671 * Read the EEPROM for the default values for flow control and store the 669 * Read the EEPROM for the default values for flow control and store the
@@ -689,7 +687,7 @@ static s32 igb_set_default_fc(struct e1000_hw *hw)
689 &nvm_data); 687 &nvm_data);
690 688
691 if (ret_val) { 689 if (ret_val) {
692 hw_dbg(hw, "NVM Read Error\n"); 690 hw_dbg("NVM Read Error\n");
693 goto out; 691 goto out;
694 } 692 }
695 693
@@ -706,7 +704,7 @@ out:
706} 704}
707 705
708/** 706/**
709 * e1000_force_mac_fc - Force the MAC's flow control settings 707 * igb_force_mac_fc - Force the MAC's flow control settings
710 * @hw: pointer to the HW structure 708 * @hw: pointer to the HW structure
711 * 709 *
712 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 710 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
@@ -740,7 +738,7 @@ s32 igb_force_mac_fc(struct e1000_hw *hw)
740 * 3: Both Rx and TX flow control (symmetric) is enabled. 738 * 3: Both Rx and TX flow control (symmetric) is enabled.
741 * other: No other values should be possible at this point. 739 * other: No other values should be possible at this point.
742 */ 740 */
743 hw_dbg(hw, "hw->fc.type = %u\n", hw->fc.type); 741 hw_dbg("hw->fc.type = %u\n", hw->fc.type);
744 742
745 switch (hw->fc.type) { 743 switch (hw->fc.type) {
746 case e1000_fc_none: 744 case e1000_fc_none:
@@ -758,7 +756,7 @@ s32 igb_force_mac_fc(struct e1000_hw *hw)
758 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 756 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
759 break; 757 break;
760 default: 758 default:
761 hw_dbg(hw, "Flow control param set incorrectly\n"); 759 hw_dbg("Flow control param set incorrectly\n");
762 ret_val = -E1000_ERR_CONFIG; 760 ret_val = -E1000_ERR_CONFIG;
763 goto out; 761 goto out;
764 } 762 }
@@ -770,7 +768,7 @@ out:
770} 768}
771 769
772/** 770/**
773 * e1000_config_fc_after_link_up - Configures flow control after link 771 * igb_config_fc_after_link_up - Configures flow control after link
774 * @hw: pointer to the HW structure 772 * @hw: pointer to the HW structure
775 * 773 *
776 * Checks the status of auto-negotiation after link up to ensure that the 774 * Checks the status of auto-negotiation after link up to ensure that the
@@ -801,7 +799,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
801 } 799 }
802 800
803 if (ret_val) { 801 if (ret_val) {
804 hw_dbg(hw, "Error forcing flow control settings\n"); 802 hw_dbg("Error forcing flow control settings\n");
805 goto out; 803 goto out;
806 } 804 }
807 805
@@ -827,7 +825,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
827 goto out; 825 goto out;
828 826
829 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 827 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
830 hw_dbg(hw, "Copper PHY and Auto Neg " 828 hw_dbg("Copper PHY and Auto Neg "
831 "has not completed.\n"); 829 "has not completed.\n");
832 goto out; 830 goto out;
833 } 831 }
@@ -893,11 +891,11 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
893 */ 891 */
894 if (hw->fc.original_type == e1000_fc_full) { 892 if (hw->fc.original_type == e1000_fc_full) {
895 hw->fc.type = e1000_fc_full; 893 hw->fc.type = e1000_fc_full;
896 hw_dbg(hw, "Flow Control = FULL.\r\n"); 894 hw_dbg("Flow Control = FULL.\r\n");
897 } else { 895 } else {
898 hw->fc.type = e1000_fc_rx_pause; 896 hw->fc.type = e1000_fc_rx_pause;
899 hw_dbg(hw, "Flow Control = " 897 hw_dbg("Flow Control = "
900 "RX PAUSE frames only.\r\n"); 898 "RX PAUSE frames only.\r\n");
901 } 899 }
902 } 900 }
903 /* 901 /*
@@ -913,7 +911,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
913 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 911 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
914 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 912 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
915 hw->fc.type = e1000_fc_tx_pause; 913 hw->fc.type = e1000_fc_tx_pause;
916 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\r\n"); 914 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
917 } 915 }
918 /* 916 /*
919 * For transmitting PAUSE frames ONLY. 917 * For transmitting PAUSE frames ONLY.
@@ -928,7 +926,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
928 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 926 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
929 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 927 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
930 hw->fc.type = e1000_fc_rx_pause; 928 hw->fc.type = e1000_fc_rx_pause;
931 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); 929 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
932 } 930 }
933 /* 931 /*
934 * Per the IEEE spec, at this point flow control should be 932 * Per the IEEE spec, at this point flow control should be
@@ -955,10 +953,10 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
955 hw->fc.original_type == e1000_fc_tx_pause) || 953 hw->fc.original_type == e1000_fc_tx_pause) ||
956 hw->fc.strict_ieee) { 954 hw->fc.strict_ieee) {
957 hw->fc.type = e1000_fc_none; 955 hw->fc.type = e1000_fc_none;
958 hw_dbg(hw, "Flow Control = NONE.\r\n"); 956 hw_dbg("Flow Control = NONE.\r\n");
959 } else { 957 } else {
960 hw->fc.type = e1000_fc_rx_pause; 958 hw->fc.type = e1000_fc_rx_pause;
961 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); 959 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
962 } 960 }
963 961
964 /* 962 /*
@@ -968,7 +966,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
968 */ 966 */
969 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); 967 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
970 if (ret_val) { 968 if (ret_val) {
971 hw_dbg(hw, "Error getting link speed and duplex\n"); 969 hw_dbg("Error getting link speed and duplex\n");
972 goto out; 970 goto out;
973 } 971 }
974 972
@@ -981,7 +979,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
981 */ 979 */
982 ret_val = igb_force_mac_fc(hw); 980 ret_val = igb_force_mac_fc(hw);
983 if (ret_val) { 981 if (ret_val) {
984 hw_dbg(hw, "Error forcing flow control settings\n"); 982 hw_dbg("Error forcing flow control settings\n");
985 goto out; 983 goto out;
986 } 984 }
987 } 985 }
@@ -991,7 +989,7 @@ out:
991} 989}
992 990
993/** 991/**
994 * e1000_get_speed_and_duplex_copper - Retreive current speed/duplex 992 * igb_get_speed_and_duplex_copper - Retreive current speed/duplex
995 * @hw: pointer to the HW structure 993 * @hw: pointer to the HW structure
996 * @speed: stores the current speed 994 * @speed: stores the current speed
997 * @duplex: stores the current duplex 995 * @duplex: stores the current duplex
@@ -1007,28 +1005,28 @@ s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1007 status = rd32(E1000_STATUS); 1005 status = rd32(E1000_STATUS);
1008 if (status & E1000_STATUS_SPEED_1000) { 1006 if (status & E1000_STATUS_SPEED_1000) {
1009 *speed = SPEED_1000; 1007 *speed = SPEED_1000;
1010 hw_dbg(hw, "1000 Mbs, "); 1008 hw_dbg("1000 Mbs, ");
1011 } else if (status & E1000_STATUS_SPEED_100) { 1009 } else if (status & E1000_STATUS_SPEED_100) {
1012 *speed = SPEED_100; 1010 *speed = SPEED_100;
1013 hw_dbg(hw, "100 Mbs, "); 1011 hw_dbg("100 Mbs, ");
1014 } else { 1012 } else {
1015 *speed = SPEED_10; 1013 *speed = SPEED_10;
1016 hw_dbg(hw, "10 Mbs, "); 1014 hw_dbg("10 Mbs, ");
1017 } 1015 }
1018 1016
1019 if (status & E1000_STATUS_FD) { 1017 if (status & E1000_STATUS_FD) {
1020 *duplex = FULL_DUPLEX; 1018 *duplex = FULL_DUPLEX;
1021 hw_dbg(hw, "Full Duplex\n"); 1019 hw_dbg("Full Duplex\n");
1022 } else { 1020 } else {
1023 *duplex = HALF_DUPLEX; 1021 *duplex = HALF_DUPLEX;
1024 hw_dbg(hw, "Half Duplex\n"); 1022 hw_dbg("Half Duplex\n");
1025 } 1023 }
1026 1024
1027 return 0; 1025 return 0;
1028} 1026}
1029 1027
1030/** 1028/**
1031 * e1000_get_hw_semaphore - Acquire hardware semaphore 1029 * igb_get_hw_semaphore - Acquire hardware semaphore
1032 * @hw: pointer to the HW structure 1030 * @hw: pointer to the HW structure
1033 * 1031 *
1034 * Acquire the HW semaphore to access the PHY or NVM 1032 * Acquire the HW semaphore to access the PHY or NVM
@@ -1051,7 +1049,7 @@ s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1051 } 1049 }
1052 1050
1053 if (i == timeout) { 1051 if (i == timeout) {
1054 hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n"); 1052 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1055 ret_val = -E1000_ERR_NVM; 1053 ret_val = -E1000_ERR_NVM;
1056 goto out; 1054 goto out;
1057 } 1055 }
@@ -1071,7 +1069,7 @@ s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1071 if (i == timeout) { 1069 if (i == timeout) {
1072 /* Release semaphores */ 1070 /* Release semaphores */
1073 igb_put_hw_semaphore(hw); 1071 igb_put_hw_semaphore(hw);
1074 hw_dbg(hw, "Driver can't access the NVM\n"); 1072 hw_dbg("Driver can't access the NVM\n");
1075 ret_val = -E1000_ERR_NVM; 1073 ret_val = -E1000_ERR_NVM;
1076 goto out; 1074 goto out;
1077 } 1075 }
@@ -1081,7 +1079,7 @@ out:
1081} 1079}
1082 1080
1083/** 1081/**
1084 * e1000_put_hw_semaphore - Release hardware semaphore 1082 * igb_put_hw_semaphore - Release hardware semaphore
1085 * @hw: pointer to the HW structure 1083 * @hw: pointer to the HW structure
1086 * 1084 *
1087 * Release hardware semaphore used to access the PHY or NVM 1085 * Release hardware semaphore used to access the PHY or NVM
@@ -1098,7 +1096,7 @@ void igb_put_hw_semaphore(struct e1000_hw *hw)
1098} 1096}
1099 1097
1100/** 1098/**
1101 * e1000_get_auto_rd_done - Check for auto read completion 1099 * igb_get_auto_rd_done - Check for auto read completion
1102 * @hw: pointer to the HW structure 1100 * @hw: pointer to the HW structure
1103 * 1101 *
1104 * Check EEPROM for Auto Read done bit. 1102 * Check EEPROM for Auto Read done bit.
@@ -1117,7 +1115,7 @@ s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1117 } 1115 }
1118 1116
1119 if (i == AUTO_READ_DONE_TIMEOUT) { 1117 if (i == AUTO_READ_DONE_TIMEOUT) {
1120 hw_dbg(hw, "Auto read by HW from NVM has not completed.\n"); 1118 hw_dbg("Auto read by HW from NVM has not completed.\n");
1121 ret_val = -E1000_ERR_RESET; 1119 ret_val = -E1000_ERR_RESET;
1122 goto out; 1120 goto out;
1123 } 1121 }
@@ -1127,7 +1125,7 @@ out:
1127} 1125}
1128 1126
1129/** 1127/**
1130 * e1000_valid_led_default - Verify a valid default LED config 1128 * igb_valid_led_default - Verify a valid default LED config
1131 * @hw: pointer to the HW structure 1129 * @hw: pointer to the HW structure
1132 * @data: pointer to the NVM (EEPROM) 1130 * @data: pointer to the NVM (EEPROM)
1133 * 1131 *
@@ -1140,7 +1138,7 @@ static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1140 1138
1141 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1139 ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1142 if (ret_val) { 1140 if (ret_val) {
1143 hw_dbg(hw, "NVM Read Error\n"); 1141 hw_dbg("NVM Read Error\n");
1144 goto out; 1142 goto out;
1145 } 1143 }
1146 1144
@@ -1152,7 +1150,7 @@ out:
1152} 1150}
1153 1151
1154/** 1152/**
1155 * e1000_id_led_init - 1153 * igb_id_led_init -
1156 * @hw: pointer to the HW structure 1154 * @hw: pointer to the HW structure
1157 * 1155 *
1158 **/ 1156 **/
@@ -1217,7 +1215,7 @@ out:
1217} 1215}
1218 1216
1219/** 1217/**
1220 * e1000_cleanup_led - Set LED config to default operation 1218 * igb_cleanup_led - Set LED config to default operation
1221 * @hw: pointer to the HW structure 1219 * @hw: pointer to the HW structure
1222 * 1220 *
1223 * Remove the current LED configuration and set the LED configuration 1221 * Remove the current LED configuration and set the LED configuration
@@ -1230,7 +1228,7 @@ s32 igb_cleanup_led(struct e1000_hw *hw)
1230} 1228}
1231 1229
1232/** 1230/**
1233 * e1000_blink_led - Blink LED 1231 * igb_blink_led - Blink LED
1234 * @hw: pointer to the HW structure 1232 * @hw: pointer to the HW structure
1235 * 1233 *
1236 * Blink the led's which are set to be on. 1234 * Blink the led's which are set to be on.
@@ -1263,7 +1261,7 @@ s32 igb_blink_led(struct e1000_hw *hw)
1263} 1261}
1264 1262
1265/** 1263/**
1266 * e1000_led_off - Turn LED off 1264 * igb_led_off - Turn LED off
1267 * @hw: pointer to the HW structure 1265 * @hw: pointer to the HW structure
1268 * 1266 *
1269 * Turn LED off. 1267 * Turn LED off.
@@ -1290,7 +1288,7 @@ s32 igb_led_off(struct e1000_hw *hw)
1290} 1288}
1291 1289
1292/** 1290/**
1293 * e1000_disable_pcie_master - Disables PCI-express master access 1291 * igb_disable_pcie_master - Disables PCI-express master access
1294 * @hw: pointer to the HW structure 1292 * @hw: pointer to the HW structure
1295 * 1293 *
1296 * Returns 0 (0) if successful, else returns -10 1294 * Returns 0 (0) if successful, else returns -10
@@ -1322,7 +1320,7 @@ s32 igb_disable_pcie_master(struct e1000_hw *hw)
1322 } 1320 }
1323 1321
1324 if (!timeout) { 1322 if (!timeout) {
1325 hw_dbg(hw, "Master requests are pending.\n"); 1323 hw_dbg("Master requests are pending.\n");
1326 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1324 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1327 goto out; 1325 goto out;
1328 } 1326 }
@@ -1332,7 +1330,7 @@ out:
1332} 1330}
1333 1331
1334/** 1332/**
1335 * e1000_reset_adaptive - Reset Adaptive Interframe Spacing 1333 * igb_reset_adaptive - Reset Adaptive Interframe Spacing
1336 * @hw: pointer to the HW structure 1334 * @hw: pointer to the HW structure
1337 * 1335 *
1338 * Reset the Adaptive Interframe Spacing throttle to default values. 1336 * Reset the Adaptive Interframe Spacing throttle to default values.
@@ -1342,7 +1340,7 @@ void igb_reset_adaptive(struct e1000_hw *hw)
1342 struct e1000_mac_info *mac = &hw->mac; 1340 struct e1000_mac_info *mac = &hw->mac;
1343 1341
1344 if (!mac->adaptive_ifs) { 1342 if (!mac->adaptive_ifs) {
1345 hw_dbg(hw, "Not in Adaptive IFS mode!\n"); 1343 hw_dbg("Not in Adaptive IFS mode!\n");
1346 goto out; 1344 goto out;
1347 } 1345 }
1348 1346
@@ -1361,7 +1359,7 @@ out:
1361} 1359}
1362 1360
1363/** 1361/**
1364 * e1000_update_adaptive - Update Adaptive Interframe Spacing 1362 * igb_update_adaptive - Update Adaptive Interframe Spacing
1365 * @hw: pointer to the HW structure 1363 * @hw: pointer to the HW structure
1366 * 1364 *
1367 * Update the Adaptive Interframe Spacing Throttle value based on the 1365 * Update the Adaptive Interframe Spacing Throttle value based on the
@@ -1372,7 +1370,7 @@ void igb_update_adaptive(struct e1000_hw *hw)
1372 struct e1000_mac_info *mac = &hw->mac; 1370 struct e1000_mac_info *mac = &hw->mac;
1373 1371
1374 if (!mac->adaptive_ifs) { 1372 if (!mac->adaptive_ifs) {
1375 hw_dbg(hw, "Not in Adaptive IFS mode!\n"); 1373 hw_dbg("Not in Adaptive IFS mode!\n");
1376 goto out; 1374 goto out;
1377 } 1375 }
1378 1376
@@ -1402,7 +1400,7 @@ out:
1402} 1400}
1403 1401
1404/** 1402/**
1405 * e1000_validate_mdi_setting - Verify MDI/MDIx settings 1403 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1406 * @hw: pointer to the HW structure 1404 * @hw: pointer to the HW structure
1407 * 1405 *
1408 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 1406 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
@@ -1413,7 +1411,7 @@ s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1413 s32 ret_val = 0; 1411 s32 ret_val = 0;
1414 1412
1415 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1413 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1416 hw_dbg(hw, "Invalid MDI setting detected\n"); 1414 hw_dbg("Invalid MDI setting detected\n");
1417 hw->phy.mdix = 1; 1415 hw->phy.mdix = 1;
1418 ret_val = -E1000_ERR_CONFIG; 1416 ret_val = -E1000_ERR_CONFIG;
1419 goto out; 1417 goto out;
@@ -1424,7 +1422,7 @@ out:
1424} 1422}
1425 1423
1426/** 1424/**
1427 * e1000_write_8bit_ctrl_reg - Write a 8bit CTRL register 1425 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1428 * @hw: pointer to the HW structure 1426 * @hw: pointer to the HW structure
1429 * @reg: 32bit register offset such as E1000_SCTL 1427 * @reg: 32bit register offset such as E1000_SCTL
1430 * @offset: register offset to write to 1428 * @offset: register offset to write to
@@ -1452,7 +1450,7 @@ s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1452 break; 1450 break;
1453 } 1451 }
1454 if (!(regvalue & E1000_GEN_CTL_READY)) { 1452 if (!(regvalue & E1000_GEN_CTL_READY)) {
1455 hw_dbg(hw, "Reg %08x did not indicate ready\n", reg); 1453 hw_dbg("Reg %08x did not indicate ready\n", reg);
1456 ret_val = -E1000_ERR_PHY; 1454 ret_val = -E1000_ERR_PHY;
1457 goto out; 1455 goto out;
1458 } 1456 }
@@ -1462,7 +1460,7 @@ out:
1462} 1460}
1463 1461
1464/** 1462/**
1465 * e1000_enable_mng_pass_thru - Enable processing of ARP's 1463 * igb_enable_mng_pass_thru - Enable processing of ARP's
1466 * @hw: pointer to the HW structure 1464 * @hw: pointer to the HW structure
1467 * 1465 *
1468 * Verifies the hardware needs to allow ARPs to be processed by the host. 1466 * Verifies the hardware needs to allow ARPs to be processed by the host.
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h
index 326b6592307b..dc2f8cce15e7 100644
--- a/drivers/net/igb/e1000_mac.h
+++ b/drivers/net/igb/e1000_mac.h
@@ -94,5 +94,6 @@ enum e1000_mng_mode {
94#define E1000_HICR_C 0x02 94#define E1000_HICR_C 0x02
95 95
96extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); 96extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
97extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
97 98
98#endif 99#endif
diff --git a/drivers/net/igb/e1000_nvm.c b/drivers/net/igb/e1000_nvm.c
index 2897106fee92..a84e4e429fa7 100644
--- a/drivers/net/igb/e1000_nvm.c
+++ b/drivers/net/igb/e1000_nvm.c
@@ -32,7 +32,7 @@
32#include "e1000_nvm.h" 32#include "e1000_nvm.h"
33 33
34/** 34/**
35 * e1000_raise_eec_clk - Raise EEPROM clock 35 * igb_raise_eec_clk - Raise EEPROM clock
36 * @hw: pointer to the HW structure 36 * @hw: pointer to the HW structure
37 * @eecd: pointer to the EEPROM 37 * @eecd: pointer to the EEPROM
38 * 38 *
@@ -47,7 +47,7 @@ static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
47} 47}
48 48
49/** 49/**
50 * e1000_lower_eec_clk - Lower EEPROM clock 50 * igb_lower_eec_clk - Lower EEPROM clock
51 * @hw: pointer to the HW structure 51 * @hw: pointer to the HW structure
52 * @eecd: pointer to the EEPROM 52 * @eecd: pointer to the EEPROM
53 * 53 *
@@ -62,7 +62,7 @@ static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
62} 62}
63 63
64/** 64/**
65 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 65 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
66 * @hw: pointer to the HW structure 66 * @hw: pointer to the HW structure
67 * @data: data to send to the EEPROM 67 * @data: data to send to the EEPROM
68 * @count: number of bits to shift out 68 * @count: number of bits to shift out
@@ -105,7 +105,7 @@ static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
105} 105}
106 106
107/** 107/**
108 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 108 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM
109 * @hw: pointer to the HW structure 109 * @hw: pointer to the HW structure
110 * @count: number of bits to shift in 110 * @count: number of bits to shift in
111 * 111 *
@@ -143,7 +143,7 @@ static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
143} 143}
144 144
145/** 145/**
146 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 146 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
147 * @hw: pointer to the HW structure 147 * @hw: pointer to the HW structure
148 * @ee_reg: EEPROM flag for polling 148 * @ee_reg: EEPROM flag for polling
149 * 149 *
@@ -174,7 +174,7 @@ static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
174} 174}
175 175
176/** 176/**
177 * e1000_acquire_nvm - Generic request for access to EEPROM 177 * igb_acquire_nvm - Generic request for access to EEPROM
178 * @hw: pointer to the HW structure 178 * @hw: pointer to the HW structure
179 * 179 *
180 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 180 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
@@ -202,7 +202,7 @@ s32 igb_acquire_nvm(struct e1000_hw *hw)
202 if (!timeout) { 202 if (!timeout) {
203 eecd &= ~E1000_EECD_REQ; 203 eecd &= ~E1000_EECD_REQ;
204 wr32(E1000_EECD, eecd); 204 wr32(E1000_EECD, eecd);
205 hw_dbg(hw, "Could not acquire NVM grant\n"); 205 hw_dbg("Could not acquire NVM grant\n");
206 ret_val = -E1000_ERR_NVM; 206 ret_val = -E1000_ERR_NVM;
207 } 207 }
208 208
@@ -210,7 +210,7 @@ s32 igb_acquire_nvm(struct e1000_hw *hw)
210} 210}
211 211
212/** 212/**
213 * e1000_standby_nvm - Return EEPROM to standby state 213 * igb_standby_nvm - Return EEPROM to standby state
214 * @hw: pointer to the HW structure 214 * @hw: pointer to the HW structure
215 * 215 *
216 * Return the EEPROM to a standby state. 216 * Return the EEPROM to a standby state.
@@ -273,7 +273,7 @@ static void e1000_stop_nvm(struct e1000_hw *hw)
273} 273}
274 274
275/** 275/**
276 * e1000_release_nvm - Release exclusive access to EEPROM 276 * igb_release_nvm - Release exclusive access to EEPROM
277 * @hw: pointer to the HW structure 277 * @hw: pointer to the HW structure
278 * 278 *
279 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 279 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
@@ -290,7 +290,7 @@ void igb_release_nvm(struct e1000_hw *hw)
290} 290}
291 291
292/** 292/**
293 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 293 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write
294 * @hw: pointer to the HW structure 294 * @hw: pointer to the HW structure
295 * 295 *
296 * Setups the EEPROM for reading and writing. 296 * Setups the EEPROM for reading and writing.
@@ -337,7 +337,7 @@ static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
337 } 337 }
338 338
339 if (!timeout) { 339 if (!timeout) {
340 hw_dbg(hw, "SPI NVM Status error\n"); 340 hw_dbg("SPI NVM Status error\n");
341 ret_val = -E1000_ERR_NVM; 341 ret_val = -E1000_ERR_NVM;
342 goto out; 342 goto out;
343 } 343 }
@@ -348,7 +348,7 @@ out:
348} 348}
349 349
350/** 350/**
351 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 351 * igb_read_nvm_eerd - Reads EEPROM using EERD register
352 * @hw: pointer to the HW structure 352 * @hw: pointer to the HW structure
353 * @offset: offset of word in the EEPROM to read 353 * @offset: offset of word in the EEPROM to read
354 * @words: number of words to read 354 * @words: number of words to read
@@ -368,7 +368,7 @@ s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
368 */ 368 */
369 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 369 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
370 (words == 0)) { 370 (words == 0)) {
371 hw_dbg(hw, "nvm parameter(s) out of bounds\n"); 371 hw_dbg("nvm parameter(s) out of bounds\n");
372 ret_val = -E1000_ERR_NVM; 372 ret_val = -E1000_ERR_NVM;
373 goto out; 373 goto out;
374 } 374 }
@@ -391,7 +391,7 @@ out:
391} 391}
392 392
393/** 393/**
394 * e1000_write_nvm_spi - Write to EEPROM using SPI 394 * igb_write_nvm_spi - Write to EEPROM using SPI
395 * @hw: pointer to the HW structure 395 * @hw: pointer to the HW structure
396 * @offset: offset within the EEPROM to be written to 396 * @offset: offset within the EEPROM to be written to
397 * @words: number of words to write 397 * @words: number of words to write
@@ -414,7 +414,7 @@ s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
414 */ 414 */
415 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 415 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
416 (words == 0)) { 416 (words == 0)) {
417 hw_dbg(hw, "nvm parameter(s) out of bounds\n"); 417 hw_dbg("nvm parameter(s) out of bounds\n");
418 ret_val = -E1000_ERR_NVM; 418 ret_val = -E1000_ERR_NVM;
419 goto out; 419 goto out;
420 } 420 }
@@ -475,7 +475,7 @@ out:
475} 475}
476 476
477/** 477/**
478 * e1000_read_part_num - Read device part number 478 * igb_read_part_num - Read device part number
479 * @hw: pointer to the HW structure 479 * @hw: pointer to the HW structure
480 * @part_num: pointer to device part number 480 * @part_num: pointer to device part number
481 * 481 *
@@ -489,14 +489,14 @@ s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num)
489 489
490 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 490 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
491 if (ret_val) { 491 if (ret_val) {
492 hw_dbg(hw, "NVM Read Error\n"); 492 hw_dbg("NVM Read Error\n");
493 goto out; 493 goto out;
494 } 494 }
495 *part_num = (u32)(nvm_data << 16); 495 *part_num = (u32)(nvm_data << 16);
496 496
497 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 497 ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
498 if (ret_val) { 498 if (ret_val) {
499 hw_dbg(hw, "NVM Read Error\n"); 499 hw_dbg("NVM Read Error\n");
500 goto out; 500 goto out;
501 } 501 }
502 *part_num |= nvm_data; 502 *part_num |= nvm_data;
@@ -506,7 +506,7 @@ out:
506} 506}
507 507
508/** 508/**
509 * e1000_read_mac_addr - Read device MAC address 509 * igb_read_mac_addr - Read device MAC address
510 * @hw: pointer to the HW structure 510 * @hw: pointer to the HW structure
511 * 511 *
512 * Reads the device MAC address from the EEPROM and stores the value. 512 * Reads the device MAC address from the EEPROM and stores the value.
@@ -522,7 +522,7 @@ s32 igb_read_mac_addr(struct e1000_hw *hw)
522 offset = i >> 1; 522 offset = i >> 1;
523 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data); 523 ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
524 if (ret_val) { 524 if (ret_val) {
525 hw_dbg(hw, "NVM Read Error\n"); 525 hw_dbg("NVM Read Error\n");
526 goto out; 526 goto out;
527 } 527 }
528 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 528 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
@@ -541,7 +541,7 @@ out:
541} 541}
542 542
543/** 543/**
544 * e1000_validate_nvm_checksum - Validate EEPROM checksum 544 * igb_validate_nvm_checksum - Validate EEPROM checksum
545 * @hw: pointer to the HW structure 545 * @hw: pointer to the HW structure
546 * 546 *
547 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 547 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
@@ -556,14 +556,14 @@ s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
556 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 556 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
557 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); 557 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
558 if (ret_val) { 558 if (ret_val) {
559 hw_dbg(hw, "NVM Read Error\n"); 559 hw_dbg("NVM Read Error\n");
560 goto out; 560 goto out;
561 } 561 }
562 checksum += nvm_data; 562 checksum += nvm_data;
563 } 563 }
564 564
565 if (checksum != (u16) NVM_SUM) { 565 if (checksum != (u16) NVM_SUM) {
566 hw_dbg(hw, "NVM Checksum Invalid\n"); 566 hw_dbg("NVM Checksum Invalid\n");
567 ret_val = -E1000_ERR_NVM; 567 ret_val = -E1000_ERR_NVM;
568 goto out; 568 goto out;
569 } 569 }
@@ -573,7 +573,7 @@ out:
573} 573}
574 574
575/** 575/**
576 * e1000_update_nvm_checksum - Update EEPROM checksum 576 * igb_update_nvm_checksum - Update EEPROM checksum
577 * @hw: pointer to the HW structure 577 * @hw: pointer to the HW structure
578 * 578 *
579 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 579 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
@@ -589,7 +589,7 @@ s32 igb_update_nvm_checksum(struct e1000_hw *hw)
589 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 589 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
590 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data); 590 ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
591 if (ret_val) { 591 if (ret_val) {
592 hw_dbg(hw, "NVM Read Error while updating checksum.\n"); 592 hw_dbg("NVM Read Error while updating checksum.\n");
593 goto out; 593 goto out;
594 } 594 }
595 checksum += nvm_data; 595 checksum += nvm_data;
@@ -597,7 +597,7 @@ s32 igb_update_nvm_checksum(struct e1000_hw *hw)
597 checksum = (u16) NVM_SUM - checksum; 597 checksum = (u16) NVM_SUM - checksum;
598 ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 598 ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
599 if (ret_val) 599 if (ret_val)
600 hw_dbg(hw, "NVM Write Error while updating checksum.\n"); 600 hw_dbg("NVM Write Error while updating checksum.\n");
601 601
602out: 602out:
603 return ret_val; 603 return ret_val;
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c
index 08a86b107229..17fddb91c9f5 100644
--- a/drivers/net/igb/e1000_phy.c
+++ b/drivers/net/igb/e1000_phy.c
@@ -61,7 +61,7 @@ static const u16 e1000_igp_2_cable_length_table[] =
61 sizeof(e1000_igp_2_cable_length_table[0])) 61 sizeof(e1000_igp_2_cable_length_table[0]))
62 62
63/** 63/**
64 * e1000_check_reset_block - Check if PHY reset is blocked 64 * igb_check_reset_block - Check if PHY reset is blocked
65 * @hw: pointer to the HW structure 65 * @hw: pointer to the HW structure
66 * 66 *
67 * Read the PHY management control register and check whether a PHY reset 67 * Read the PHY management control register and check whether a PHY reset
@@ -79,7 +79,7 @@ s32 igb_check_reset_block(struct e1000_hw *hw)
79} 79}
80 80
81/** 81/**
82 * e1000_get_phy_id - Retrieve the PHY ID and revision 82 * igb_get_phy_id - Retrieve the PHY ID and revision
83 * @hw: pointer to the HW structure 83 * @hw: pointer to the HW structure
84 * 84 *
85 * Reads the PHY registers and stores the PHY ID and possibly the PHY 85 * Reads the PHY registers and stores the PHY ID and possibly the PHY
@@ -109,7 +109,7 @@ out:
109} 109}
110 110
111/** 111/**
112 * e1000_phy_reset_dsp - Reset PHY DSP 112 * igb_phy_reset_dsp - Reset PHY DSP
113 * @hw: pointer to the HW structure 113 * @hw: pointer to the HW structure
114 * 114 *
115 * Reset the digital signal processor. 115 * Reset the digital signal processor.
@@ -129,7 +129,7 @@ out:
129} 129}
130 130
131/** 131/**
132 * e1000_read_phy_reg_mdic - Read MDI control register 132 * igb_read_phy_reg_mdic - Read MDI control register
133 * @hw: pointer to the HW structure 133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read 134 * @offset: register offset to be read
135 * @data: pointer to the read data 135 * @data: pointer to the read data
@@ -144,7 +144,7 @@ static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
144 s32 ret_val = 0; 144 s32 ret_val = 0;
145 145
146 if (offset > MAX_PHY_REG_ADDRESS) { 146 if (offset > MAX_PHY_REG_ADDRESS) {
147 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 147 hw_dbg("PHY Address %d is out of range\n", offset);
148 ret_val = -E1000_ERR_PARAM; 148 ret_val = -E1000_ERR_PARAM;
149 goto out; 149 goto out;
150 } 150 }
@@ -172,12 +172,12 @@ static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
172 break; 172 break;
173 } 173 }
174 if (!(mdic & E1000_MDIC_READY)) { 174 if (!(mdic & E1000_MDIC_READY)) {
175 hw_dbg(hw, "MDI Read did not complete\n"); 175 hw_dbg("MDI Read did not complete\n");
176 ret_val = -E1000_ERR_PHY; 176 ret_val = -E1000_ERR_PHY;
177 goto out; 177 goto out;
178 } 178 }
179 if (mdic & E1000_MDIC_ERROR) { 179 if (mdic & E1000_MDIC_ERROR) {
180 hw_dbg(hw, "MDI Error\n"); 180 hw_dbg("MDI Error\n");
181 ret_val = -E1000_ERR_PHY; 181 ret_val = -E1000_ERR_PHY;
182 goto out; 182 goto out;
183 } 183 }
@@ -188,7 +188,7 @@ out:
188} 188}
189 189
190/** 190/**
191 * e1000_write_phy_reg_mdic - Write MDI control register 191 * igb_write_phy_reg_mdic - Write MDI control register
192 * @hw: pointer to the HW structure 192 * @hw: pointer to the HW structure
193 * @offset: register offset to write to 193 * @offset: register offset to write to
194 * @data: data to write to register at offset 194 * @data: data to write to register at offset
@@ -202,7 +202,7 @@ static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
202 s32 ret_val = 0; 202 s32 ret_val = 0;
203 203
204 if (offset > MAX_PHY_REG_ADDRESS) { 204 if (offset > MAX_PHY_REG_ADDRESS) {
205 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 205 hw_dbg("PHY Address %d is out of range\n", offset);
206 ret_val = -E1000_ERR_PARAM; 206 ret_val = -E1000_ERR_PARAM;
207 goto out; 207 goto out;
208 } 208 }
@@ -231,12 +231,12 @@ static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
231 break; 231 break;
232 } 232 }
233 if (!(mdic & E1000_MDIC_READY)) { 233 if (!(mdic & E1000_MDIC_READY)) {
234 hw_dbg(hw, "MDI Write did not complete\n"); 234 hw_dbg("MDI Write did not complete\n");
235 ret_val = -E1000_ERR_PHY; 235 ret_val = -E1000_ERR_PHY;
236 goto out; 236 goto out;
237 } 237 }
238 if (mdic & E1000_MDIC_ERROR) { 238 if (mdic & E1000_MDIC_ERROR) {
239 hw_dbg(hw, "MDI Error\n"); 239 hw_dbg("MDI Error\n");
240 ret_val = -E1000_ERR_PHY; 240 ret_val = -E1000_ERR_PHY;
241 goto out; 241 goto out;
242 } 242 }
@@ -246,7 +246,7 @@ out:
246} 246}
247 247
248/** 248/**
249 * e1000_read_phy_reg_igp - Read igp PHY register 249 * igb_read_phy_reg_igp - Read igp PHY register
250 * @hw: pointer to the HW structure 250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read 251 * @offset: register offset to be read
252 * @data: pointer to the read data 252 * @data: pointer to the read data
@@ -284,7 +284,7 @@ out:
284} 284}
285 285
286/** 286/**
287 * e1000_write_phy_reg_igp - Write igp PHY register 287 * igb_write_phy_reg_igp - Write igp PHY register
288 * @hw: pointer to the HW structure 288 * @hw: pointer to the HW structure
289 * @offset: register offset to write to 289 * @offset: register offset to write to
290 * @data: data to write at register offset 290 * @data: data to write at register offset
@@ -321,7 +321,7 @@ out:
321} 321}
322 322
323/** 323/**
324 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 324 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
325 * @hw: pointer to the HW structure 325 * @hw: pointer to the HW structure
326 * 326 *
327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
@@ -423,7 +423,7 @@ s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
423 /* Commit the changes. */ 423 /* Commit the changes. */
424 ret_val = igb_phy_sw_reset(hw); 424 ret_val = igb_phy_sw_reset(hw);
425 if (ret_val) { 425 if (ret_val) {
426 hw_dbg(hw, "Error committing the PHY changes\n"); 426 hw_dbg("Error committing the PHY changes\n");
427 goto out; 427 goto out;
428 } 428 }
429 429
@@ -432,7 +432,7 @@ out:
432} 432}
433 433
434/** 434/**
435 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 435 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
436 * @hw: pointer to the HW structure 436 * @hw: pointer to the HW structure
437 * 437 *
438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
@@ -451,7 +451,7 @@ s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
451 451
452 ret_val = hw->phy.ops.reset_phy(hw); 452 ret_val = hw->phy.ops.reset_phy(hw);
453 if (ret_val) { 453 if (ret_val) {
454 hw_dbg(hw, "Error resetting the PHY.\n"); 454 hw_dbg("Error resetting the PHY.\n");
455 goto out; 455 goto out;
456 } 456 }
457 457
@@ -467,7 +467,7 @@ s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
467 if (hw->phy.ops.set_d3_lplu_state) 467 if (hw->phy.ops.set_d3_lplu_state)
468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
469 if (ret_val) { 469 if (ret_val) {
470 hw_dbg(hw, "Error Disabling LPLU D3\n"); 470 hw_dbg("Error Disabling LPLU D3\n");
471 goto out; 471 goto out;
472 } 472 }
473 } 473 }
@@ -475,7 +475,7 @@ s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
475 /* disable lplu d0 during driver init */ 475 /* disable lplu d0 during driver init */
476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
477 if (ret_val) { 477 if (ret_val) {
478 hw_dbg(hw, "Error Disabling LPLU D0\n"); 478 hw_dbg("Error Disabling LPLU D0\n");
479 goto out; 479 goto out;
480 } 480 }
481 /* Configure mdi-mdix settings */ 481 /* Configure mdi-mdix settings */
@@ -570,7 +570,7 @@ out:
570} 570}
571 571
572/** 572/**
573 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 573 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
574 * @hw: pointer to the HW structure 574 * @hw: pointer to the HW structure
575 * 575 *
576 * Performs initial bounds checking on autoneg advertisement parameter, then 576 * Performs initial bounds checking on autoneg advertisement parameter, then
@@ -597,13 +597,13 @@ s32 igb_copper_link_autoneg(struct e1000_hw *hw)
597 if (phy->autoneg_advertised == 0) 597 if (phy->autoneg_advertised == 0)
598 phy->autoneg_advertised = phy->autoneg_mask; 598 phy->autoneg_advertised = phy->autoneg_mask;
599 599
600 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n"); 600 hw_dbg("Reconfiguring auto-neg advertisement params\n");
601 ret_val = igb_phy_setup_autoneg(hw); 601 ret_val = igb_phy_setup_autoneg(hw);
602 if (ret_val) { 602 if (ret_val) {
603 hw_dbg(hw, "Error Setting up Auto-Negotiation\n"); 603 hw_dbg("Error Setting up Auto-Negotiation\n");
604 goto out; 604 goto out;
605 } 605 }
606 hw_dbg(hw, "Restarting Auto-Neg\n"); 606 hw_dbg("Restarting Auto-Neg\n");
607 607
608 /* 608 /*
609 * Restart auto-negotiation by setting the Auto Neg Enable bit and 609 * Restart auto-negotiation by setting the Auto Neg Enable bit and
@@ -625,8 +625,8 @@ s32 igb_copper_link_autoneg(struct e1000_hw *hw)
625 if (phy->autoneg_wait_to_complete) { 625 if (phy->autoneg_wait_to_complete) {
626 ret_val = igb_wait_autoneg(hw); 626 ret_val = igb_wait_autoneg(hw);
627 if (ret_val) { 627 if (ret_val) {
628 hw_dbg(hw, "Error while waiting for " 628 hw_dbg("Error while waiting for "
629 "autoneg to complete\n"); 629 "autoneg to complete\n");
630 goto out; 630 goto out;
631 } 631 }
632 } 632 }
@@ -638,7 +638,7 @@ out:
638} 638}
639 639
640/** 640/**
641 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 641 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
642 * @hw: pointer to the HW structure 642 * @hw: pointer to the HW structure
643 * 643 *
644 * Reads the MII auto-neg advertisement register and/or the 1000T control 644 * Reads the MII auto-neg advertisement register and/or the 1000T control
@@ -689,39 +689,39 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
689 NWAY_AR_10T_HD_CAPS); 689 NWAY_AR_10T_HD_CAPS);
690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
691 691
692 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised); 692 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
693 693
694 /* Do we want to advertise 10 Mb Half Duplex? */ 694 /* Do we want to advertise 10 Mb Half Duplex? */
695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
696 hw_dbg(hw, "Advertise 10mb Half duplex\n"); 696 hw_dbg("Advertise 10mb Half duplex\n");
697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
698 } 698 }
699 699
700 /* Do we want to advertise 10 Mb Full Duplex? */ 700 /* Do we want to advertise 10 Mb Full Duplex? */
701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
702 hw_dbg(hw, "Advertise 10mb Full duplex\n"); 702 hw_dbg("Advertise 10mb Full duplex\n");
703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
704 } 704 }
705 705
706 /* Do we want to advertise 100 Mb Half Duplex? */ 706 /* Do we want to advertise 100 Mb Half Duplex? */
707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
708 hw_dbg(hw, "Advertise 100mb Half duplex\n"); 708 hw_dbg("Advertise 100mb Half duplex\n");
709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
710 } 710 }
711 711
712 /* Do we want to advertise 100 Mb Full Duplex? */ 712 /* Do we want to advertise 100 Mb Full Duplex? */
713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
714 hw_dbg(hw, "Advertise 100mb Full duplex\n"); 714 hw_dbg("Advertise 100mb Full duplex\n");
715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
716 } 716 }
717 717
718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
720 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n"); 720 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
721 721
722 /* Do we want to advertise 1000 Mb Full Duplex? */ 722 /* Do we want to advertise 1000 Mb Full Duplex? */
723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
724 hw_dbg(hw, "Advertise 1000mb Full duplex\n"); 724 hw_dbg("Advertise 1000mb Full duplex\n");
725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
726 } 726 }
727 727
@@ -780,7 +780,7 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
781 break; 781 break;
782 default: 782 default:
783 hw_dbg(hw, "Flow control param set incorrectly\n"); 783 hw_dbg("Flow control param set incorrectly\n");
784 ret_val = -E1000_ERR_CONFIG; 784 ret_val = -E1000_ERR_CONFIG;
785 goto out; 785 goto out;
786 } 786 }
@@ -790,7 +790,7 @@ static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
790 if (ret_val) 790 if (ret_val)
791 goto out; 791 goto out;
792 792
793 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 793 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
794 794
795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
796 ret_val = hw->phy.ops.write_phy_reg(hw, 796 ret_val = hw->phy.ops.write_phy_reg(hw,
@@ -805,7 +805,7 @@ out:
805} 805}
806 806
807/** 807/**
808 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 808 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
809 * @hw: pointer to the HW structure 809 * @hw: pointer to the HW structure
810 * 810 *
811 * Calls the PHY setup function to force speed and duplex. Clears the 811 * Calls the PHY setup function to force speed and duplex. Clears the
@@ -846,13 +846,12 @@ s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
846 if (ret_val) 846 if (ret_val)
847 goto out; 847 goto out;
848 848
849 hw_dbg(hw, "IGP PSCR: %X\n", phy_data); 849 hw_dbg("IGP PSCR: %X\n", phy_data);
850 850
851 udelay(1); 851 udelay(1);
852 852
853 if (phy->autoneg_wait_to_complete) { 853 if (phy->autoneg_wait_to_complete) {
854 hw_dbg(hw, 854 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
855 "Waiting for forced speed/duplex link on IGP phy.\n");
856 855
857 ret_val = igb_phy_has_link(hw, 856 ret_val = igb_phy_has_link(hw,
858 PHY_FORCE_LIMIT, 857 PHY_FORCE_LIMIT,
@@ -862,7 +861,7 @@ s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
862 goto out; 861 goto out;
863 862
864 if (!link) 863 if (!link)
865 hw_dbg(hw, "Link taking longer than expected.\n"); 864 hw_dbg("Link taking longer than expected.\n");
866 865
867 /* Try once more */ 866 /* Try once more */
868 ret_val = igb_phy_has_link(hw, 867 ret_val = igb_phy_has_link(hw,
@@ -878,7 +877,7 @@ out:
878} 877}
879 878
880/** 879/**
881 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 880 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
882 * @hw: pointer to the HW structure 881 * @hw: pointer to the HW structure
883 * 882 *
884 * Calls the PHY setup function to force speed and duplex. Clears the 883 * Calls the PHY setup function to force speed and duplex. Clears the
@@ -909,7 +908,7 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
909 if (ret_val) 908 if (ret_val)
910 goto out; 909 goto out;
911 910
912 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data); 911 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
913 912
914 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); 913 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
915 if (ret_val) 914 if (ret_val)
@@ -927,8 +926,7 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
927 udelay(1); 926 udelay(1);
928 927
929 if (phy->autoneg_wait_to_complete) { 928 if (phy->autoneg_wait_to_complete) {
930 hw_dbg(hw, 929 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
931 "Waiting for forced speed/duplex link on M88 phy.\n");
932 930
933 ret_val = igb_phy_has_link(hw, 931 ret_val = igb_phy_has_link(hw,
934 PHY_FORCE_LIMIT, 932 PHY_FORCE_LIMIT,
@@ -993,7 +991,7 @@ out:
993} 991}
994 992
995/** 993/**
996 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 994 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
997 * @hw: pointer to the HW structure 995 * @hw: pointer to the HW structure
998 * @phy_ctrl: pointer to current value of PHY_CONTROL 996 * @phy_ctrl: pointer to current value of PHY_CONTROL
999 * 997 *
@@ -1028,11 +1026,11 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1028 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1026 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1029 ctrl &= ~E1000_CTRL_FD; 1027 ctrl &= ~E1000_CTRL_FD;
1030 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1028 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1031 hw_dbg(hw, "Half Duplex\n"); 1029 hw_dbg("Half Duplex\n");
1032 } else { 1030 } else {
1033 ctrl |= E1000_CTRL_FD; 1031 ctrl |= E1000_CTRL_FD;
1034 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1032 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1035 hw_dbg(hw, "Full Duplex\n"); 1033 hw_dbg("Full Duplex\n");
1036 } 1034 }
1037 1035
1038 /* Forcing 10mb or 100mb? */ 1036 /* Forcing 10mb or 100mb? */
@@ -1040,12 +1038,12 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1040 ctrl |= E1000_CTRL_SPD_100; 1038 ctrl |= E1000_CTRL_SPD_100;
1041 *phy_ctrl |= MII_CR_SPEED_100; 1039 *phy_ctrl |= MII_CR_SPEED_100;
1042 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1040 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1043 hw_dbg(hw, "Forcing 100mb\n"); 1041 hw_dbg("Forcing 100mb\n");
1044 } else { 1042 } else {
1045 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1043 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1046 *phy_ctrl |= MII_CR_SPEED_10; 1044 *phy_ctrl |= MII_CR_SPEED_10;
1047 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1045 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1048 hw_dbg(hw, "Forcing 10mb\n"); 1046 hw_dbg("Forcing 10mb\n");
1049 } 1047 }
1050 1048
1051 igb_config_collision_dist(hw); 1049 igb_config_collision_dist(hw);
@@ -1054,7 +1052,7 @@ static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1054} 1052}
1055 1053
1056/** 1054/**
1057 * e1000_set_d3_lplu_state - Sets low power link up state for D3 1055 * igb_set_d3_lplu_state - Sets low power link up state for D3
1058 * @hw: pointer to the HW structure 1056 * @hw: pointer to the HW structure
1059 * @active: boolean used to enable/disable lplu 1057 * @active: boolean used to enable/disable lplu
1060 * 1058 *
@@ -1146,7 +1144,7 @@ out:
1146} 1144}
1147 1145
1148/** 1146/**
1149 * e1000_check_downshift - Checks whether a downshift in speed occured 1147 * igb_check_downshift - Checks whether a downshift in speed occured
1150 * @hw: pointer to the HW structure 1148 * @hw: pointer to the HW structure
1151 * 1149 *
1152 * Success returns 0, Failure returns 1 1150 * Success returns 0, Failure returns 1
@@ -1188,7 +1186,7 @@ out:
1188} 1186}
1189 1187
1190/** 1188/**
1191 * e1000_check_polarity_m88 - Checks the polarity. 1189 * igb_check_polarity_m88 - Checks the polarity.
1192 * @hw: pointer to the HW structure 1190 * @hw: pointer to the HW structure
1193 * 1191 *
1194 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1192 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
@@ -1212,7 +1210,7 @@ static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1212} 1210}
1213 1211
1214/** 1212/**
1215 * e1000_check_polarity_igp - Checks the polarity. 1213 * igb_check_polarity_igp - Checks the polarity.
1216 * @hw: pointer to the HW structure 1214 * @hw: pointer to the HW structure
1217 * 1215 *
1218 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1216 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
@@ -1260,7 +1258,7 @@ out:
1260} 1258}
1261 1259
1262/** 1260/**
1263 * e1000_wait_autoneg - Wait for auto-neg compeletion 1261 * igb_wait_autoneg - Wait for auto-neg compeletion
1264 * @hw: pointer to the HW structure 1262 * @hw: pointer to the HW structure
1265 * 1263 *
1266 * Waits for auto-negotiation to complete or for the auto-negotiation time 1264 * Waits for auto-negotiation to complete or for the auto-negotiation time
@@ -1292,7 +1290,7 @@ static s32 igb_wait_autoneg(struct e1000_hw *hw)
1292} 1290}
1293 1291
1294/** 1292/**
1295 * e1000_phy_has_link - Polls PHY for link 1293 * igb_phy_has_link - Polls PHY for link
1296 * @hw: pointer to the HW structure 1294 * @hw: pointer to the HW structure
1297 * @iterations: number of times to poll for link 1295 * @iterations: number of times to poll for link
1298 * @usec_interval: delay between polling attempts 1296 * @usec_interval: delay between polling attempts
@@ -1332,7 +1330,7 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1332} 1330}
1333 1331
1334/** 1332/**
1335 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1333 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1336 * @hw: pointer to the HW structure 1334 * @hw: pointer to the HW structure
1337 * 1335 *
1338 * Reads the PHY specific status register to retrieve the cable length 1336 * Reads the PHY specific status register to retrieve the cable length
@@ -1369,7 +1367,7 @@ out:
1369} 1367}
1370 1368
1371/** 1369/**
1372 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1370 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1373 * @hw: pointer to the HW structure 1371 * @hw: pointer to the HW structure
1374 * 1372 *
1375 * The automatic gain control (agc) normalizes the amplitude of the 1373 * The automatic gain control (agc) normalizes the amplitude of the
@@ -1442,7 +1440,7 @@ out:
1442} 1440}
1443 1441
1444/** 1442/**
1445 * e1000_get_phy_info_m88 - Retrieve PHY information 1443 * igb_get_phy_info_m88 - Retrieve PHY information
1446 * @hw: pointer to the HW structure 1444 * @hw: pointer to the HW structure
1447 * 1445 *
1448 * Valid for only copper links. Read the PHY status register (sticky read) 1446 * Valid for only copper links. Read the PHY status register (sticky read)
@@ -1459,7 +1457,7 @@ s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1459 bool link; 1457 bool link;
1460 1458
1461 if (hw->phy.media_type != e1000_media_type_copper) { 1459 if (hw->phy.media_type != e1000_media_type_copper) {
1462 hw_dbg(hw, "Phy info is only valid for copper media\n"); 1460 hw_dbg("Phy info is only valid for copper media\n");
1463 ret_val = -E1000_ERR_CONFIG; 1461 ret_val = -E1000_ERR_CONFIG;
1464 goto out; 1462 goto out;
1465 } 1463 }
@@ -1469,7 +1467,7 @@ s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1469 goto out; 1467 goto out;
1470 1468
1471 if (!link) { 1469 if (!link) {
1472 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1470 hw_dbg("Phy info is only valid if link is up\n");
1473 ret_val = -E1000_ERR_CONFIG; 1471 ret_val = -E1000_ERR_CONFIG;
1474 goto out; 1472 goto out;
1475 } 1473 }
@@ -1523,7 +1521,7 @@ out:
1523} 1521}
1524 1522
1525/** 1523/**
1526 * e1000_get_phy_info_igp - Retrieve igp PHY information 1524 * igb_get_phy_info_igp - Retrieve igp PHY information
1527 * @hw: pointer to the HW structure 1525 * @hw: pointer to the HW structure
1528 * 1526 *
1529 * Read PHY status to determine if link is up. If link is up, then 1527 * Read PHY status to determine if link is up. If link is up, then
@@ -1543,7 +1541,7 @@ s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1543 goto out; 1541 goto out;
1544 1542
1545 if (!link) { 1543 if (!link) {
1546 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1544 hw_dbg("Phy info is only valid if link is up\n");
1547 ret_val = -E1000_ERR_CONFIG; 1545 ret_val = -E1000_ERR_CONFIG;
1548 goto out; 1546 goto out;
1549 } 1547 }
@@ -1590,7 +1588,7 @@ out:
1590} 1588}
1591 1589
1592/** 1590/**
1593 * e1000_phy_sw_reset - PHY software reset 1591 * igb_phy_sw_reset - PHY software reset
1594 * @hw: pointer to the HW structure 1592 * @hw: pointer to the HW structure
1595 * 1593 *
1596 * Does a software reset of the PHY by reading the PHY control register and 1594 * Does a software reset of the PHY by reading the PHY control register and
@@ -1617,7 +1615,7 @@ out:
1617} 1615}
1618 1616
1619/** 1617/**
1620 * e1000_phy_hw_reset - PHY hardware reset 1618 * igb_phy_hw_reset - PHY hardware reset
1621 * @hw: pointer to the HW structure 1619 * @hw: pointer to the HW structure
1622 * 1620 *
1623 * Verify the reset block is not blocking us from resetting. Acquire 1621 * Verify the reset block is not blocking us from resetting. Acquire
@@ -1663,7 +1661,7 @@ out:
1663/* Internal function pointers */ 1661/* Internal function pointers */
1664 1662
1665/** 1663/**
1666 * e1000_get_phy_cfg_done - Generic PHY configuration done 1664 * igb_get_phy_cfg_done - Generic PHY configuration done
1667 * @hw: pointer to the HW structure 1665 * @hw: pointer to the HW structure
1668 * 1666 *
1669 * Return success if silicon family did not implement a family specific 1667 * Return success if silicon family did not implement a family specific
@@ -1678,7 +1676,7 @@ static s32 igb_get_phy_cfg_done(struct e1000_hw *hw)
1678} 1676}
1679 1677
1680/** 1678/**
1681 * e1000_release_phy - Generic release PHY 1679 * igb_release_phy - Generic release PHY
1682 * @hw: pointer to the HW structure 1680 * @hw: pointer to the HW structure
1683 * 1681 *
1684 * Return if silicon family does not require a semaphore when accessing the 1682 * Return if silicon family does not require a semaphore when accessing the
@@ -1691,7 +1689,7 @@ static void igb_release_phy(struct e1000_hw *hw)
1691} 1689}
1692 1690
1693/** 1691/**
1694 * e1000_acquire_phy - Generic acquire PHY 1692 * igb_acquire_phy - Generic acquire PHY
1695 * @hw: pointer to the HW structure 1693 * @hw: pointer to the HW structure
1696 * 1694 *
1697 * Return success if silicon family does not require a semaphore when 1695 * Return success if silicon family does not require a semaphore when
@@ -1706,7 +1704,7 @@ static s32 igb_acquire_phy(struct e1000_hw *hw)
1706} 1704}
1707 1705
1708/** 1706/**
1709 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 1707 * igb_phy_force_speed_duplex - Generic force PHY speed/duplex
1710 * @hw: pointer to the HW structure 1708 * @hw: pointer to the HW structure
1711 * 1709 *
1712 * When the silicon family has not implemented a forced speed/duplex 1710 * When the silicon family has not implemented a forced speed/duplex
@@ -1721,14 +1719,14 @@ s32 igb_phy_force_speed_duplex(struct e1000_hw *hw)
1721} 1719}
1722 1720
1723/** 1721/**
1724 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 1722 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
1725 * @hw: pointer to the HW structure 1723 * @hw: pointer to the HW structure
1726 * 1724 *
1727 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 1725 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1728 **/ 1726 **/
1729s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 1727s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1730{ 1728{
1731 hw_dbg(hw, "Running IGP 3 PHY init script\n"); 1729 hw_dbg("Running IGP 3 PHY init script\n");
1732 1730
1733 /* PHY init IGP 3 */ 1731 /* PHY init IGP 3 */
1734 /* Enable rise/fall, 10-mode work in class-A */ 1732 /* Enable rise/fall, 10-mode work in class-A */
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index ff187b73c69e..b95093d24c09 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -56,6 +56,9 @@
56#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 56#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
57#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 57#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
58#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 58#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
59#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
60#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
61#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
59#define E1000_TCTL 0x00400 /* TX Control - RW */ 62#define E1000_TCTL 0x00400 /* TX Control - RW */
60#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 63#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
61#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 64#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
@@ -217,6 +220,7 @@
217#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 220#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
218#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 221#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
219#define E1000_RA 0x05400 /* Receive Address - RW Array */ 222#define E1000_RA 0x05400 /* Receive Address - RW Array */
223#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */
220#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 224#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
221#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ 225#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */
222#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 226#define E1000_WUC 0x05800 /* Wakeup Control - RW */
@@ -235,6 +239,8 @@
235#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 239#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
236#define E1000_SWSM 0x05B50 /* SW Semaphore */ 240#define E1000_SWSM 0x05B50 /* SW Semaphore */
237#define E1000_FWSM 0x05B54 /* FW Semaphore */ 241#define E1000_FWSM 0x05B54 /* FW Semaphore */
242#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
243#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
238#define E1000_HICR 0x08F00 /* Host Inteface Control */ 244#define E1000_HICR 0x08F00 /* Host Inteface Control */
239 245
240/* RSS registers */ 246/* RSS registers */
@@ -256,7 +262,8 @@
256#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 262#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
257#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ 263#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
258 264
259#define E1000_REGISTER(a, reg) reg 265#define E1000_REGISTER(a, reg) (((a)->mac.type < e1000_82576) \
266 ? reg : e1000_translate_register_82576(reg))
260 267
261#define wr32(reg, value) (writel(value, hw->hw_addr + reg)) 268#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
262#define rd32(reg) (readl(hw->hw_addr + reg)) 269#define rd32(reg) (readl(hw->hw_addr + reg))
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h
index 6b2e7d351d65..4ff6f0567f3f 100644
--- a/drivers/net/igb/igb.h
+++ b/drivers/net/igb/igb.h
@@ -36,12 +36,20 @@
36 36
37struct igb_adapter; 37struct igb_adapter;
38 38
39#ifdef CONFIG_IGB_LRO
40#include <linux/inet_lro.h>
41#define MAX_LRO_AGGR 32
42#define MAX_LRO_DESCRIPTORS 8
43#endif
44
39/* Interrupt defines */ 45/* Interrupt defines */
40#define IGB_MAX_TX_CLEAN 72 46#define IGB_MAX_TX_CLEAN 72
41 47
42#define IGB_MIN_DYN_ITR 3000 48#define IGB_MIN_DYN_ITR 3000
43#define IGB_MAX_DYN_ITR 96000 49#define IGB_MAX_DYN_ITR 96000
44#define IGB_START_ITR 6000 50
51/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
52#define IGB_START_ITR 648
45 53
46#define IGB_DYN_ITR_PACKET_THRESHOLD 2 54#define IGB_DYN_ITR_PACKET_THRESHOLD 2
47#define IGB_DYN_ITR_LENGTH_LOW 200 55#define IGB_DYN_ITR_LENGTH_LOW 200
@@ -62,6 +70,7 @@ struct igb_adapter;
62 70
63/* Transmit and receive queues */ 71/* Transmit and receive queues */
64#define IGB_MAX_RX_QUEUES 4 72#define IGB_MAX_RX_QUEUES 4
73#define IGB_MAX_TX_QUEUES 4
65 74
66/* RX descriptor control thresholds. 75/* RX descriptor control thresholds.
67 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 76 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
@@ -124,6 +133,7 @@ struct igb_buffer {
124 struct { 133 struct {
125 struct page *page; 134 struct page *page;
126 u64 page_dma; 135 u64 page_dma;
136 unsigned int page_offset;
127 }; 137 };
128 }; 138 };
129}; 139};
@@ -150,24 +160,26 @@ struct igb_ring {
150 u16 itr_register; 160 u16 itr_register;
151 u16 cpu; 161 u16 cpu;
152 162
163 int queue_index;
153 unsigned int total_bytes; 164 unsigned int total_bytes;
154 unsigned int total_packets; 165 unsigned int total_packets;
155 166
156 union { 167 union {
157 /* TX */ 168 /* TX */
158 struct { 169 struct {
159 spinlock_t tx_clean_lock; 170 struct igb_queue_stats tx_stats;
160 spinlock_t tx_lock;
161 bool detect_tx_hung; 171 bool detect_tx_hung;
162 }; 172 };
163 /* RX */ 173 /* RX */
164 struct { 174 struct {
165 /* arrays of page information for packet split */
166 struct sk_buff *pending_skb;
167 int pending_skb_page;
168 int no_itr_adjust;
169 struct igb_queue_stats rx_stats; 175 struct igb_queue_stats rx_stats;
170 struct napi_struct napi; 176 struct napi_struct napi;
177 int set_itr;
178 struct igb_ring *buddy;
179#ifdef CONFIG_IGB_LRO
180 struct net_lro_mgr lro_mgr;
181 bool lro_used;
182#endif
171 }; 183 };
172 }; 184 };
173 185
@@ -210,7 +222,6 @@ struct igb_adapter {
210 u32 itr_setting; 222 u32 itr_setting;
211 u16 tx_itr; 223 u16 tx_itr;
212 u16 rx_itr; 224 u16 rx_itr;
213 int set_itr;
214 225
215 struct work_struct reset_task; 226 struct work_struct reset_task;
216 struct work_struct watchdog_task; 227 struct work_struct watchdog_task;
@@ -265,14 +276,34 @@ struct igb_adapter {
265 int msg_enable; 276 int msg_enable;
266 struct msix_entry *msix_entries; 277 struct msix_entry *msix_entries;
267 u32 eims_enable_mask; 278 u32 eims_enable_mask;
279 u32 eims_other;
268 280
269 /* to not mess up cache alignment, always add to the bottom */ 281 /* to not mess up cache alignment, always add to the bottom */
270 unsigned long state; 282 unsigned long state;
271 unsigned int msi_enabled; 283 unsigned int flags;
272
273 u32 eeprom_wol; 284 u32 eeprom_wol;
285
286 /* for ioport free */
287 int bars;
288 int need_ioport;
289
290 struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
291#ifdef CONFIG_IGB_LRO
292 unsigned int lro_max_aggr;
293 unsigned int lro_aggregated;
294 unsigned int lro_flushed;
295 unsigned int lro_no_desc;
296#endif
274}; 297};
275 298
299#define IGB_FLAG_HAS_MSI (1 << 0)
300#define IGB_FLAG_MSI_ENABLE (1 << 1)
301#define IGB_FLAG_HAS_DCA (1 << 2)
302#define IGB_FLAG_DCA_ENABLED (1 << 3)
303#define IGB_FLAG_IN_NETPOLL (1 << 5)
304#define IGB_FLAG_QUAD_PORT_A (1 << 6)
305#define IGB_FLAG_NEED_CTX_IDX (1 << 7)
306
276enum e1000_state_t { 307enum e1000_state_t {
277 __IGB_TESTING, 308 __IGB_TESTING,
278 __IGB_RESETTING, 309 __IGB_RESETTING,
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index 0447f9bcd27a..11aee1309951 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -93,13 +93,16 @@ static const struct igb_stats igb_gstrings_stats[] = {
93 { "tx_smbus", IGB_STAT(stats.mgptc) }, 93 { "tx_smbus", IGB_STAT(stats.mgptc) },
94 { "rx_smbus", IGB_STAT(stats.mgprc) }, 94 { "rx_smbus", IGB_STAT(stats.mgprc) },
95 { "dropped_smbus", IGB_STAT(stats.mgpdc) }, 95 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
96#ifdef CONFIG_IGB_LRO
97 { "lro_aggregated", IGB_STAT(lro_aggregated) },
98 { "lro_flushed", IGB_STAT(lro_flushed) },
99 { "lro_no_desc", IGB_STAT(lro_no_desc) },
100#endif
96}; 101};
97 102
98#define IGB_QUEUE_STATS_LEN \ 103#define IGB_QUEUE_STATS_LEN \
99 ((((((struct igb_adapter *)netdev->priv)->num_rx_queues > 1) ? \ 104 ((((struct igb_adapter *)netdev->priv)->num_rx_queues + \
100 ((struct igb_adapter *)netdev->priv)->num_rx_queues : 0) + \ 105 ((struct igb_adapter *)netdev->priv)->num_tx_queues) * \
101 (((((struct igb_adapter *)netdev->priv)->num_tx_queues > 1) ? \
102 ((struct igb_adapter *)netdev->priv)->num_tx_queues : 0))) * \
103 (sizeof(struct igb_queue_stats) / sizeof(u64))) 106 (sizeof(struct igb_queue_stats) / sizeof(u64)))
104#define IGB_GLOBAL_STATS_LEN \ 107#define IGB_GLOBAL_STATS_LEN \
105 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats) 108 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
@@ -829,8 +832,9 @@ err_setup:
829/* ethtool register test data */ 832/* ethtool register test data */
830struct igb_reg_test { 833struct igb_reg_test {
831 u16 reg; 834 u16 reg;
832 u8 array_len; 835 u16 reg_offset;
833 u8 test_type; 836 u16 array_len;
837 u16 test_type;
834 u32 mask; 838 u32 mask;
835 u32 write; 839 u32 write;
836}; 840};
@@ -852,34 +856,72 @@ struct igb_reg_test {
852#define TABLE64_TEST_LO 5 856#define TABLE64_TEST_LO 5
853#define TABLE64_TEST_HI 6 857#define TABLE64_TEST_HI 6
854 858
855/* default register test */ 859/* 82576 reg test */
860static struct igb_reg_test reg_test_82576[] = {
861 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
862 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
863 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
864 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
865 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
866 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
867 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
868 { E1000_RDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
869 { E1000_RDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
870 { E1000_RDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
871 /* Enable all four RX queues before testing. */
872 { E1000_RXDCTL(0), 0x100, 1, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
873 /* RDH is read-only for 82576, only test RDT. */
874 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
875 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
876 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
877 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
878 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
879 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
880 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
881 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
882 { E1000_TDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
883 { E1000_TDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
884 { E1000_TDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
885 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
886 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
887 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
888 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
889 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
890 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
891 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
892 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
893 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
894 { 0, 0, 0, 0 }
895};
896
897/* 82575 register test */
856static struct igb_reg_test reg_test_82575[] = { 898static struct igb_reg_test reg_test_82575[] = {
857 { E1000_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 899 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
858 { E1000_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 900 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
859 { E1000_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 901 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
860 { E1000_VET, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 902 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
861 { E1000_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 903 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
862 { E1000_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 904 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
863 { E1000_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 905 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
864 /* Enable all four RX queues before testing. */ 906 /* Enable all four RX queues before testing. */
865 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 907 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
866 /* RDH is read-only for 82575, only test RDT. */ 908 /* RDH is read-only for 82575, only test RDT. */
867 { E1000_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 909 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
868 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 910 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
869 { E1000_FCRTH, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 911 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
870 { E1000_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 912 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
871 { E1000_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 913 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
872 { E1000_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 914 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
873 { E1000_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 915 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
874 { E1000_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 916 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
875 { E1000_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 917 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
876 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 918 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
877 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 919 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
878 { E1000_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 920 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
879 { E1000_TXCW, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 921 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
880 { E1000_RA, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 922 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
881 { E1000_RA, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 923 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
882 { E1000_MTA, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 924 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
883 { 0, 0, 0, 0 } 925 { 0, 0, 0, 0 }
884}; 926};
885 927
@@ -939,7 +981,15 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
939 u32 i, toggle; 981 u32 i, toggle;
940 982
941 toggle = 0x7FFFF3FF; 983 toggle = 0x7FFFF3FF;
942 test = reg_test_82575; 984
985 switch (adapter->hw.mac.type) {
986 case e1000_82576:
987 test = reg_test_82576;
988 break;
989 default:
990 test = reg_test_82575;
991 break;
992 }
943 993
944 /* Because the status register is such a special case, 994 /* Because the status register is such a special case,
945 * we handle it separately from the rest of the register 995 * we handle it separately from the rest of the register
@@ -966,19 +1016,19 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
966 for (i = 0; i < test->array_len; i++) { 1016 for (i = 0; i < test->array_len; i++) {
967 switch (test->test_type) { 1017 switch (test->test_type) {
968 case PATTERN_TEST: 1018 case PATTERN_TEST:
969 REG_PATTERN_TEST(test->reg + (i * 0x100), 1019 REG_PATTERN_TEST(test->reg + (i * test->reg_offset),
970 test->mask, 1020 test->mask,
971 test->write); 1021 test->write);
972 break; 1022 break;
973 case SET_READ_TEST: 1023 case SET_READ_TEST:
974 REG_SET_AND_CHECK(test->reg + (i * 0x100), 1024 REG_SET_AND_CHECK(test->reg + (i * test->reg_offset),
975 test->mask, 1025 test->mask,
976 test->write); 1026 test->write);
977 break; 1027 break;
978 case WRITE_NO_TEST: 1028 case WRITE_NO_TEST:
979 writel(test->write, 1029 writel(test->write,
980 (adapter->hw.hw_addr + test->reg) 1030 (adapter->hw.hw_addr + test->reg)
981 + (i * 0x100)); 1031 + (i * test->reg_offset));
982 break; 1032 break;
983 case TABLE32_TEST: 1033 case TABLE32_TEST:
984 REG_PATTERN_TEST(test->reg + (i * 4), 1034 REG_PATTERN_TEST(test->reg + (i * 4),
@@ -1052,7 +1102,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1052 if (adapter->msix_entries) { 1102 if (adapter->msix_entries) {
1053 /* NOTE: we don't test MSI-X interrupts here, yet */ 1103 /* NOTE: we don't test MSI-X interrupts here, yet */
1054 return 0; 1104 return 0;
1055 } else if (adapter->msi_enabled) { 1105 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1056 shared_int = false; 1106 shared_int = false;
1057 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) { 1107 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1058 *data = 1; 1108 *data = 1;
@@ -1394,13 +1444,39 @@ static int igb_set_phy_loopback(struct igb_adapter *adapter)
1394static int igb_setup_loopback_test(struct igb_adapter *adapter) 1444static int igb_setup_loopback_test(struct igb_adapter *adapter)
1395{ 1445{
1396 struct e1000_hw *hw = &adapter->hw; 1446 struct e1000_hw *hw = &adapter->hw;
1397 u32 rctl; 1447 u32 reg;
1398 1448
1399 if (hw->phy.media_type == e1000_media_type_fiber || 1449 if (hw->phy.media_type == e1000_media_type_fiber ||
1400 hw->phy.media_type == e1000_media_type_internal_serdes) { 1450 hw->phy.media_type == e1000_media_type_internal_serdes) {
1401 rctl = rd32(E1000_RCTL); 1451 reg = rd32(E1000_RCTL);
1402 rctl |= E1000_RCTL_LBM_TCVR; 1452 reg |= E1000_RCTL_LBM_TCVR;
1403 wr32(E1000_RCTL, rctl); 1453 wr32(E1000_RCTL, reg);
1454
1455 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1456
1457 reg = rd32(E1000_CTRL);
1458 reg &= ~(E1000_CTRL_RFCE |
1459 E1000_CTRL_TFCE |
1460 E1000_CTRL_LRST);
1461 reg |= E1000_CTRL_SLU |
1462 E1000_CTRL_FD;
1463 wr32(E1000_CTRL, reg);
1464
1465 /* Unset switch control to serdes energy detect */
1466 reg = rd32(E1000_CONNSW);
1467 reg &= ~E1000_CONNSW_ENRGSRC;
1468 wr32(E1000_CONNSW, reg);
1469
1470 /* Set PCS register for forced speed */
1471 reg = rd32(E1000_PCS_LCTL);
1472 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1473 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1474 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1475 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1476 E1000_PCS_LCTL_FSD | /* Force Speed */
1477 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1478 wr32(E1000_PCS_LCTL, reg);
1479
1404 return 0; 1480 return 0;
1405 } else if (hw->phy.media_type == e1000_media_type_copper) { 1481 } else if (hw->phy.media_type == e1000_media_type_copper) {
1406 return igb_set_phy_loopback(adapter); 1482 return igb_set_phy_loopback(adapter);
@@ -1660,6 +1736,8 @@ static int igb_wol_exclusion(struct igb_adapter *adapter,
1660 wol->supported = 0; 1736 wol->supported = 0;
1661 break; 1737 break;
1662 case E1000_DEV_ID_82575EB_FIBER_SERDES: 1738 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1739 case E1000_DEV_ID_82576_FIBER:
1740 case E1000_DEV_ID_82576_SERDES:
1663 /* Wake events not supported on port B */ 1741 /* Wake events not supported on port B */
1664 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { 1742 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1665 wol->supported = 0; 1743 wol->supported = 0;
@@ -1668,6 +1746,15 @@ static int igb_wol_exclusion(struct igb_adapter *adapter,
1668 /* return success for non excluded adapter ports */ 1746 /* return success for non excluded adapter ports */
1669 retval = 0; 1747 retval = 0;
1670 break; 1748 break;
1749 case E1000_DEV_ID_82576_QUAD_COPPER:
1750 /* quad port adapters only support WoL on port A */
1751 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1752 wol->supported = 0;
1753 break;
1754 }
1755 /* return success for non excluded adapter ports */
1756 retval = 0;
1757 break;
1671 default: 1758 default:
1672 /* dual port cards only support WoL on port A from now on 1759 /* dual port cards only support WoL on port A from now on
1673 * unless it was enabled in the eeprom for port B 1760 * unless it was enabled in the eeprom for port B
@@ -1774,6 +1861,8 @@ static int igb_set_coalesce(struct net_device *netdev,
1774 struct ethtool_coalesce *ec) 1861 struct ethtool_coalesce *ec)
1775{ 1862{
1776 struct igb_adapter *adapter = netdev_priv(netdev); 1863 struct igb_adapter *adapter = netdev_priv(netdev);
1864 struct e1000_hw *hw = &adapter->hw;
1865 int i;
1777 1866
1778 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 1867 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1779 ((ec->rx_coalesce_usecs > 3) && 1868 ((ec->rx_coalesce_usecs > 3) &&
@@ -1782,13 +1871,16 @@ static int igb_set_coalesce(struct net_device *netdev,
1782 return -EINVAL; 1871 return -EINVAL;
1783 1872
1784 /* convert to rate of irq's per second */ 1873 /* convert to rate of irq's per second */
1785 if (ec->rx_coalesce_usecs <= 3) 1874 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1786 adapter->itr_setting = ec->rx_coalesce_usecs; 1875 adapter->itr_setting = ec->rx_coalesce_usecs;
1787 else 1876 adapter->itr = IGB_START_ITR;
1788 adapter->itr_setting = (1000000 / ec->rx_coalesce_usecs); 1877 } else {
1878 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1879 adapter->itr = adapter->itr_setting;
1880 }
1789 1881
1790 if (netif_running(netdev)) 1882 for (i = 0; i < adapter->num_rx_queues; i++)
1791 igb_reinit_locked(adapter); 1883 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1792 1884
1793 return 0; 1885 return 0;
1794} 1886}
@@ -1801,7 +1893,7 @@ static int igb_get_coalesce(struct net_device *netdev,
1801 if (adapter->itr_setting <= 3) 1893 if (adapter->itr_setting <= 3)
1802 ec->rx_coalesce_usecs = adapter->itr_setting; 1894 ec->rx_coalesce_usecs = adapter->itr_setting;
1803 else 1895 else
1804 ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting; 1896 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1805 1897
1806 return 0; 1898 return 0;
1807} 1899}
@@ -1835,6 +1927,18 @@ static void igb_get_ethtool_stats(struct net_device *netdev,
1835 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64); 1927 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1836 int j; 1928 int j;
1837 int i; 1929 int i;
1930#ifdef CONFIG_IGB_LRO
1931 int aggregated = 0, flushed = 0, no_desc = 0;
1932
1933 for (i = 0; i < adapter->num_rx_queues; i++) {
1934 aggregated += adapter->rx_ring[i].lro_mgr.stats.aggregated;
1935 flushed += adapter->rx_ring[i].lro_mgr.stats.flushed;
1936 no_desc += adapter->rx_ring[i].lro_mgr.stats.no_desc;
1937 }
1938 adapter->lro_aggregated = aggregated;
1939 adapter->lro_flushed = flushed;
1940 adapter->lro_no_desc = no_desc;
1941#endif
1838 1942
1839 igb_update_stats(adapter); 1943 igb_update_stats(adapter);
1840 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 1944 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
@@ -1842,6 +1946,13 @@ static void igb_get_ethtool_stats(struct net_device *netdev,
1842 data[i] = (igb_gstrings_stats[i].sizeof_stat == 1946 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1843 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1947 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1844 } 1948 }
1949 for (j = 0; j < adapter->num_tx_queues; j++) {
1950 int k;
1951 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1952 for (k = 0; k < stat_count; k++)
1953 data[i + k] = queue_stat[k];
1954 i += k;
1955 }
1845 for (j = 0; j < adapter->num_rx_queues; j++) { 1956 for (j = 0; j < adapter->num_rx_queues; j++) {
1846 int k; 1957 int k;
1847 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats; 1958 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index e79a26a886c8..1b7cb29fe68e 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -41,22 +41,27 @@
41#include <linux/delay.h> 41#include <linux/delay.h>
42#include <linux/interrupt.h> 42#include <linux/interrupt.h>
43#include <linux/if_ether.h> 43#include <linux/if_ether.h>
44 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
45#include "igb.h" 47#include "igb.h"
46 48
47#define DRV_VERSION "1.0.8-k2" 49#define DRV_VERSION "1.2.45-k2"
48char igb_driver_name[] = "igb"; 50char igb_driver_name[] = "igb";
49char igb_driver_version[] = DRV_VERSION; 51char igb_driver_version[] = DRV_VERSION;
50static const char igb_driver_string[] = 52static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver"; 53 "Intel(R) Gigabit Ethernet Network Driver";
52static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation."; 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
53
54 55
55static const struct e1000_info *igb_info_tbl[] = { 56static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info, 57 [board_82575] = &e1000_82575_info,
57}; 58};
58 59
59static struct pci_device_id igb_pci_tbl[] = { 60static struct pci_device_id igb_pci_tbl[] = {
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
@@ -71,8 +76,8 @@ static int igb_setup_all_tx_resources(struct igb_adapter *);
71static int igb_setup_all_rx_resources(struct igb_adapter *); 76static int igb_setup_all_rx_resources(struct igb_adapter *);
72static void igb_free_all_tx_resources(struct igb_adapter *); 77static void igb_free_all_tx_resources(struct igb_adapter *);
73static void igb_free_all_rx_resources(struct igb_adapter *); 78static void igb_free_all_rx_resources(struct igb_adapter *);
74static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *); 79static void igb_free_tx_resources(struct igb_ring *);
75static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *); 80static void igb_free_rx_resources(struct igb_ring *);
76void igb_update_stats(struct igb_adapter *); 81void igb_update_stats(struct igb_adapter *);
77static int igb_probe(struct pci_dev *, const struct pci_device_id *); 82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78static void __devexit igb_remove(struct pci_dev *pdev); 83static void __devexit igb_remove(struct pci_dev *pdev);
@@ -84,8 +89,8 @@ static void igb_configure_rx(struct igb_adapter *);
84static void igb_setup_rctl(struct igb_adapter *); 89static void igb_setup_rctl(struct igb_adapter *);
85static void igb_clean_all_tx_rings(struct igb_adapter *); 90static void igb_clean_all_tx_rings(struct igb_adapter *);
86static void igb_clean_all_rx_rings(struct igb_adapter *); 91static void igb_clean_all_rx_rings(struct igb_adapter *);
87static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *); 92static void igb_clean_tx_ring(struct igb_ring *);
88static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *); 93static void igb_clean_rx_ring(struct igb_ring *);
89static void igb_set_multi(struct net_device *); 94static void igb_set_multi(struct net_device *);
90static void igb_update_phy_info(unsigned long); 95static void igb_update_phy_info(unsigned long);
91static void igb_watchdog(unsigned long); 96static void igb_watchdog(unsigned long);
@@ -102,12 +107,18 @@ static irqreturn_t igb_msix_other(int irq, void *);
102static irqreturn_t igb_msix_rx(int irq, void *); 107static irqreturn_t igb_msix_rx(int irq, void *);
103static irqreturn_t igb_msix_tx(int irq, void *); 108static irqreturn_t igb_msix_tx(int irq, void *);
104static int igb_clean_rx_ring_msix(struct napi_struct *, int); 109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
105static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *); 110#ifdef CONFIG_DCA
106static int igb_clean(struct napi_struct *, int); 111static void igb_update_rx_dca(struct igb_ring *);
107static bool igb_clean_rx_irq_adv(struct igb_adapter *, 112static void igb_update_tx_dca(struct igb_ring *);
108 struct igb_ring *, int *, int); 113static void igb_setup_dca(struct igb_adapter *);
109static void igb_alloc_rx_buffers_adv(struct igb_adapter *, 114#endif /* CONFIG_DCA */
110 struct igb_ring *, int); 115static bool igb_clean_tx_irq(struct igb_ring *);
116static int igb_poll(struct napi_struct *, int);
117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
119#ifdef CONFIG_IGB_LRO
120static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
121#endif
111static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 122static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
112static void igb_tx_timeout(struct net_device *); 123static void igb_tx_timeout(struct net_device *);
113static void igb_reset_task(struct work_struct *); 124static void igb_reset_task(struct work_struct *);
@@ -121,6 +132,14 @@ static int igb_suspend(struct pci_dev *, pm_message_t);
121static int igb_resume(struct pci_dev *); 132static int igb_resume(struct pci_dev *);
122#endif 133#endif
123static void igb_shutdown(struct pci_dev *); 134static void igb_shutdown(struct pci_dev *);
135#ifdef CONFIG_DCA
136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
124 143
125#ifdef CONFIG_NET_POLL_CONTROLLER 144#ifdef CONFIG_NET_POLL_CONTROLLER
126/* for netdump / net console */ 145/* for netdump / net console */
@@ -153,6 +172,8 @@ static struct pci_driver igb_driver = {
153 .err_handler = &igb_err_handler 172 .err_handler = &igb_err_handler
154}; 173};
155 174
175static int global_quad_port_a; /* global quad port a indication */
176
156MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
157MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
158MODULE_LICENSE("GPL"); 179MODULE_LICENSE("GPL");
@@ -184,7 +205,12 @@ static int __init igb_init_module(void)
184 205
185 printk(KERN_INFO "%s\n", igb_copyright); 206 printk(KERN_INFO "%s\n", igb_copyright);
186 207
208 global_quad_port_a = 0;
209
187 ret = pci_register_driver(&igb_driver); 210 ret = pci_register_driver(&igb_driver);
211#ifdef CONFIG_DCA
212 dca_register_notify(&dca_notifier);
213#endif
188 return ret; 214 return ret;
189} 215}
190 216
@@ -198,6 +224,9 @@ module_init(igb_init_module);
198 **/ 224 **/
199static void __exit igb_exit_module(void) 225static void __exit igb_exit_module(void)
200{ 226{
227#ifdef CONFIG_DCA
228 dca_unregister_notify(&dca_notifier);
229#endif
201 pci_unregister_driver(&igb_driver); 230 pci_unregister_driver(&igb_driver);
202} 231}
203 232
@@ -226,25 +255,46 @@ static int igb_alloc_queues(struct igb_adapter *adapter)
226 return -ENOMEM; 255 return -ENOMEM;
227 } 256 }
228 257
258 adapter->rx_ring->buddy = adapter->tx_ring;
259
260 for (i = 0; i < adapter->num_tx_queues; i++) {
261 struct igb_ring *ring = &(adapter->tx_ring[i]);
262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
229 for (i = 0; i < adapter->num_rx_queues; i++) { 265 for (i = 0; i < adapter->num_rx_queues; i++) {
230 struct igb_ring *ring = &(adapter->rx_ring[i]); 266 struct igb_ring *ring = &(adapter->rx_ring[i]);
231 ring->adapter = adapter; 267 ring->adapter = adapter;
268 ring->queue_index = i;
232 ring->itr_register = E1000_ITR; 269 ring->itr_register = E1000_ITR;
233 270
234 if (!ring->napi.poll) 271 /* set a default napi handler for each rx_ring */
235 netif_napi_add(adapter->netdev, &ring->napi, igb_clean, 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
236 adapter->napi.weight /
237 adapter->num_rx_queues);
238 } 273 }
239 return 0; 274 return 0;
240} 275}
241 276
277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
242#define IGB_N0_QUEUE -1 288#define IGB_N0_QUEUE -1
243static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, 289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
244 int tx_queue, int msix_vector) 290 int tx_queue, int msix_vector)
245{ 291{
246 u32 msixbm = 0; 292 u32 msixbm = 0;
247 struct e1000_hw *hw = &adapter->hw; 293 struct e1000_hw *hw = &adapter->hw;
294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
248 /* The 82575 assigns vectors using a bitmask, which matches the 298 /* The 82575 assigns vectors using a bitmask, which matches the
249 bitmask for the EICR/EIMS/EIMC registers. To assign one 299 bitmask for the EICR/EIMS/EIMC registers. To assign one
250 or more queues to a vector, we write the appropriate bits 300 or more queues to a vector, we write the appropriate bits
@@ -259,6 +309,47 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
259 E1000_EICR_TX_QUEUE0 << tx_queue; 309 E1000_EICR_TX_QUEUE0 << tx_queue;
260 } 310 }
261 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
312 break;
313 case e1000_82576:
314 /* Kawela uses a table-based method for assigning vectors.
315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
262} 353}
263 354
264/** 355/**
@@ -274,13 +365,19 @@ static void igb_configure_msix(struct igb_adapter *adapter)
274 struct e1000_hw *hw = &adapter->hw; 365 struct e1000_hw *hw = &adapter->hw;
275 366
276 adapter->eims_enable_mask = 0; 367 adapter->eims_enable_mask = 0;
368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
277 374
278 for (i = 0; i < adapter->num_tx_queues; i++) { 375 for (i = 0; i < adapter->num_tx_queues; i++) {
279 struct igb_ring *tx_ring = &adapter->tx_ring[i]; 376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
280 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++); 377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
281 adapter->eims_enable_mask |= tx_ring->eims_value; 378 adapter->eims_enable_mask |= tx_ring->eims_value;
282 if (tx_ring->itr_val) 379 if (tx_ring->itr_val)
283 writel(1000000000 / (tx_ring->itr_val * 256), 380 writel(tx_ring->itr_val,
284 hw->hw_addr + tx_ring->itr_register); 381 hw->hw_addr + tx_ring->itr_register);
285 else 382 else
286 writel(1, hw->hw_addr + tx_ring->itr_register); 383 writel(1, hw->hw_addr + tx_ring->itr_register);
@@ -288,10 +385,11 @@ static void igb_configure_msix(struct igb_adapter *adapter)
288 385
289 for (i = 0; i < adapter->num_rx_queues; i++) { 386 for (i = 0; i < adapter->num_rx_queues; i++) {
290 struct igb_ring *rx_ring = &adapter->rx_ring[i]; 387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
388 rx_ring->buddy = 0;
291 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++); 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
292 adapter->eims_enable_mask |= rx_ring->eims_value; 390 adapter->eims_enable_mask |= rx_ring->eims_value;
293 if (rx_ring->itr_val) 391 if (rx_ring->itr_val)
294 writel(1000000000 / (rx_ring->itr_val * 256), 392 writel(rx_ring->itr_val,
295 hw->hw_addr + rx_ring->itr_register); 393 hw->hw_addr + rx_ring->itr_register);
296 else 394 else
297 writel(1, hw->hw_addr + rx_ring->itr_register); 395 writel(1, hw->hw_addr + rx_ring->itr_register);
@@ -299,12 +397,11 @@ static void igb_configure_msix(struct igb_adapter *adapter)
299 397
300 398
301 /* set vector for other causes, i.e. link changes */ 399 /* set vector for other causes, i.e. link changes */
400 switch (hw->mac.type) {
401 case e1000_82575:
302 array_wr32(E1000_MSIXBM(0), vector++, 402 array_wr32(E1000_MSIXBM(0), vector++,
303 E1000_EIMS_OTHER); 403 E1000_EIMS_OTHER);
304 404
305 /* disable IAM for ICR interrupt bits */
306 wr32(E1000_IAM, 0);
307
308 tmp = rd32(E1000_CTRL_EXT); 405 tmp = rd32(E1000_CTRL_EXT);
309 /* enable MSI-X PBA support*/ 406 /* enable MSI-X PBA support*/
310 tmp |= E1000_CTRL_EXT_PBA_CLR; 407 tmp |= E1000_CTRL_EXT_PBA_CLR;
@@ -315,7 +412,21 @@ static void igb_configure_msix(struct igb_adapter *adapter)
315 412
316 wr32(E1000_CTRL_EXT, tmp); 413 wr32(E1000_CTRL_EXT, tmp);
317 adapter->eims_enable_mask |= E1000_EIMS_OTHER; 414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
415 adapter->eims_other = E1000_EIMS_OTHER;
416
417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
318 422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
319 wrfl(); 430 wrfl();
320} 431}
321 432
@@ -341,7 +452,7 @@ static int igb_request_msix(struct igb_adapter *adapter)
341 if (err) 452 if (err)
342 goto out; 453 goto out;
343 ring->itr_register = E1000_EITR(0) + (vector << 2); 454 ring->itr_register = E1000_EITR(0) + (vector << 2);
344 ring->itr_val = adapter->itr; 455 ring->itr_val = 976; /* ~4000 ints/sec */
345 vector++; 456 vector++;
346 } 457 }
347 for (i = 0; i < adapter->num_rx_queues; i++) { 458 for (i = 0; i < adapter->num_rx_queues; i++) {
@@ -357,6 +468,9 @@ static int igb_request_msix(struct igb_adapter *adapter)
357 goto out; 468 goto out;
358 ring->itr_register = E1000_EITR(0) + (vector << 2); 469 ring->itr_register = E1000_EITR(0) + (vector << 2);
359 ring->itr_val = adapter->itr; 470 ring->itr_val = adapter->itr;
471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
360 vector++; 474 vector++;
361 } 475 }
362 476
@@ -365,9 +479,6 @@ static int igb_request_msix(struct igb_adapter *adapter)
365 if (err) 479 if (err)
366 goto out; 480 goto out;
367 481
368 adapter->napi.poll = igb_clean_rx_ring_msix;
369 for (i = 0; i < adapter->num_rx_queues; i++)
370 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
371 igb_configure_msix(adapter); 482 igb_configure_msix(adapter);
372 return 0; 483 return 0;
373out: 484out:
@@ -380,7 +491,7 @@ static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
380 pci_disable_msix(adapter->pdev); 491 pci_disable_msix(adapter->pdev);
381 kfree(adapter->msix_entries); 492 kfree(adapter->msix_entries);
382 adapter->msix_entries = NULL; 493 adapter->msix_entries = NULL;
383 } else if (adapter->msi_enabled) 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
384 pci_disable_msi(adapter->pdev); 495 pci_disable_msi(adapter->pdev);
385 return; 496 return;
386} 497}
@@ -417,8 +528,12 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter)
417 /* If we can't do MSI-X, try MSI */ 528 /* If we can't do MSI-X, try MSI */
418msi_only: 529msi_only:
419 adapter->num_rx_queues = 1; 530 adapter->num_rx_queues = 1;
531 adapter->num_tx_queues = 1;
420 if (!pci_enable_msi(adapter->pdev)) 532 if (!pci_enable_msi(adapter->pdev))
421 adapter->msi_enabled = 1; 533 adapter->flags |= IGB_FLAG_HAS_MSI;
534
535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
422 return; 537 return;
423} 538}
424 539
@@ -436,29 +551,38 @@ static int igb_request_irq(struct igb_adapter *adapter)
436 551
437 if (adapter->msix_entries) { 552 if (adapter->msix_entries) {
438 err = igb_request_msix(adapter); 553 err = igb_request_msix(adapter);
439 if (!err) { 554 if (!err)
440 /* enable IAM, auto-mask,
441 * DO NOT USE EIAM or IAM in legacy mode */
442 wr32(E1000_IAM, IMS_ENABLE_MASK);
443 goto request_done; 555 goto request_done;
444 }
445 /* fall back to MSI */ 556 /* fall back to MSI */
446 igb_reset_interrupt_capability(adapter); 557 igb_reset_interrupt_capability(adapter);
447 if (!pci_enable_msi(adapter->pdev)) 558 if (!pci_enable_msi(adapter->pdev))
448 adapter->msi_enabled = 1; 559 adapter->flags |= IGB_FLAG_HAS_MSI;
449 igb_free_all_tx_resources(adapter); 560 igb_free_all_tx_resources(adapter);
450 igb_free_all_rx_resources(adapter); 561 igb_free_all_rx_resources(adapter);
451 adapter->num_rx_queues = 1; 562 adapter->num_rx_queues = 1;
452 igb_alloc_queues(adapter); 563 igb_alloc_queues(adapter);
564 } else {
565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
453 } 576 }
454 if (adapter->msi_enabled) { 577
578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
455 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0, 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
456 netdev->name, netdev); 580 netdev->name, netdev);
457 if (!err) 581 if (!err)
458 goto request_done; 582 goto request_done;
459 /* fall back to legacy interrupts */ 583 /* fall back to legacy interrupts */
460 igb_reset_interrupt_capability(adapter); 584 igb_reset_interrupt_capability(adapter);
461 adapter->msi_enabled = 0; 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
462 } 586 }
463 587
464 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, 588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
@@ -502,9 +626,12 @@ static void igb_irq_disable(struct igb_adapter *adapter)
502 struct e1000_hw *hw = &adapter->hw; 626 struct e1000_hw *hw = &adapter->hw;
503 627
504 if (adapter->msix_entries) { 628 if (adapter->msix_entries) {
629 wr32(E1000_EIAM, 0);
505 wr32(E1000_EIMC, ~0); 630 wr32(E1000_EIMC, ~0);
506 wr32(E1000_EIAC, 0); 631 wr32(E1000_EIAC, 0);
507 } 632 }
633
634 wr32(E1000_IAM, 0);
508 wr32(E1000_IMC, ~0); 635 wr32(E1000_IMC, ~0);
509 wrfl(); 636 wrfl();
510 synchronize_irq(adapter->pdev->irq); 637 synchronize_irq(adapter->pdev->irq);
@@ -519,13 +646,14 @@ static void igb_irq_enable(struct igb_adapter *adapter)
519 struct e1000_hw *hw = &adapter->hw; 646 struct e1000_hw *hw = &adapter->hw;
520 647
521 if (adapter->msix_entries) { 648 if (adapter->msix_entries) {
522 wr32(E1000_EIMS, 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
523 adapter->eims_enable_mask); 650 wr32(E1000_EIAM, adapter->eims_enable_mask);
524 wr32(E1000_EIAC, 651 wr32(E1000_EIMS, adapter->eims_enable_mask);
525 adapter->eims_enable_mask);
526 wr32(E1000_IMS, E1000_IMS_LSC); 652 wr32(E1000_IMS, E1000_IMS_LSC);
527 } else 653 } else {
528 wr32(E1000_IMS, IMS_ENABLE_MASK); 654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
529} 657}
530 658
531static void igb_update_mng_vlan(struct igb_adapter *adapter) 659static void igb_update_mng_vlan(struct igb_adapter *adapter)
@@ -632,12 +760,15 @@ static void igb_configure(struct igb_adapter *adapter)
632 igb_configure_tx(adapter); 760 igb_configure_tx(adapter);
633 igb_setup_rctl(adapter); 761 igb_setup_rctl(adapter);
634 igb_configure_rx(adapter); 762 igb_configure_rx(adapter);
763
764 igb_rx_fifo_flush_82575(&adapter->hw);
765
635 /* call IGB_DESC_UNUSED which always leaves 766 /* call IGB_DESC_UNUSED which always leaves
636 * at least 1 descriptor unused to make sure 767 * at least 1 descriptor unused to make sure
637 * next_to_use != next_to_clean */ 768 * next_to_use != next_to_clean */
638 for (i = 0; i < adapter->num_rx_queues; i++) { 769 for (i = 0; i < adapter->num_rx_queues; i++) {
639 struct igb_ring *ring = &adapter->rx_ring[i]; 770 struct igb_ring *ring = &adapter->rx_ring[i];
640 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring)); 771 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
641 } 772 }
642 773
643 774
@@ -660,13 +791,10 @@ int igb_up(struct igb_adapter *adapter)
660 791
661 clear_bit(__IGB_DOWN, &adapter->state); 792 clear_bit(__IGB_DOWN, &adapter->state);
662 793
663 napi_enable(&adapter->napi); 794 for (i = 0; i < adapter->num_rx_queues; i++)
664 795 napi_enable(&adapter->rx_ring[i].napi);
665 if (adapter->msix_entries) { 796 if (adapter->msix_entries)
666 for (i = 0; i < adapter->num_rx_queues; i++)
667 napi_enable(&adapter->rx_ring[i].napi);
668 igb_configure_msix(adapter); 797 igb_configure_msix(adapter);
669 }
670 798
671 /* Clear any pending interrupts. */ 799 /* Clear any pending interrupts. */
672 rd32(E1000_ICR); 800 rd32(E1000_ICR);
@@ -693,7 +821,7 @@ void igb_down(struct igb_adapter *adapter)
693 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 821 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
694 /* flush and sleep below */ 822 /* flush and sleep below */
695 823
696 netif_stop_queue(netdev); 824 netif_tx_stop_all_queues(netdev);
697 825
698 /* disable transmits in the hardware */ 826 /* disable transmits in the hardware */
699 tctl = rd32(E1000_TCTL); 827 tctl = rd32(E1000_TCTL);
@@ -703,11 +831,9 @@ void igb_down(struct igb_adapter *adapter)
703 wrfl(); 831 wrfl();
704 msleep(10); 832 msleep(10);
705 833
706 napi_disable(&adapter->napi); 834 for (i = 0; i < adapter->num_rx_queues; i++)
835 napi_disable(&adapter->rx_ring[i].napi);
707 836
708 if (adapter->msix_entries)
709 for (i = 0; i < adapter->num_rx_queues; i++)
710 napi_disable(&adapter->rx_ring[i].napi);
711 igb_irq_disable(adapter); 837 igb_irq_disable(adapter);
712 838
713 del_timer_sync(&adapter->watchdog_timer); 839 del_timer_sync(&adapter->watchdog_timer);
@@ -737,16 +863,23 @@ void igb_reinit_locked(struct igb_adapter *adapter)
737void igb_reset(struct igb_adapter *adapter) 863void igb_reset(struct igb_adapter *adapter)
738{ 864{
739 struct e1000_hw *hw = &adapter->hw; 865 struct e1000_hw *hw = &adapter->hw;
740 struct e1000_fc_info *fc = &adapter->hw.fc; 866 struct e1000_mac_info *mac = &hw->mac;
867 struct e1000_fc_info *fc = &hw->fc;
741 u32 pba = 0, tx_space, min_tx_space, min_rx_space; 868 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
742 u16 hwm; 869 u16 hwm;
743 870
744 /* Repartition Pba for greater than 9k mtu 871 /* Repartition Pba for greater than 9k mtu
745 * To take effect CTRL.RST is required. 872 * To take effect CTRL.RST is required.
746 */ 873 */
874 if (mac->type != e1000_82576) {
747 pba = E1000_PBA_34K; 875 pba = E1000_PBA_34K;
876 }
877 else {
878 pba = E1000_PBA_64K;
879 }
748 880
749 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { 881 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
882 (mac->type < e1000_82576)) {
750 /* adjust PBA for jumbo frames */ 883 /* adjust PBA for jumbo frames */
751 wr32(E1000_PBA, pba); 884 wr32(E1000_PBA, pba);
752 885
@@ -785,8 +918,8 @@ void igb_reset(struct igb_adapter *adapter)
785 if (pba < min_rx_space) 918 if (pba < min_rx_space)
786 pba = min_rx_space; 919 pba = min_rx_space;
787 } 920 }
921 wr32(E1000_PBA, pba);
788 } 922 }
789 wr32(E1000_PBA, pba);
790 923
791 /* flow control settings */ 924 /* flow control settings */
792 /* The high water mark must be low enough to fit one full frame 925 /* The high water mark must be low enough to fit one full frame
@@ -795,10 +928,15 @@ void igb_reset(struct igb_adapter *adapter)
795 * - 90% of the Rx FIFO size, or 928 * - 90% of the Rx FIFO size, or
796 * - the full Rx FIFO size minus one full frame */ 929 * - the full Rx FIFO size minus one full frame */
797 hwm = min(((pba << 10) * 9 / 10), 930 hwm = min(((pba << 10) * 9 / 10),
798 ((pba << 10) - adapter->max_frame_size)); 931 ((pba << 10) - 2 * adapter->max_frame_size));
799 932
800 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ 933 if (mac->type < e1000_82576) {
801 fc->low_water = fc->high_water - 8; 934 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
935 fc->low_water = fc->high_water - 8;
936 } else {
937 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
938 fc->low_water = fc->high_water - 16;
939 }
802 fc->pause_time = 0xFFFF; 940 fc->pause_time = 0xFFFF;
803 fc->send_xon = 1; 941 fc->send_xon = 1;
804 fc->type = fc->original_type; 942 fc->type = fc->original_type;
@@ -821,6 +959,21 @@ void igb_reset(struct igb_adapter *adapter)
821} 959}
822 960
823/** 961/**
962 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
963 * @pdev: PCI device information struct
964 *
965 * Returns true if an adapter needs ioport resources
966 **/
967static int igb_is_need_ioport(struct pci_dev *pdev)
968{
969 switch (pdev->device) {
970 /* Currently there are no adapters that need ioport resources */
971 default:
972 return false;
973 }
974}
975
976/**
824 * igb_probe - Device Initialization Routine 977 * igb_probe - Device Initialization Routine
825 * @pdev: PCI device information struct 978 * @pdev: PCI device information struct
826 * @ent: entry in igb_pci_tbl 979 * @ent: entry in igb_pci_tbl
@@ -839,13 +992,21 @@ static int __devinit igb_probe(struct pci_dev *pdev,
839 struct e1000_hw *hw; 992 struct e1000_hw *hw;
840 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 993 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
841 unsigned long mmio_start, mmio_len; 994 unsigned long mmio_start, mmio_len;
842 static int cards_found;
843 int i, err, pci_using_dac; 995 int i, err, pci_using_dac;
844 u16 eeprom_data = 0; 996 u16 eeprom_data = 0;
845 u16 eeprom_apme_mask = IGB_EEPROM_APME; 997 u16 eeprom_apme_mask = IGB_EEPROM_APME;
846 u32 part_num; 998 u32 part_num;
999 int bars, need_ioport;
847 1000
848 err = pci_enable_device(pdev); 1001 /* do not allocate ioport bars when not needed */
1002 need_ioport = igb_is_need_ioport(pdev);
1003 if (need_ioport) {
1004 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1005 err = pci_enable_device(pdev);
1006 } else {
1007 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1008 err = pci_enable_device_mem(pdev);
1009 }
849 if (err) 1010 if (err)
850 return err; 1011 return err;
851 1012
@@ -867,7 +1028,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
867 } 1028 }
868 } 1029 }
869 1030
870 err = pci_request_regions(pdev, igb_driver_name); 1031 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
871 if (err) 1032 if (err)
872 goto err_pci_reg; 1033 goto err_pci_reg;
873 1034
@@ -875,7 +1036,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
875 pci_save_state(pdev); 1036 pci_save_state(pdev);
876 1037
877 err = -ENOMEM; 1038 err = -ENOMEM;
878 netdev = alloc_etherdev(sizeof(struct igb_adapter)); 1039 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
879 if (!netdev) 1040 if (!netdev)
880 goto err_alloc_etherdev; 1041 goto err_alloc_etherdev;
881 1042
@@ -888,6 +1049,8 @@ static int __devinit igb_probe(struct pci_dev *pdev,
888 hw = &adapter->hw; 1049 hw = &adapter->hw;
889 hw->back = adapter; 1050 hw->back = adapter;
890 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; 1051 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1052 adapter->bars = bars;
1053 adapter->need_ioport = need_ioport;
891 1054
892 mmio_start = pci_resource_start(pdev, 0); 1055 mmio_start = pci_resource_start(pdev, 0);
893 mmio_len = pci_resource_len(pdev, 0); 1056 mmio_len = pci_resource_len(pdev, 0);
@@ -907,7 +1070,6 @@ static int __devinit igb_probe(struct pci_dev *pdev,
907 igb_set_ethtool_ops(netdev); 1070 igb_set_ethtool_ops(netdev);
908 netdev->tx_timeout = &igb_tx_timeout; 1071 netdev->tx_timeout = &igb_tx_timeout;
909 netdev->watchdog_timeo = 5 * HZ; 1072 netdev->watchdog_timeo = 5 * HZ;
910 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
911 netdev->vlan_rx_register = igb_vlan_rx_register; 1073 netdev->vlan_rx_register = igb_vlan_rx_register;
912 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid; 1074 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
913 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid; 1075 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
@@ -921,8 +1083,6 @@ static int __devinit igb_probe(struct pci_dev *pdev,
921 netdev->mem_start = mmio_start; 1083 netdev->mem_start = mmio_start;
922 netdev->mem_end = mmio_start + mmio_len; 1084 netdev->mem_end = mmio_start + mmio_len;
923 1085
924 adapter->bd_number = cards_found;
925
926 /* PCI config space info */ 1086 /* PCI config space info */
927 hw->vendor_id = pdev->vendor; 1087 hw->vendor_id = pdev->vendor;
928 hw->device_id = pdev->device; 1088 hw->device_id = pdev->device;
@@ -947,6 +1107,17 @@ static int __devinit igb_probe(struct pci_dev *pdev,
947 1107
948 igb_get_bus_info_pcie(hw); 1108 igb_get_bus_info_pcie(hw);
949 1109
1110 /* set flags */
1111 switch (hw->mac.type) {
1112 case e1000_82576:
1113 case e1000_82575:
1114 adapter->flags |= IGB_FLAG_HAS_DCA;
1115 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1116 break;
1117 default:
1118 break;
1119 }
1120
950 hw->phy.autoneg_wait_to_complete = false; 1121 hw->phy.autoneg_wait_to_complete = false;
951 hw->mac.adaptive_ifs = true; 1122 hw->mac.adaptive_ifs = true;
952 1123
@@ -968,8 +1139,17 @@ static int __devinit igb_probe(struct pci_dev *pdev,
968 NETIF_F_HW_VLAN_FILTER; 1139 NETIF_F_HW_VLAN_FILTER;
969 1140
970 netdev->features |= NETIF_F_TSO; 1141 netdev->features |= NETIF_F_TSO;
971
972 netdev->features |= NETIF_F_TSO6; 1142 netdev->features |= NETIF_F_TSO6;
1143
1144#ifdef CONFIG_IGB_LRO
1145 netdev->features |= NETIF_F_LRO;
1146#endif
1147
1148 netdev->vlan_features |= NETIF_F_TSO;
1149 netdev->vlan_features |= NETIF_F_TSO6;
1150 netdev->vlan_features |= NETIF_F_HW_CSUM;
1151 netdev->vlan_features |= NETIF_F_SG;
1152
973 if (pci_using_dac) 1153 if (pci_using_dac)
974 netdev->features |= NETIF_F_HIGHDMA; 1154 netdev->features |= NETIF_F_HIGHDMA;
975 1155
@@ -1053,11 +1233,23 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1053 adapter->eeprom_wol = 0; 1233 adapter->eeprom_wol = 0;
1054 break; 1234 break;
1055 case E1000_DEV_ID_82575EB_FIBER_SERDES: 1235 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1236 case E1000_DEV_ID_82576_FIBER:
1237 case E1000_DEV_ID_82576_SERDES:
1056 /* Wake events only supported on port A for dual fiber 1238 /* Wake events only supported on port A for dual fiber
1057 * regardless of eeprom setting */ 1239 * regardless of eeprom setting */
1058 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 1240 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1059 adapter->eeprom_wol = 0; 1241 adapter->eeprom_wol = 0;
1060 break; 1242 break;
1243 case E1000_DEV_ID_82576_QUAD_COPPER:
1244 /* if quad port adapter, disable WoL on all but port A */
1245 if (global_quad_port_a != 0)
1246 adapter->eeprom_wol = 0;
1247 else
1248 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1249 /* Reset for multiple quad port adapters */
1250 if (++global_quad_port_a == 4)
1251 global_quad_port_a = 0;
1252 break;
1061 } 1253 }
1062 1254
1063 /* initialize the wol settings based on the eeprom settings */ 1255 /* initialize the wol settings based on the eeprom settings */
@@ -1072,13 +1264,25 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1072 1264
1073 /* tell the stack to leave us alone until igb_open() is called */ 1265 /* tell the stack to leave us alone until igb_open() is called */
1074 netif_carrier_off(netdev); 1266 netif_carrier_off(netdev);
1075 netif_stop_queue(netdev); 1267 netif_tx_stop_all_queues(netdev);
1076 1268
1077 strcpy(netdev->name, "eth%d"); 1269 strcpy(netdev->name, "eth%d");
1078 err = register_netdev(netdev); 1270 err = register_netdev(netdev);
1079 if (err) 1271 if (err)
1080 goto err_register; 1272 goto err_register;
1081 1273
1274#ifdef CONFIG_DCA
1275 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1276 (dca_add_requester(&pdev->dev) == 0)) {
1277 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1278 dev_info(&pdev->dev, "DCA enabled\n");
1279 /* Always use CB2 mode, difference is masked
1280 * in the CB driver. */
1281 wr32(E1000_DCA_CTRL, 2);
1282 igb_setup_dca(adapter);
1283 }
1284#endif
1285
1082 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 1286 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1083 /* print bus type/speed/width info */ 1287 /* print bus type/speed/width info */
1084 dev_info(&pdev->dev, 1288 dev_info(&pdev->dev,
@@ -1099,10 +1303,9 @@ static int __devinit igb_probe(struct pci_dev *pdev,
1099 dev_info(&pdev->dev, 1303 dev_info(&pdev->dev,
1100 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 1304 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1101 adapter->msix_entries ? "MSI-X" : 1305 adapter->msix_entries ? "MSI-X" :
1102 adapter->msi_enabled ? "MSI" : "legacy", 1306 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1103 adapter->num_rx_queues, adapter->num_tx_queues); 1307 adapter->num_rx_queues, adapter->num_tx_queues);
1104 1308
1105 cards_found++;
1106 return 0; 1309 return 0;
1107 1310
1108err_register: 1311err_register:
@@ -1115,15 +1318,14 @@ err_eeprom:
1115 iounmap(hw->flash_address); 1318 iounmap(hw->flash_address);
1116 1319
1117 igb_remove_device(hw); 1320 igb_remove_device(hw);
1118 kfree(adapter->tx_ring); 1321 igb_free_queues(adapter);
1119 kfree(adapter->rx_ring);
1120err_sw_init: 1322err_sw_init:
1121err_hw_init: 1323err_hw_init:
1122 iounmap(hw->hw_addr); 1324 iounmap(hw->hw_addr);
1123err_ioremap: 1325err_ioremap:
1124 free_netdev(netdev); 1326 free_netdev(netdev);
1125err_alloc_etherdev: 1327err_alloc_etherdev:
1126 pci_release_regions(pdev); 1328 pci_release_selected_regions(pdev, bars);
1127err_pci_reg: 1329err_pci_reg:
1128err_dma: 1330err_dma:
1129 pci_disable_device(pdev); 1331 pci_disable_device(pdev);
@@ -1143,6 +1345,9 @@ static void __devexit igb_remove(struct pci_dev *pdev)
1143{ 1345{
1144 struct net_device *netdev = pci_get_drvdata(pdev); 1346 struct net_device *netdev = pci_get_drvdata(pdev);
1145 struct igb_adapter *adapter = netdev_priv(netdev); 1347 struct igb_adapter *adapter = netdev_priv(netdev);
1348#ifdef CONFIG_DCA
1349 struct e1000_hw *hw = &adapter->hw;
1350#endif
1146 1351
1147 /* flush_scheduled work may reschedule our watchdog task, so 1352 /* flush_scheduled work may reschedule our watchdog task, so
1148 * explicitly disable watchdog tasks from being rescheduled */ 1353 * explicitly disable watchdog tasks from being rescheduled */
@@ -1152,6 +1357,15 @@ static void __devexit igb_remove(struct pci_dev *pdev)
1152 1357
1153 flush_scheduled_work(); 1358 flush_scheduled_work();
1154 1359
1360#ifdef CONFIG_DCA
1361 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1362 dev_info(&pdev->dev, "DCA disabled\n");
1363 dca_remove_requester(&pdev->dev);
1364 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1365 wr32(E1000_DCA_CTRL, 1);
1366 }
1367#endif
1368
1155 /* Release control of h/w to f/w. If f/w is AMT enabled, this 1369 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1156 * would have already happened in close and is redundant. */ 1370 * would have already happened in close and is redundant. */
1157 igb_release_hw_control(adapter); 1371 igb_release_hw_control(adapter);
@@ -1164,13 +1378,12 @@ static void __devexit igb_remove(struct pci_dev *pdev)
1164 igb_remove_device(&adapter->hw); 1378 igb_remove_device(&adapter->hw);
1165 igb_reset_interrupt_capability(adapter); 1379 igb_reset_interrupt_capability(adapter);
1166 1380
1167 kfree(adapter->tx_ring); 1381 igb_free_queues(adapter);
1168 kfree(adapter->rx_ring);
1169 1382
1170 iounmap(adapter->hw.hw_addr); 1383 iounmap(adapter->hw.hw_addr);
1171 if (adapter->hw.flash_address) 1384 if (adapter->hw.flash_address)
1172 iounmap(adapter->hw.flash_address); 1385 iounmap(adapter->hw.flash_address);
1173 pci_release_regions(pdev); 1386 pci_release_selected_regions(pdev, adapter->bars);
1174 1387
1175 free_netdev(netdev); 1388 free_netdev(netdev);
1176 1389
@@ -1200,9 +1413,11 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
1200 1413
1201 /* Number of supported queues. */ 1414 /* Number of supported queues. */
1202 /* Having more queues than CPUs doesn't make sense. */ 1415 /* Having more queues than CPUs doesn't make sense. */
1203 adapter->num_tx_queues = 1; 1416 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1204 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus()); 1417 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1205 1418
1419 /* This call may decrease the number of queues depending on
1420 * interrupt mode. */
1206 igb_set_interrupt_capability(adapter); 1421 igb_set_interrupt_capability(adapter);
1207 1422
1208 if (igb_alloc_queues(adapter)) { 1423 if (igb_alloc_queues(adapter)) {
@@ -1270,15 +1485,16 @@ static int igb_open(struct net_device *netdev)
1270 /* From here on the code is the same as igb_up() */ 1485 /* From here on the code is the same as igb_up() */
1271 clear_bit(__IGB_DOWN, &adapter->state); 1486 clear_bit(__IGB_DOWN, &adapter->state);
1272 1487
1273 napi_enable(&adapter->napi); 1488 for (i = 0; i < adapter->num_rx_queues; i++)
1274 if (adapter->msix_entries) 1489 napi_enable(&adapter->rx_ring[i].napi);
1275 for (i = 0; i < adapter->num_rx_queues; i++)
1276 napi_enable(&adapter->rx_ring[i].napi);
1277
1278 igb_irq_enable(adapter);
1279 1490
1280 /* Clear any pending interrupts. */ 1491 /* Clear any pending interrupts. */
1281 rd32(E1000_ICR); 1492 rd32(E1000_ICR);
1493
1494 igb_irq_enable(adapter);
1495
1496 netif_tx_start_all_queues(netdev);
1497
1282 /* Fire a link status change interrupt to start the watchdog. */ 1498 /* Fire a link status change interrupt to start the watchdog. */
1283 wr32(E1000_ICS, E1000_ICS_LSC); 1499 wr32(E1000_ICS, E1000_ICS_LSC);
1284 1500
@@ -1364,8 +1580,6 @@ int igb_setup_tx_resources(struct igb_adapter *adapter,
1364 tx_ring->adapter = adapter; 1580 tx_ring->adapter = adapter;
1365 tx_ring->next_to_use = 0; 1581 tx_ring->next_to_use = 0;
1366 tx_ring->next_to_clean = 0; 1582 tx_ring->next_to_clean = 0;
1367 spin_lock_init(&tx_ring->tx_clean_lock);
1368 spin_lock_init(&tx_ring->tx_lock);
1369 return 0; 1583 return 0;
1370 1584
1371err: 1585err:
@@ -1385,6 +1599,7 @@ err:
1385static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 1599static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1386{ 1600{
1387 int i, err = 0; 1601 int i, err = 0;
1602 int r_idx;
1388 1603
1389 for (i = 0; i < adapter->num_tx_queues; i++) { 1604 for (i = 0; i < adapter->num_tx_queues; i++) {
1390 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]); 1605 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
@@ -1392,12 +1607,15 @@ static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1392 dev_err(&adapter->pdev->dev, 1607 dev_err(&adapter->pdev->dev,
1393 "Allocation for Tx Queue %u failed\n", i); 1608 "Allocation for Tx Queue %u failed\n", i);
1394 for (i--; i >= 0; i--) 1609 for (i--; i >= 0; i--)
1395 igb_free_tx_resources(adapter, 1610 igb_free_tx_resources(&adapter->tx_ring[i]);
1396 &adapter->tx_ring[i]);
1397 break; 1611 break;
1398 } 1612 }
1399 } 1613 }
1400 1614
1615 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1616 r_idx = i % adapter->num_tx_queues;
1617 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1618 }
1401 return err; 1619 return err;
1402} 1620}
1403 1621
@@ -1484,6 +1702,14 @@ int igb_setup_rx_resources(struct igb_adapter *adapter,
1484 struct pci_dev *pdev = adapter->pdev; 1702 struct pci_dev *pdev = adapter->pdev;
1485 int size, desc_len; 1703 int size, desc_len;
1486 1704
1705#ifdef CONFIG_IGB_LRO
1706 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1707 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1708 if (!rx_ring->lro_mgr.lro_arr)
1709 goto err;
1710 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1711#endif
1712
1487 size = sizeof(struct igb_buffer) * rx_ring->count; 1713 size = sizeof(struct igb_buffer) * rx_ring->count;
1488 rx_ring->buffer_info = vmalloc(size); 1714 rx_ring->buffer_info = vmalloc(size);
1489 if (!rx_ring->buffer_info) 1715 if (!rx_ring->buffer_info)
@@ -1504,15 +1730,16 @@ int igb_setup_rx_resources(struct igb_adapter *adapter,
1504 1730
1505 rx_ring->next_to_clean = 0; 1731 rx_ring->next_to_clean = 0;
1506 rx_ring->next_to_use = 0; 1732 rx_ring->next_to_use = 0;
1507 rx_ring->pending_skb = NULL;
1508 1733
1509 rx_ring->adapter = adapter; 1734 rx_ring->adapter = adapter;
1510 /* FIXME: do we want to setup ring->napi->poll here? */
1511 rx_ring->napi.poll = adapter->napi.poll;
1512 1735
1513 return 0; 1736 return 0;
1514 1737
1515err: 1738err:
1739#ifdef CONFIG_IGB_LRO
1740 vfree(rx_ring->lro_mgr.lro_arr);
1741 rx_ring->lro_mgr.lro_arr = NULL;
1742#endif
1516 vfree(rx_ring->buffer_info); 1743 vfree(rx_ring->buffer_info);
1517 dev_err(&adapter->pdev->dev, "Unable to allocate memory for " 1744 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1518 "the receive descriptor ring\n"); 1745 "the receive descriptor ring\n");
@@ -1536,8 +1763,7 @@ static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1536 dev_err(&adapter->pdev->dev, 1763 dev_err(&adapter->pdev->dev,
1537 "Allocation for Rx Queue %u failed\n", i); 1764 "Allocation for Rx Queue %u failed\n", i);
1538 for (i--; i >= 0; i--) 1765 for (i--; i >= 0; i--)
1539 igb_free_rx_resources(adapter, 1766 igb_free_rx_resources(&adapter->rx_ring[i]);
1540 &adapter->rx_ring[i]);
1541 break; 1767 break;
1542 } 1768 }
1543 } 1769 }
@@ -1564,10 +1790,12 @@ static void igb_setup_rctl(struct igb_adapter *adapter)
1564 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 1790 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1565 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 1791 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1566 1792
1567 /* disable the stripping of CRC because it breaks 1793 /*
1568 * BMC firmware connected over SMBUS 1794 * enable stripping of CRC. It's unlikely this will break BMC
1569 rctl |= E1000_RCTL_SECRC; 1795 * redirection as it did with e1000. Newer features require
1796 * that the HW strips the CRC.
1570 */ 1797 */
1798 rctl |= E1000_RCTL_SECRC;
1571 1799
1572 rctl &= ~E1000_RCTL_SBP; 1800 rctl &= ~E1000_RCTL_SBP;
1573 1801
@@ -1597,15 +1825,6 @@ static void igb_setup_rctl(struct igb_adapter *adapter)
1597 rctl |= E1000_RCTL_SZ_2048; 1825 rctl |= E1000_RCTL_SZ_2048;
1598 rctl &= ~E1000_RCTL_BSEX; 1826 rctl &= ~E1000_RCTL_BSEX;
1599 break; 1827 break;
1600 case IGB_RXBUFFER_4096:
1601 rctl |= E1000_RCTL_SZ_4096;
1602 break;
1603 case IGB_RXBUFFER_8192:
1604 rctl |= E1000_RCTL_SZ_8192;
1605 break;
1606 case IGB_RXBUFFER_16384:
1607 rctl |= E1000_RCTL_SZ_16384;
1608 break;
1609 } 1828 }
1610 } else { 1829 } else {
1611 rctl &= ~E1000_RCTL_BSEX; 1830 rctl &= ~E1000_RCTL_BSEX;
@@ -1623,10 +1842,8 @@ static void igb_setup_rctl(struct igb_adapter *adapter)
1623 * so only enable packet split for jumbo frames */ 1842 * so only enable packet split for jumbo frames */
1624 if (rctl & E1000_RCTL_LPE) { 1843 if (rctl & E1000_RCTL_LPE) {
1625 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128; 1844 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1626 srrctl = adapter->rx_ps_hdr_size << 1845 srrctl |= adapter->rx_ps_hdr_size <<
1627 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 1846 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1628 /* buffer size is ALWAYS one page */
1629 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1630 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; 1847 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1631 } else { 1848 } else {
1632 adapter->rx_ps_hdr_size = 0; 1849 adapter->rx_ps_hdr_size = 0;
@@ -1660,8 +1877,7 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1660 mdelay(10); 1877 mdelay(10);
1661 1878
1662 if (adapter->itr_setting > 3) 1879 if (adapter->itr_setting > 3)
1663 wr32(E1000_ITR, 1880 wr32(E1000_ITR, adapter->itr);
1664 1000000000 / (adapter->itr * 256));
1665 1881
1666 /* Setup the HW Rx Head and Tail Descriptor Pointers and 1882 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1667 * the Base and Length of the Rx Descriptor Ring */ 1883 * the Base and Length of the Rx Descriptor Ring */
@@ -1686,6 +1902,16 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1686 rxdctl |= IGB_RX_HTHRESH << 8; 1902 rxdctl |= IGB_RX_HTHRESH << 8;
1687 rxdctl |= IGB_RX_WTHRESH << 16; 1903 rxdctl |= IGB_RX_WTHRESH << 16;
1688 wr32(E1000_RXDCTL(i), rxdctl); 1904 wr32(E1000_RXDCTL(i), rxdctl);
1905#ifdef CONFIG_IGB_LRO
1906 /* Intitial LRO Settings */
1907 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1908 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1909 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1910 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1911 ring->lro_mgr.dev = adapter->netdev;
1912 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1913 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1914#endif
1689 } 1915 }
1690 1916
1691 if (adapter->num_rx_queues > 1) { 1917 if (adapter->num_rx_queues > 1) {
@@ -1699,7 +1925,10 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1699 1925
1700 get_random_bytes(&random[0], 40); 1926 get_random_bytes(&random[0], 40);
1701 1927
1702 shift = 6; 1928 if (hw->mac.type >= e1000_82576)
1929 shift = 0;
1930 else
1931 shift = 6;
1703 for (j = 0; j < (32 * 4); j++) { 1932 for (j = 0; j < (32 * 4); j++) {
1704 reta.bytes[j & 3] = 1933 reta.bytes[j & 3] =
1705 (j % adapter->num_rx_queues) << shift; 1934 (j % adapter->num_rx_queues) << shift;
@@ -1765,12 +1994,11 @@ static void igb_configure_rx(struct igb_adapter *adapter)
1765 * 1994 *
1766 * Free all transmit software resources 1995 * Free all transmit software resources
1767 **/ 1996 **/
1768static void igb_free_tx_resources(struct igb_adapter *adapter, 1997static void igb_free_tx_resources(struct igb_ring *tx_ring)
1769 struct igb_ring *tx_ring)
1770{ 1998{
1771 struct pci_dev *pdev = adapter->pdev; 1999 struct pci_dev *pdev = tx_ring->adapter->pdev;
1772 2000
1773 igb_clean_tx_ring(adapter, tx_ring); 2001 igb_clean_tx_ring(tx_ring);
1774 2002
1775 vfree(tx_ring->buffer_info); 2003 vfree(tx_ring->buffer_info);
1776 tx_ring->buffer_info = NULL; 2004 tx_ring->buffer_info = NULL;
@@ -1791,7 +2019,7 @@ static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1791 int i; 2019 int i;
1792 2020
1793 for (i = 0; i < adapter->num_tx_queues; i++) 2021 for (i = 0; i < adapter->num_tx_queues; i++)
1794 igb_free_tx_resources(adapter, &adapter->tx_ring[i]); 2022 igb_free_tx_resources(&adapter->tx_ring[i]);
1795} 2023}
1796 2024
1797static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter, 2025static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
@@ -1817,9 +2045,9 @@ static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1817 * @adapter: board private structure 2045 * @adapter: board private structure
1818 * @tx_ring: ring to be cleaned 2046 * @tx_ring: ring to be cleaned
1819 **/ 2047 **/
1820static void igb_clean_tx_ring(struct igb_adapter *adapter, 2048static void igb_clean_tx_ring(struct igb_ring *tx_ring)
1821 struct igb_ring *tx_ring)
1822{ 2049{
2050 struct igb_adapter *adapter = tx_ring->adapter;
1823 struct igb_buffer *buffer_info; 2051 struct igb_buffer *buffer_info;
1824 unsigned long size; 2052 unsigned long size;
1825 unsigned int i; 2053 unsigned int i;
@@ -1856,7 +2084,7 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1856 int i; 2084 int i;
1857 2085
1858 for (i = 0; i < adapter->num_tx_queues; i++) 2086 for (i = 0; i < adapter->num_tx_queues; i++)
1859 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]); 2087 igb_clean_tx_ring(&adapter->tx_ring[i]);
1860} 2088}
1861 2089
1862/** 2090/**
@@ -1866,16 +2094,20 @@ static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1866 * 2094 *
1867 * Free all receive software resources 2095 * Free all receive software resources
1868 **/ 2096 **/
1869static void igb_free_rx_resources(struct igb_adapter *adapter, 2097static void igb_free_rx_resources(struct igb_ring *rx_ring)
1870 struct igb_ring *rx_ring)
1871{ 2098{
1872 struct pci_dev *pdev = adapter->pdev; 2099 struct pci_dev *pdev = rx_ring->adapter->pdev;
1873 2100
1874 igb_clean_rx_ring(adapter, rx_ring); 2101 igb_clean_rx_ring(rx_ring);
1875 2102
1876 vfree(rx_ring->buffer_info); 2103 vfree(rx_ring->buffer_info);
1877 rx_ring->buffer_info = NULL; 2104 rx_ring->buffer_info = NULL;
1878 2105
2106#ifdef CONFIG_IGB_LRO
2107 vfree(rx_ring->lro_mgr.lro_arr);
2108 rx_ring->lro_mgr.lro_arr = NULL;
2109#endif
2110
1879 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2111 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1880 2112
1881 rx_ring->desc = NULL; 2113 rx_ring->desc = NULL;
@@ -1892,7 +2124,7 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1892 int i; 2124 int i;
1893 2125
1894 for (i = 0; i < adapter->num_rx_queues; i++) 2126 for (i = 0; i < adapter->num_rx_queues; i++)
1895 igb_free_rx_resources(adapter, &adapter->rx_ring[i]); 2127 igb_free_rx_resources(&adapter->rx_ring[i]);
1896} 2128}
1897 2129
1898/** 2130/**
@@ -1900,9 +2132,9 @@ static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1900 * @adapter: board private structure 2132 * @adapter: board private structure
1901 * @rx_ring: ring to free buffers from 2133 * @rx_ring: ring to free buffers from
1902 **/ 2134 **/
1903static void igb_clean_rx_ring(struct igb_adapter *adapter, 2135static void igb_clean_rx_ring(struct igb_ring *rx_ring)
1904 struct igb_ring *rx_ring)
1905{ 2136{
2137 struct igb_adapter *adapter = rx_ring->adapter;
1906 struct igb_buffer *buffer_info; 2138 struct igb_buffer *buffer_info;
1907 struct pci_dev *pdev = adapter->pdev; 2139 struct pci_dev *pdev = adapter->pdev;
1908 unsigned long size; 2140 unsigned long size;
@@ -1930,20 +2162,17 @@ static void igb_clean_rx_ring(struct igb_adapter *adapter,
1930 buffer_info->skb = NULL; 2162 buffer_info->skb = NULL;
1931 } 2163 }
1932 if (buffer_info->page) { 2164 if (buffer_info->page) {
1933 pci_unmap_page(pdev, buffer_info->page_dma, 2165 if (buffer_info->page_dma)
1934 PAGE_SIZE, PCI_DMA_FROMDEVICE); 2166 pci_unmap_page(pdev, buffer_info->page_dma,
2167 PAGE_SIZE / 2,
2168 PCI_DMA_FROMDEVICE);
1935 put_page(buffer_info->page); 2169 put_page(buffer_info->page);
1936 buffer_info->page = NULL; 2170 buffer_info->page = NULL;
1937 buffer_info->page_dma = 0; 2171 buffer_info->page_dma = 0;
2172 buffer_info->page_offset = 0;
1938 } 2173 }
1939 } 2174 }
1940 2175
1941 /* there also may be some cached data from a chained receive */
1942 if (rx_ring->pending_skb) {
1943 dev_kfree_skb(rx_ring->pending_skb);
1944 rx_ring->pending_skb = NULL;
1945 }
1946
1947 size = sizeof(struct igb_buffer) * rx_ring->count; 2176 size = sizeof(struct igb_buffer) * rx_ring->count;
1948 memset(rx_ring->buffer_info, 0, size); 2177 memset(rx_ring->buffer_info, 0, size);
1949 2178
@@ -1966,7 +2195,7 @@ static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1966 int i; 2195 int i;
1967 2196
1968 for (i = 0; i < adapter->num_rx_queues; i++) 2197 for (i = 0; i < adapter->num_rx_queues; i++)
1969 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]); 2198 igb_clean_rx_ring(&adapter->rx_ring[i]);
1970} 2199}
1971 2200
1972/** 2201/**
@@ -2015,19 +2244,22 @@ static void igb_set_multi(struct net_device *netdev)
2015 2244
2016 rctl = rd32(E1000_RCTL); 2245 rctl = rd32(E1000_RCTL);
2017 2246
2018 if (netdev->flags & IFF_PROMISC) 2247 if (netdev->flags & IFF_PROMISC) {
2019 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2248 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2020 else if (netdev->flags & IFF_ALLMULTI) { 2249 rctl &= ~E1000_RCTL_VFE;
2021 rctl |= E1000_RCTL_MPE; 2250 } else {
2022 rctl &= ~E1000_RCTL_UPE; 2251 if (netdev->flags & IFF_ALLMULTI) {
2023 } else 2252 rctl |= E1000_RCTL_MPE;
2024 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2253 rctl &= ~E1000_RCTL_UPE;
2025 2254 } else
2255 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2256 rctl |= E1000_RCTL_VFE;
2257 }
2026 wr32(E1000_RCTL, rctl); 2258 wr32(E1000_RCTL, rctl);
2027 2259
2028 if (!netdev->mc_count) { 2260 if (!netdev->mc_count) {
2029 /* nothing to program, so clear mc list */ 2261 /* nothing to program, so clear mc list */
2030 igb_update_mc_addr_list(hw, NULL, 0, 1, 2262 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
2031 mac->rar_entry_count); 2263 mac->rar_entry_count);
2032 return; 2264 return;
2033 } 2265 }
@@ -2045,7 +2277,8 @@ static void igb_set_multi(struct net_device *netdev)
2045 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); 2277 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2046 mc_ptr = mc_ptr->next; 2278 mc_ptr = mc_ptr->next;
2047 } 2279 }
2048 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count); 2280 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2281 mac->rar_entry_count);
2049 kfree(mta_list); 2282 kfree(mta_list);
2050} 2283}
2051 2284
@@ -2135,7 +2368,7 @@ static void igb_watchdog_task(struct work_struct *work)
2135 } 2368 }
2136 2369
2137 netif_carrier_on(netdev); 2370 netif_carrier_on(netdev);
2138 netif_wake_queue(netdev); 2371 netif_tx_wake_all_queues(netdev);
2139 2372
2140 if (!test_bit(__IGB_DOWN, &adapter->state)) 2373 if (!test_bit(__IGB_DOWN, &adapter->state))
2141 mod_timer(&adapter->phy_info_timer, 2374 mod_timer(&adapter->phy_info_timer,
@@ -2147,7 +2380,7 @@ static void igb_watchdog_task(struct work_struct *work)
2147 adapter->link_duplex = 0; 2380 adapter->link_duplex = 0;
2148 dev_info(&adapter->pdev->dev, "NIC Link is Down\n"); 2381 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2149 netif_carrier_off(netdev); 2382 netif_carrier_off(netdev);
2150 netif_stop_queue(netdev); 2383 netif_tx_stop_all_queues(netdev);
2151 if (!test_bit(__IGB_DOWN, &adapter->state)) 2384 if (!test_bit(__IGB_DOWN, &adapter->state))
2152 mod_timer(&adapter->phy_info_timer, 2385 mod_timer(&adapter->phy_info_timer,
2153 round_jiffies(jiffies + 2 * HZ)); 2386 round_jiffies(jiffies + 2 * HZ));
@@ -2200,38 +2433,60 @@ enum latency_range {
2200}; 2433};
2201 2434
2202 2435
2203static void igb_lower_rx_eitr(struct igb_adapter *adapter, 2436/**
2204 struct igb_ring *rx_ring) 2437 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2438 *
2439 * Stores a new ITR value based on strictly on packet size. This
2440 * algorithm is less sophisticated than that used in igb_update_itr,
2441 * due to the difficulty of synchronizing statistics across multiple
2442 * receive rings. The divisors and thresholds used by this fuction
2443 * were determined based on theoretical maximum wire speed and testing
2444 * data, in order to minimize response time while increasing bulk
2445 * throughput.
2446 * This functionality is controlled by the InterruptThrottleRate module
2447 * parameter (see igb_param.c)
2448 * NOTE: This function is called only when operating in a multiqueue
2449 * receive environment.
2450 * @rx_ring: pointer to ring
2451 **/
2452static void igb_update_ring_itr(struct igb_ring *rx_ring)
2205{ 2453{
2206 struct e1000_hw *hw = &adapter->hw; 2454 int new_val = rx_ring->itr_val;
2207 int new_val; 2455 int avg_wire_size = 0;
2456 struct igb_adapter *adapter = rx_ring->adapter;
2208 2457
2209 new_val = rx_ring->itr_val / 2; 2458 if (!rx_ring->total_packets)
2210 if (new_val < IGB_MIN_DYN_ITR) 2459 goto clear_counts; /* no packets, so don't do anything */
2211 new_val = IGB_MIN_DYN_ITR;
2212 2460
2213 if (new_val != rx_ring->itr_val) { 2461 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2214 rx_ring->itr_val = new_val; 2462 * ints/sec - ITR timer value of 120 ticks.
2215 wr32(rx_ring->itr_register, 2463 */
2216 1000000000 / (new_val * 256)); 2464 if (adapter->link_speed != SPEED_1000) {
2465 new_val = 120;
2466 goto set_itr_val;
2217 } 2467 }
2218} 2468 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2219 2469
2220static void igb_raise_rx_eitr(struct igb_adapter *adapter, 2470 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2221 struct igb_ring *rx_ring) 2471 avg_wire_size += 24;
2222{
2223 struct e1000_hw *hw = &adapter->hw;
2224 int new_val;
2225 2472
2226 new_val = rx_ring->itr_val * 2; 2473 /* Don't starve jumbo frames */
2227 if (new_val > IGB_MAX_DYN_ITR) 2474 avg_wire_size = min(avg_wire_size, 3000);
2228 new_val = IGB_MAX_DYN_ITR;
2229 2475
2476 /* Give a little boost to mid-size frames */
2477 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2478 new_val = avg_wire_size / 3;
2479 else
2480 new_val = avg_wire_size / 2;
2481
2482set_itr_val:
2230 if (new_val != rx_ring->itr_val) { 2483 if (new_val != rx_ring->itr_val) {
2231 rx_ring->itr_val = new_val; 2484 rx_ring->itr_val = new_val;
2232 wr32(rx_ring->itr_register, 2485 rx_ring->set_itr = 1;
2233 1000000000 / (new_val * 256));
2234 } 2486 }
2487clear_counts:
2488 rx_ring->total_bytes = 0;
2489 rx_ring->total_packets = 0;
2235} 2490}
2236 2491
2237/** 2492/**
@@ -2298,8 +2553,7 @@ update_itr_done:
2298 return retval; 2553 return retval;
2299} 2554}
2300 2555
2301static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register, 2556static void igb_set_itr(struct igb_adapter *adapter)
2302 int rx_only)
2303{ 2557{
2304 u16 current_itr; 2558 u16 current_itr;
2305 u32 new_itr = adapter->itr; 2559 u32 new_itr = adapter->itr;
@@ -2315,26 +2569,23 @@ static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2315 adapter->rx_itr, 2569 adapter->rx_itr,
2316 adapter->rx_ring->total_packets, 2570 adapter->rx_ring->total_packets,
2317 adapter->rx_ring->total_bytes); 2571 adapter->rx_ring->total_bytes);
2318 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2319 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2320 adapter->rx_itr = low_latency;
2321 2572
2322 if (!rx_only) { 2573 if (adapter->rx_ring->buddy) {
2323 adapter->tx_itr = igb_update_itr(adapter, 2574 adapter->tx_itr = igb_update_itr(adapter,
2324 adapter->tx_itr, 2575 adapter->tx_itr,
2325 adapter->tx_ring->total_packets, 2576 adapter->tx_ring->total_packets,
2326 adapter->tx_ring->total_bytes); 2577 adapter->tx_ring->total_bytes);
2327 /* conservative mode (itr 3) eliminates the
2328 * lowest_latency setting */
2329 if (adapter->itr_setting == 3 &&
2330 adapter->tx_itr == lowest_latency)
2331 adapter->tx_itr = low_latency;
2332 2578
2333 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2579 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2334 } else { 2580 } else {
2335 current_itr = adapter->rx_itr; 2581 current_itr = adapter->rx_itr;
2336 } 2582 }
2337 2583
2584 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2585 if (adapter->itr_setting == 3 &&
2586 current_itr == lowest_latency)
2587 current_itr = low_latency;
2588
2338 switch (current_itr) { 2589 switch (current_itr) {
2339 /* counts and packets in update_itr are dependent on these numbers */ 2590 /* counts and packets in update_itr are dependent on these numbers */
2340 case lowest_latency: 2591 case lowest_latency:
@@ -2351,6 +2602,13 @@ static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2351 } 2602 }
2352 2603
2353set_itr_now: 2604set_itr_now:
2605 adapter->rx_ring->total_bytes = 0;
2606 adapter->rx_ring->total_packets = 0;
2607 if (adapter->rx_ring->buddy) {
2608 adapter->rx_ring->buddy->total_bytes = 0;
2609 adapter->rx_ring->buddy->total_packets = 0;
2610 }
2611
2354 if (new_itr != adapter->itr) { 2612 if (new_itr != adapter->itr) {
2355 /* this attempts to bias the interrupt rate towards Bulk 2613 /* this attempts to bias the interrupt rate towards Bulk
2356 * by adding intermediate steps when interrupt rate is 2614 * by adding intermediate steps when interrupt rate is
@@ -2365,7 +2623,8 @@ set_itr_now:
2365 * ends up being correct. 2623 * ends up being correct.
2366 */ 2624 */
2367 adapter->itr = new_itr; 2625 adapter->itr = new_itr;
2368 adapter->set_itr = 1; 2626 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2627 adapter->rx_ring->set_itr = 1;
2369 } 2628 }
2370 2629
2371 return; 2630 return;
@@ -2441,9 +2700,9 @@ static inline int igb_tso_adv(struct igb_adapter *adapter,
2441 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); 2700 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2442 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); 2701 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2443 2702
2444 /* Context index must be unique per ring. Luckily, so is the interrupt 2703 /* Context index must be unique per ring. */
2445 * mask value. */ 2704 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2446 mss_l4len_idx |= tx_ring->eims_value >> 4; 2705 mss_l4len_idx |= tx_ring->queue_index << 4;
2447 2706
2448 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 2707 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2449 context_desc->seqnum_seed = 0; 2708 context_desc->seqnum_seed = 0;
@@ -2507,8 +2766,9 @@ static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2507 2766
2508 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); 2767 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2509 context_desc->seqnum_seed = 0; 2768 context_desc->seqnum_seed = 0;
2510 context_desc->mss_l4len_idx = 2769 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2511 cpu_to_le32(tx_ring->eims_value >> 4); 2770 context_desc->mss_l4len_idx =
2771 cpu_to_le32(tx_ring->queue_index << 4);
2512 2772
2513 buffer_info->time_stamp = jiffies; 2773 buffer_info->time_stamp = jiffies;
2514 buffer_info->dma = 0; 2774 buffer_info->dma = 0;
@@ -2609,9 +2869,10 @@ static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2609 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2869 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2610 } 2870 }
2611 2871
2612 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO | 2872 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2613 IGB_TX_FLAGS_VLAN)) 2873 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2614 olinfo_status |= tx_ring->eims_value >> 4; 2874 IGB_TX_FLAGS_VLAN)))
2875 olinfo_status |= tx_ring->queue_index << 4;
2615 2876
2616 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); 2877 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2617 2878
@@ -2647,7 +2908,8 @@ static int __igb_maybe_stop_tx(struct net_device *netdev,
2647{ 2908{
2648 struct igb_adapter *adapter = netdev_priv(netdev); 2909 struct igb_adapter *adapter = netdev_priv(netdev);
2649 2910
2650 netif_stop_queue(netdev); 2911 netif_stop_subqueue(netdev, tx_ring->queue_index);
2912
2651 /* Herbert's original patch had: 2913 /* Herbert's original patch had:
2652 * smp_mb__after_netif_stop_queue(); 2914 * smp_mb__after_netif_stop_queue();
2653 * but since that doesn't exist yet, just open code it. */ 2915 * but since that doesn't exist yet, just open code it. */
@@ -2659,7 +2921,7 @@ static int __igb_maybe_stop_tx(struct net_device *netdev,
2659 return -EBUSY; 2921 return -EBUSY;
2660 2922
2661 /* A reprieve! */ 2923 /* A reprieve! */
2662 netif_start_queue(netdev); 2924 netif_wake_subqueue(netdev, tx_ring->queue_index);
2663 ++adapter->restart_queue; 2925 ++adapter->restart_queue;
2664 return 0; 2926 return 0;
2665} 2927}
@@ -2681,7 +2943,6 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2681 struct igb_adapter *adapter = netdev_priv(netdev); 2943 struct igb_adapter *adapter = netdev_priv(netdev);
2682 unsigned int tx_flags = 0; 2944 unsigned int tx_flags = 0;
2683 unsigned int len; 2945 unsigned int len;
2684 unsigned long irq_flags;
2685 u8 hdr_len = 0; 2946 u8 hdr_len = 0;
2686 int tso = 0; 2947 int tso = 0;
2687 2948
@@ -2697,10 +2958,6 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2697 return NETDEV_TX_OK; 2958 return NETDEV_TX_OK;
2698 } 2959 }
2699 2960
2700 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2701 /* Collision - tell upper layer to requeue */
2702 return NETDEV_TX_LOCKED;
2703
2704 /* need: 1 descriptor per page, 2961 /* need: 1 descriptor per page,
2705 * + 2 desc gap to keep tail from touching head, 2962 * + 2 desc gap to keep tail from touching head,
2706 * + 1 desc for skb->data, 2963 * + 1 desc for skb->data,
@@ -2708,21 +2965,23 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2708 * otherwise try next time */ 2965 * otherwise try next time */
2709 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 2966 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2710 /* this is a hard error */ 2967 /* this is a hard error */
2711 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2712 return NETDEV_TX_BUSY; 2968 return NETDEV_TX_BUSY;
2713 } 2969 }
2970 skb_orphan(skb);
2714 2971
2715 if (adapter->vlgrp && vlan_tx_tag_present(skb)) { 2972 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2716 tx_flags |= IGB_TX_FLAGS_VLAN; 2973 tx_flags |= IGB_TX_FLAGS_VLAN;
2717 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 2974 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2718 } 2975 }
2719 2976
2977 if (skb->protocol == htons(ETH_P_IP))
2978 tx_flags |= IGB_TX_FLAGS_IPV4;
2979
2720 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags, 2980 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2721 &hdr_len) : 0; 2981 &hdr_len) : 0;
2722 2982
2723 if (tso < 0) { 2983 if (tso < 0) {
2724 dev_kfree_skb_any(skb); 2984 dev_kfree_skb_any(skb);
2725 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2726 return NETDEV_TX_OK; 2985 return NETDEV_TX_OK;
2727 } 2986 }
2728 2987
@@ -2732,9 +2991,6 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2732 if (skb->ip_summed == CHECKSUM_PARTIAL) 2991 if (skb->ip_summed == CHECKSUM_PARTIAL)
2733 tx_flags |= IGB_TX_FLAGS_CSUM; 2992 tx_flags |= IGB_TX_FLAGS_CSUM;
2734 2993
2735 if (skb->protocol == htons(ETH_P_IP))
2736 tx_flags |= IGB_TX_FLAGS_IPV4;
2737
2738 igb_tx_queue_adv(adapter, tx_ring, tx_flags, 2994 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2739 igb_tx_map_adv(adapter, tx_ring, skb), 2995 igb_tx_map_adv(adapter, tx_ring, skb),
2740 skb->len, hdr_len); 2996 skb->len, hdr_len);
@@ -2744,14 +3000,17 @@ static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2744 /* Make sure there is space in the ring for the next send. */ 3000 /* Make sure there is space in the ring for the next send. */
2745 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4); 3001 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2746 3002
2747 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2748 return NETDEV_TX_OK; 3003 return NETDEV_TX_OK;
2749} 3004}
2750 3005
2751static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev) 3006static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2752{ 3007{
2753 struct igb_adapter *adapter = netdev_priv(netdev); 3008 struct igb_adapter *adapter = netdev_priv(netdev);
2754 struct igb_ring *tx_ring = &adapter->tx_ring[0]; 3009 struct igb_ring *tx_ring;
3010
3011 int r_idx = 0;
3012 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3013 tx_ring = adapter->multi_tx_table[r_idx];
2755 3014
2756 /* This goes back to the question of how to logically map a tx queue 3015 /* This goes back to the question of how to logically map a tx queue
2757 * to a flow. Right now, performance is impacted slightly negatively 3016 * to a flow. Right now, performance is impacted slightly negatively
@@ -2846,7 +3105,11 @@ static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2846 else if (max_frame <= IGB_RXBUFFER_2048) 3105 else if (max_frame <= IGB_RXBUFFER_2048)
2847 adapter->rx_buffer_len = IGB_RXBUFFER_2048; 3106 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2848 else 3107 else
2849 adapter->rx_buffer_len = IGB_RXBUFFER_4096; 3108#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3109 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3110#else
3111 adapter->rx_buffer_len = PAGE_SIZE / 2;
3112#endif
2850 /* adjust allocation if LPE protects us, and we aren't using SBP */ 3113 /* adjust allocation if LPE protects us, and we aren't using SBP */
2851 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || 3114 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2852 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)) 3115 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
@@ -3010,26 +3273,19 @@ static irqreturn_t igb_msix_other(int irq, void *data)
3010 struct net_device *netdev = data; 3273 struct net_device *netdev = data;
3011 struct igb_adapter *adapter = netdev_priv(netdev); 3274 struct igb_adapter *adapter = netdev_priv(netdev);
3012 struct e1000_hw *hw = &adapter->hw; 3275 struct e1000_hw *hw = &adapter->hw;
3013 u32 eicr; 3276 u32 icr = rd32(E1000_ICR);
3014 /* disable interrupts from the "other" bit, avoid re-entry */
3015 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3016
3017 eicr = rd32(E1000_EICR);
3018
3019 if (eicr & E1000_EIMS_OTHER) {
3020 u32 icr = rd32(E1000_ICR);
3021 /* reading ICR causes bit 31 of EICR to be cleared */
3022 if (!(icr & E1000_ICR_LSC))
3023 goto no_link_interrupt;
3024 hw->mac.get_link_status = 1;
3025 /* guard against interrupt when we're going down */
3026 if (!test_bit(__IGB_DOWN, &adapter->state))
3027 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3028 }
3029 3277
3278 /* reading ICR causes bit 31 of EICR to be cleared */
3279 if (!(icr & E1000_ICR_LSC))
3280 goto no_link_interrupt;
3281 hw->mac.get_link_status = 1;
3282 /* guard against interrupt when we're going down */
3283 if (!test_bit(__IGB_DOWN, &adapter->state))
3284 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3285
3030no_link_interrupt: 3286no_link_interrupt:
3031 wr32(E1000_IMS, E1000_IMS_LSC); 3287 wr32(E1000_IMS, E1000_IMS_LSC);
3032 wr32(E1000_EIMS, E1000_EIMS_OTHER); 3288 wr32(E1000_EIMS, adapter->eims_other);
3033 3289
3034 return IRQ_HANDLED; 3290 return IRQ_HANDLED;
3035} 3291}
@@ -3040,44 +3296,186 @@ static irqreturn_t igb_msix_tx(int irq, void *data)
3040 struct igb_adapter *adapter = tx_ring->adapter; 3296 struct igb_adapter *adapter = tx_ring->adapter;
3041 struct e1000_hw *hw = &adapter->hw; 3297 struct e1000_hw *hw = &adapter->hw;
3042 3298
3043 if (!tx_ring->itr_val) 3299#ifdef CONFIG_DCA
3044 wr32(E1000_EIMC, tx_ring->eims_value); 3300 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3045 3301 igb_update_tx_dca(tx_ring);
3302#endif
3046 tx_ring->total_bytes = 0; 3303 tx_ring->total_bytes = 0;
3047 tx_ring->total_packets = 0; 3304 tx_ring->total_packets = 0;
3048 if (!igb_clean_tx_irq(adapter, tx_ring)) 3305
3306 /* auto mask will automatically reenable the interrupt when we write
3307 * EICS */
3308 if (!igb_clean_tx_irq(tx_ring))
3049 /* Ring was not completely cleaned, so fire another interrupt */ 3309 /* Ring was not completely cleaned, so fire another interrupt */
3050 wr32(E1000_EICS, tx_ring->eims_value); 3310 wr32(E1000_EICS, tx_ring->eims_value);
3051 3311 else
3052 if (!tx_ring->itr_val)
3053 wr32(E1000_EIMS, tx_ring->eims_value); 3312 wr32(E1000_EIMS, tx_ring->eims_value);
3313
3054 return IRQ_HANDLED; 3314 return IRQ_HANDLED;
3055} 3315}
3056 3316
3317static void igb_write_itr(struct igb_ring *ring)
3318{
3319 struct e1000_hw *hw = &ring->adapter->hw;
3320 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3321 switch (hw->mac.type) {
3322 case e1000_82576:
3323 wr32(ring->itr_register,
3324 ring->itr_val |
3325 0x80000000);
3326 break;
3327 default:
3328 wr32(ring->itr_register,
3329 ring->itr_val |
3330 (ring->itr_val << 16));
3331 break;
3332 }
3333 ring->set_itr = 0;
3334 }
3335}
3336
3057static irqreturn_t igb_msix_rx(int irq, void *data) 3337static irqreturn_t igb_msix_rx(int irq, void *data)
3058{ 3338{
3059 struct igb_ring *rx_ring = data; 3339 struct igb_ring *rx_ring = data;
3060 struct igb_adapter *adapter = rx_ring->adapter; 3340 struct igb_adapter *adapter = rx_ring->adapter;
3061 struct e1000_hw *hw = &adapter->hw;
3062 3341
3063 if (!rx_ring->itr_val) 3342 /* Write the ITR value calculated at the end of the
3064 wr32(E1000_EIMC, rx_ring->eims_value); 3343 * previous interrupt.
3344 */
3345
3346 igb_write_itr(rx_ring);
3065 3347
3066 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) { 3348 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3067 rx_ring->total_bytes = 0;
3068 rx_ring->total_packets = 0;
3069 rx_ring->no_itr_adjust = 0;
3070 __netif_rx_schedule(adapter->netdev, &rx_ring->napi); 3349 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3071 } else { 3350
3072 if (!rx_ring->no_itr_adjust) { 3351#ifdef CONFIG_DCA
3073 igb_lower_rx_eitr(adapter, rx_ring); 3352 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3074 rx_ring->no_itr_adjust = 1; 3353 igb_update_rx_dca(rx_ring);
3354#endif
3355 return IRQ_HANDLED;
3356}
3357
3358#ifdef CONFIG_DCA
3359static void igb_update_rx_dca(struct igb_ring *rx_ring)
3360{
3361 u32 dca_rxctrl;
3362 struct igb_adapter *adapter = rx_ring->adapter;
3363 struct e1000_hw *hw = &adapter->hw;
3364 int cpu = get_cpu();
3365 int q = rx_ring - adapter->rx_ring;
3366
3367 if (rx_ring->cpu != cpu) {
3368 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3369 if (hw->mac.type == e1000_82576) {
3370 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3371 dca_rxctrl |= dca_get_tag(cpu) <<
3372 E1000_DCA_RXCTRL_CPUID_SHIFT;
3373 } else {
3374 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3375 dca_rxctrl |= dca_get_tag(cpu);
3075 } 3376 }
3377 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3378 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3379 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3380 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3381 rx_ring->cpu = cpu;
3076 } 3382 }
3383 put_cpu();
3384}
3077 3385
3078 return IRQ_HANDLED; 3386static void igb_update_tx_dca(struct igb_ring *tx_ring)
3387{
3388 u32 dca_txctrl;
3389 struct igb_adapter *adapter = tx_ring->adapter;
3390 struct e1000_hw *hw = &adapter->hw;
3391 int cpu = get_cpu();
3392 int q = tx_ring - adapter->tx_ring;
3393
3394 if (tx_ring->cpu != cpu) {
3395 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3396 if (hw->mac.type == e1000_82576) {
3397 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3398 dca_txctrl |= dca_get_tag(cpu) <<
3399 E1000_DCA_TXCTRL_CPUID_SHIFT;
3400 } else {
3401 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3402 dca_txctrl |= dca_get_tag(cpu);
3403 }
3404 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3405 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3406 tx_ring->cpu = cpu;
3407 }
3408 put_cpu();
3409}
3410
3411static void igb_setup_dca(struct igb_adapter *adapter)
3412{
3413 int i;
3414
3415 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3416 return;
3417
3418 for (i = 0; i < adapter->num_tx_queues; i++) {
3419 adapter->tx_ring[i].cpu = -1;
3420 igb_update_tx_dca(&adapter->tx_ring[i]);
3421 }
3422 for (i = 0; i < adapter->num_rx_queues; i++) {
3423 adapter->rx_ring[i].cpu = -1;
3424 igb_update_rx_dca(&adapter->rx_ring[i]);
3425 }
3426}
3427
3428static int __igb_notify_dca(struct device *dev, void *data)
3429{
3430 struct net_device *netdev = dev_get_drvdata(dev);
3431 struct igb_adapter *adapter = netdev_priv(netdev);
3432 struct e1000_hw *hw = &adapter->hw;
3433 unsigned long event = *(unsigned long *)data;
3434
3435 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3436 goto out;
3437
3438 switch (event) {
3439 case DCA_PROVIDER_ADD:
3440 /* if already enabled, don't do it again */
3441 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3442 break;
3443 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3444 /* Always use CB2 mode, difference is masked
3445 * in the CB driver. */
3446 wr32(E1000_DCA_CTRL, 2);
3447 if (dca_add_requester(dev) == 0) {
3448 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3449 igb_setup_dca(adapter);
3450 break;
3451 }
3452 /* Fall Through since DCA is disabled. */
3453 case DCA_PROVIDER_REMOVE:
3454 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3455 /* without this a class_device is left
3456 * hanging around in the sysfs model */
3457 dca_remove_requester(dev);
3458 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3459 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3460 wr32(E1000_DCA_CTRL, 1);
3461 }
3462 break;
3463 }
3464out:
3465 return 0;
3079} 3466}
3080 3467
3468static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3469 void *p)
3470{
3471 int ret_val;
3472
3473 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3474 __igb_notify_dca);
3475
3476 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3477}
3478#endif /* CONFIG_DCA */
3081 3479
3082/** 3480/**
3083 * igb_intr_msi - Interrupt Handler 3481 * igb_intr_msi - Interrupt Handler
@@ -3088,34 +3486,19 @@ static irqreturn_t igb_intr_msi(int irq, void *data)
3088{ 3486{
3089 struct net_device *netdev = data; 3487 struct net_device *netdev = data;
3090 struct igb_adapter *adapter = netdev_priv(netdev); 3488 struct igb_adapter *adapter = netdev_priv(netdev);
3091 struct napi_struct *napi = &adapter->napi;
3092 struct e1000_hw *hw = &adapter->hw; 3489 struct e1000_hw *hw = &adapter->hw;
3093 /* read ICR disables interrupts using IAM */ 3490 /* read ICR disables interrupts using IAM */
3094 u32 icr = rd32(E1000_ICR); 3491 u32 icr = rd32(E1000_ICR);
3095 3492
3096 /* Write the ITR value calculated at the end of the 3493 igb_write_itr(adapter->rx_ring);
3097 * previous interrupt.
3098 */
3099 if (adapter->set_itr) {
3100 wr32(E1000_ITR,
3101 1000000000 / (adapter->itr * 256));
3102 adapter->set_itr = 0;
3103 }
3104 3494
3105 /* read ICR disables interrupts using IAM */
3106 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3495 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3107 hw->mac.get_link_status = 1; 3496 hw->mac.get_link_status = 1;
3108 if (!test_bit(__IGB_DOWN, &adapter->state)) 3497 if (!test_bit(__IGB_DOWN, &adapter->state))
3109 mod_timer(&adapter->watchdog_timer, jiffies + 1); 3498 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3110 } 3499 }
3111 3500
3112 if (netif_rx_schedule_prep(netdev, napi)) { 3501 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
3113 adapter->tx_ring->total_bytes = 0;
3114 adapter->tx_ring->total_packets = 0;
3115 adapter->rx_ring->total_bytes = 0;
3116 adapter->rx_ring->total_packets = 0;
3117 __netif_rx_schedule(netdev, napi);
3118 }
3119 3502
3120 return IRQ_HANDLED; 3503 return IRQ_HANDLED;
3121} 3504}
@@ -3129,7 +3512,6 @@ static irqreturn_t igb_intr(int irq, void *data)
3129{ 3512{
3130 struct net_device *netdev = data; 3513 struct net_device *netdev = data;
3131 struct igb_adapter *adapter = netdev_priv(netdev); 3514 struct igb_adapter *adapter = netdev_priv(netdev);
3132 struct napi_struct *napi = &adapter->napi;
3133 struct e1000_hw *hw = &adapter->hw; 3515 struct e1000_hw *hw = &adapter->hw;
3134 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 3516 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3135 * need for the IMC write */ 3517 * need for the IMC write */
@@ -3138,14 +3520,7 @@ static irqreturn_t igb_intr(int irq, void *data)
3138 if (!icr) 3520 if (!icr)
3139 return IRQ_NONE; /* Not our interrupt */ 3521 return IRQ_NONE; /* Not our interrupt */
3140 3522
3141 /* Write the ITR value calculated at the end of the 3523 igb_write_itr(adapter->rx_ring);
3142 * previous interrupt.
3143 */
3144 if (adapter->set_itr) {
3145 wr32(E1000_ITR,
3146 1000000000 / (adapter->itr * 256));
3147 adapter->set_itr = 0;
3148 }
3149 3524
3150 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 3525 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3151 * not set, then the adapter didn't send an interrupt */ 3526 * not set, then the adapter didn't send an interrupt */
@@ -3161,57 +3536,41 @@ static irqreturn_t igb_intr(int irq, void *data)
3161 mod_timer(&adapter->watchdog_timer, jiffies + 1); 3536 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3162 } 3537 }
3163 3538
3164 if (netif_rx_schedule_prep(netdev, napi)) { 3539 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
3165 adapter->tx_ring->total_bytes = 0;
3166 adapter->rx_ring->total_bytes = 0;
3167 adapter->tx_ring->total_packets = 0;
3168 adapter->rx_ring->total_packets = 0;
3169 __netif_rx_schedule(netdev, napi);
3170 }
3171 3540
3172 return IRQ_HANDLED; 3541 return IRQ_HANDLED;
3173} 3542}
3174 3543
3175/** 3544/**
3176 * igb_clean - NAPI Rx polling callback 3545 * igb_poll - NAPI Rx polling callback
3177 * @adapter: board private structure 3546 * @napi: napi polling structure
3547 * @budget: count of how many packets we should handle
3178 **/ 3548 **/
3179static int igb_clean(struct napi_struct *napi, int budget) 3549static int igb_poll(struct napi_struct *napi, int budget)
3180{ 3550{
3181 struct igb_adapter *adapter = container_of(napi, struct igb_adapter, 3551 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3182 napi); 3552 struct igb_adapter *adapter = rx_ring->adapter;
3183 struct net_device *netdev = adapter->netdev; 3553 struct net_device *netdev = adapter->netdev;
3184 int tx_clean_complete = 1, work_done = 0; 3554 int tx_clean_complete, work_done = 0;
3185 int i;
3186
3187 /* Must NOT use netdev_priv macro here. */
3188 adapter = netdev->priv;
3189 3555
3190 /* Keep link state information with original netdev */ 3556 /* this poll routine only supports one tx and one rx queue */
3191 if (!netif_carrier_ok(netdev)) 3557#ifdef CONFIG_DCA
3192 goto quit_polling; 3558 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3193 3559 igb_update_tx_dca(&adapter->tx_ring[0]);
3194 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from 3560#endif
3195 * being cleaned by multiple cpus simultaneously. A failure obtaining 3561 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3196 * the lock means tx_ring[i] is currently being cleaned anyway. */
3197 for (i = 0; i < adapter->num_tx_queues; i++) {
3198 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3199 tx_clean_complete &= igb_clean_tx_irq(adapter,
3200 &adapter->tx_ring[i]);
3201 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3202 }
3203 }
3204 3562
3205 for (i = 0; i < adapter->num_rx_queues; i++) 3563#ifdef CONFIG_DCA
3206 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done, 3564 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3207 adapter->rx_ring[i].napi.weight); 3565 igb_update_rx_dca(&adapter->rx_ring[0]);
3566#endif
3567 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3208 3568
3209 /* If no Tx and not enough Rx work done, exit the polling mode */ 3569 /* If no Tx and not enough Rx work done, exit the polling mode */
3210 if ((tx_clean_complete && (work_done < budget)) || 3570 if ((tx_clean_complete && (work_done < budget)) ||
3211 !netif_running(netdev)) { 3571 !netif_running(netdev)) {
3212quit_polling:
3213 if (adapter->itr_setting & 3) 3572 if (adapter->itr_setting & 3)
3214 igb_set_itr(adapter, E1000_ITR, false); 3573 igb_set_itr(adapter);
3215 netif_rx_complete(netdev, napi); 3574 netif_rx_complete(netdev, napi);
3216 if (!test_bit(__IGB_DOWN, &adapter->state)) 3575 if (!test_bit(__IGB_DOWN, &adapter->state))
3217 igb_irq_enable(adapter); 3576 igb_irq_enable(adapter);
@@ -3233,7 +3592,11 @@ static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3233 if (!netif_carrier_ok(netdev)) 3592 if (!netif_carrier_ok(netdev))
3234 goto quit_polling; 3593 goto quit_polling;
3235 3594
3236 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget); 3595#ifdef CONFIG_DCA
3596 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3597 igb_update_rx_dca(rx_ring);
3598#endif
3599 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3237 3600
3238 3601
3239 /* If not enough Rx work done, exit the polling mode */ 3602 /* If not enough Rx work done, exit the polling mode */
@@ -3241,16 +3604,16 @@ static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3241quit_polling: 3604quit_polling:
3242 netif_rx_complete(netdev, napi); 3605 netif_rx_complete(netdev, napi);
3243 3606
3244 wr32(E1000_EIMS, rx_ring->eims_value); 3607 if (adapter->itr_setting & 3) {
3245 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust && 3608 if (adapter->num_rx_queues == 1)
3246 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) { 3609 igb_set_itr(adapter);
3247 int mean_size = rx_ring->total_bytes / 3610 else
3248 rx_ring->total_packets; 3611 igb_update_ring_itr(rx_ring);
3249 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3250 igb_raise_rx_eitr(adapter, rx_ring);
3251 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3252 igb_lower_rx_eitr(adapter, rx_ring);
3253 } 3612 }
3613
3614 if (!test_bit(__IGB_DOWN, &adapter->state))
3615 wr32(E1000_EIMS, rx_ring->eims_value);
3616
3254 return 0; 3617 return 0;
3255 } 3618 }
3256 3619
@@ -3268,11 +3631,11 @@ static inline u32 get_head(struct igb_ring *tx_ring)
3268 * @adapter: board private structure 3631 * @adapter: board private structure
3269 * returns true if ring is completely cleaned 3632 * returns true if ring is completely cleaned
3270 **/ 3633 **/
3271static bool igb_clean_tx_irq(struct igb_adapter *adapter, 3634static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3272 struct igb_ring *tx_ring)
3273{ 3635{
3274 struct net_device *netdev = adapter->netdev; 3636 struct igb_adapter *adapter = tx_ring->adapter;
3275 struct e1000_hw *hw = &adapter->hw; 3637 struct e1000_hw *hw = &adapter->hw;
3638 struct net_device *netdev = adapter->netdev;
3276 struct e1000_tx_desc *tx_desc; 3639 struct e1000_tx_desc *tx_desc;
3277 struct igb_buffer *buffer_info; 3640 struct igb_buffer *buffer_info;
3278 struct sk_buff *skb; 3641 struct sk_buff *skb;
@@ -3334,9 +3697,9 @@ done_cleaning:
3334 * sees the new next_to_clean. 3697 * sees the new next_to_clean.
3335 */ 3698 */
3336 smp_mb(); 3699 smp_mb();
3337 if (netif_queue_stopped(netdev) && 3700 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3338 !(test_bit(__IGB_DOWN, &adapter->state))) { 3701 !(test_bit(__IGB_DOWN, &adapter->state))) {
3339 netif_wake_queue(netdev); 3702 netif_wake_subqueue(netdev, tx_ring->queue_index);
3340 ++adapter->restart_queue; 3703 ++adapter->restart_queue;
3341 } 3704 }
3342 } 3705 }
@@ -3355,7 +3718,7 @@ done_cleaning:
3355 /* detected Tx unit hang */ 3718 /* detected Tx unit hang */
3356 dev_err(&adapter->pdev->dev, 3719 dev_err(&adapter->pdev->dev,
3357 "Detected Tx Unit Hang\n" 3720 "Detected Tx Unit Hang\n"
3358 " Tx Queue <%lu>\n" 3721 " Tx Queue <%d>\n"
3359 " TDH <%x>\n" 3722 " TDH <%x>\n"
3360 " TDT <%x>\n" 3723 " TDT <%x>\n"
3361 " next_to_use <%x>\n" 3724 " next_to_use <%x>\n"
@@ -3365,8 +3728,7 @@ done_cleaning:
3365 " time_stamp <%lx>\n" 3728 " time_stamp <%lx>\n"
3366 " jiffies <%lx>\n" 3729 " jiffies <%lx>\n"
3367 " desc.status <%x>\n", 3730 " desc.status <%x>\n",
3368 (unsigned long)((tx_ring - adapter->tx_ring) / 3731 tx_ring->queue_index,
3369 sizeof(struct igb_ring)),
3370 readl(adapter->hw.hw_addr + tx_ring->head), 3732 readl(adapter->hw.hw_addr + tx_ring->head),
3371 readl(adapter->hw.hw_addr + tx_ring->tail), 3733 readl(adapter->hw.hw_addr + tx_ring->tail),
3372 tx_ring->next_to_use, 3734 tx_ring->next_to_use,
@@ -3375,33 +3737,87 @@ done_cleaning:
3375 tx_ring->buffer_info[i].time_stamp, 3737 tx_ring->buffer_info[i].time_stamp,
3376 jiffies, 3738 jiffies,
3377 tx_desc->upper.fields.status); 3739 tx_desc->upper.fields.status);
3378 netif_stop_queue(netdev); 3740 netif_stop_subqueue(netdev, tx_ring->queue_index);
3379 } 3741 }
3380 } 3742 }
3381 tx_ring->total_bytes += total_bytes; 3743 tx_ring->total_bytes += total_bytes;
3382 tx_ring->total_packets += total_packets; 3744 tx_ring->total_packets += total_packets;
3745 tx_ring->tx_stats.bytes += total_bytes;
3746 tx_ring->tx_stats.packets += total_packets;
3383 adapter->net_stats.tx_bytes += total_bytes; 3747 adapter->net_stats.tx_bytes += total_bytes;
3384 adapter->net_stats.tx_packets += total_packets; 3748 adapter->net_stats.tx_packets += total_packets;
3385 return retval; 3749 return retval;
3386} 3750}
3387 3751
3752#ifdef CONFIG_IGB_LRO
3753 /**
3754 * igb_get_skb_hdr - helper function for LRO header processing
3755 * @skb: pointer to sk_buff to be added to LRO packet
3756 * @iphdr: pointer to ip header structure
3757 * @tcph: pointer to tcp header structure
3758 * @hdr_flags: pointer to header flags
3759 * @priv: pointer to the receive descriptor for the current sk_buff
3760 **/
3761static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3762 u64 *hdr_flags, void *priv)
3763{
3764 union e1000_adv_rx_desc *rx_desc = priv;
3765 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3766 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3767
3768 /* Verify that this is a valid IPv4 TCP packet */
3769 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3770 E1000_RXDADV_PKTTYPE_TCP))
3771 return -1;
3772
3773 /* Set network headers */
3774 skb_reset_network_header(skb);
3775 skb_set_transport_header(skb, ip_hdrlen(skb));
3776 *iphdr = ip_hdr(skb);
3777 *tcph = tcp_hdr(skb);
3778 *hdr_flags = LRO_IPV4 | LRO_TCP;
3779
3780 return 0;
3781
3782}
3783#endif /* CONFIG_IGB_LRO */
3388 3784
3389/** 3785/**
3390 * igb_receive_skb - helper function to handle rx indications 3786 * igb_receive_skb - helper function to handle rx indications
3391 * @adapter: board private structure 3787 * @ring: pointer to receive ring receving this packet
3392 * @status: descriptor status field as written by hardware 3788 * @status: descriptor status field as written by hardware
3393 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 3789 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3394 * @skb: pointer to sk_buff to be indicated to stack 3790 * @skb: pointer to sk_buff to be indicated to stack
3395 **/ 3791 **/
3396static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan, 3792static void igb_receive_skb(struct igb_ring *ring, u8 status,
3397 struct sk_buff *skb) 3793 union e1000_adv_rx_desc * rx_desc,
3794 struct sk_buff *skb)
3398{ 3795{
3399 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP)) 3796 struct igb_adapter * adapter = ring->adapter;
3400 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 3797 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3401 le16_to_cpu(vlan) & 3798
3402 E1000_RXD_SPC_VLAN_MASK); 3799#ifdef CONFIG_IGB_LRO
3403 else 3800 if (adapter->netdev->features & NETIF_F_LRO &&
3404 netif_receive_skb(skb); 3801 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3802 if (vlan_extracted)
3803 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3804 adapter->vlgrp,
3805 le16_to_cpu(rx_desc->wb.upper.vlan),
3806 rx_desc);
3807 else
3808 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3809 ring->lro_used = 1;
3810 } else {
3811#endif
3812 if (vlan_extracted)
3813 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3814 le16_to_cpu(rx_desc->wb.upper.vlan));
3815 else
3816
3817 netif_receive_skb(skb);
3818#ifdef CONFIG_IGB_LRO
3819 }
3820#endif
3405} 3821}
3406 3822
3407 3823
@@ -3427,16 +3843,16 @@ static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3427 adapter->hw_csum_good++; 3843 adapter->hw_csum_good++;
3428} 3844}
3429 3845
3430static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter, 3846static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3431 struct igb_ring *rx_ring, 3847 int *work_done, int budget)
3432 int *work_done, int budget)
3433{ 3848{
3849 struct igb_adapter *adapter = rx_ring->adapter;
3434 struct net_device *netdev = adapter->netdev; 3850 struct net_device *netdev = adapter->netdev;
3435 struct pci_dev *pdev = adapter->pdev; 3851 struct pci_dev *pdev = adapter->pdev;
3436 union e1000_adv_rx_desc *rx_desc , *next_rxd; 3852 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3437 struct igb_buffer *buffer_info , *next_buffer; 3853 struct igb_buffer *buffer_info , *next_buffer;
3438 struct sk_buff *skb; 3854 struct sk_buff *skb;
3439 unsigned int i, j; 3855 unsigned int i;
3440 u32 length, hlen, staterr; 3856 u32 length, hlen, staterr;
3441 bool cleaned = false; 3857 bool cleaned = false;
3442 int cleaned_count = 0; 3858 int cleaned_count = 0;
@@ -3466,64 +3882,48 @@ static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3466 cleaned = true; 3882 cleaned = true;
3467 cleaned_count++; 3883 cleaned_count++;
3468 3884
3469 if (rx_ring->pending_skb != NULL) { 3885 skb = buffer_info->skb;
3470 skb = rx_ring->pending_skb; 3886 prefetch(skb->data - NET_IP_ALIGN);
3471 rx_ring->pending_skb = NULL; 3887 buffer_info->skb = NULL;
3472 j = rx_ring->pending_skb_page; 3888 if (!adapter->rx_ps_hdr_size) {
3473 } else { 3889 pci_unmap_single(pdev, buffer_info->dma,
3474 skb = buffer_info->skb; 3890 adapter->rx_buffer_len +
3475 prefetch(skb->data - NET_IP_ALIGN); 3891 NET_IP_ALIGN,
3476 buffer_info->skb = NULL; 3892 PCI_DMA_FROMDEVICE);
3477 if (hlen) { 3893 skb_put(skb, length);
3478 pci_unmap_single(pdev, buffer_info->dma, 3894 goto send_up;
3479 adapter->rx_ps_hdr_size + 3895 }
3480 NET_IP_ALIGN, 3896
3481 PCI_DMA_FROMDEVICE); 3897 if (!skb_shinfo(skb)->nr_frags) {
3482 skb_put(skb, hlen); 3898 pci_unmap_single(pdev, buffer_info->dma,
3483 } else { 3899 adapter->rx_ps_hdr_size +
3484 pci_unmap_single(pdev, buffer_info->dma, 3900 NET_IP_ALIGN,
3485 adapter->rx_buffer_len + 3901 PCI_DMA_FROMDEVICE);
3486 NET_IP_ALIGN, 3902 skb_put(skb, hlen);
3487 PCI_DMA_FROMDEVICE);
3488 skb_put(skb, length);
3489 goto send_up;
3490 }
3491 j = 0;
3492 } 3903 }
3493 3904
3494 while (length) { 3905 if (length) {
3495 pci_unmap_page(pdev, buffer_info->page_dma, 3906 pci_unmap_page(pdev, buffer_info->page_dma,
3496 PAGE_SIZE, PCI_DMA_FROMDEVICE); 3907 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3497 buffer_info->page_dma = 0; 3908 buffer_info->page_dma = 0;
3498 skb_fill_page_desc(skb, j, buffer_info->page, 3909
3499 0, length); 3910 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3500 buffer_info->page = NULL; 3911 buffer_info->page,
3912 buffer_info->page_offset,
3913 length);
3914
3915 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3916 (page_count(buffer_info->page) != 1))
3917 buffer_info->page = NULL;
3918 else
3919 get_page(buffer_info->page);
3501 3920
3502 skb->len += length; 3921 skb->len += length;
3503 skb->data_len += length; 3922 skb->data_len += length;
3504 skb->truesize += length;
3505 rx_desc->wb.upper.status_error = 0;
3506 if (staterr & E1000_RXD_STAT_EOP)
3507 break;
3508 3923
3509 j++; 3924 skb->truesize += length;
3510 cleaned_count++;
3511 i++;
3512 if (i == rx_ring->count)
3513 i = 0;
3514
3515 buffer_info = &rx_ring->buffer_info[i];
3516 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3517 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3518 length = le16_to_cpu(rx_desc->wb.upper.length);
3519 if (!(staterr & E1000_RXD_STAT_DD)) {
3520 rx_ring->pending_skb = skb;
3521 rx_ring->pending_skb_page = j;
3522 goto out;
3523 }
3524 } 3925 }
3525send_up: 3926send_up:
3526 pskb_trim(skb, skb->len - 4);
3527 i++; 3927 i++;
3528 if (i == rx_ring->count) 3928 if (i == rx_ring->count)
3529 i = 0; 3929 i = 0;
@@ -3531,11 +3931,16 @@ send_up:
3531 prefetch(next_rxd); 3931 prefetch(next_rxd);
3532 next_buffer = &rx_ring->buffer_info[i]; 3932 next_buffer = &rx_ring->buffer_info[i];
3533 3933
3934 if (!(staterr & E1000_RXD_STAT_EOP)) {
3935 buffer_info->skb = xchg(&next_buffer->skb, skb);
3936 buffer_info->dma = xchg(&next_buffer->dma, 0);
3937 goto next_desc;
3938 }
3939
3534 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { 3940 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3535 dev_kfree_skb_irq(skb); 3941 dev_kfree_skb_irq(skb);
3536 goto next_desc; 3942 goto next_desc;
3537 } 3943 }
3538 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3539 3944
3540 total_bytes += skb->len; 3945 total_bytes += skb->len;
3541 total_packets++; 3946 total_packets++;
@@ -3544,7 +3949,7 @@ send_up:
3544 3949
3545 skb->protocol = eth_type_trans(skb, netdev); 3950 skb->protocol = eth_type_trans(skb, netdev);
3546 3951
3547 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb); 3952 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3548 3953
3549 netdev->last_rx = jiffies; 3954 netdev->last_rx = jiffies;
3550 3955
@@ -3553,8 +3958,7 @@ next_desc:
3553 3958
3554 /* return some buffers to hardware, one at a time is too slow */ 3959 /* return some buffers to hardware, one at a time is too slow */
3555 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 3960 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3556 igb_alloc_rx_buffers_adv(adapter, rx_ring, 3961 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3557 cleaned_count);
3558 cleaned_count = 0; 3962 cleaned_count = 0;
3559 } 3963 }
3560 3964
@@ -3564,12 +3968,19 @@ next_desc:
3564 3968
3565 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 3969 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3566 } 3970 }
3567out: 3971
3568 rx_ring->next_to_clean = i; 3972 rx_ring->next_to_clean = i;
3569 cleaned_count = IGB_DESC_UNUSED(rx_ring); 3973 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3570 3974
3975#ifdef CONFIG_IGB_LRO
3976 if (rx_ring->lro_used) {
3977 lro_flush_all(&rx_ring->lro_mgr);
3978 rx_ring->lro_used = 0;
3979 }
3980#endif
3981
3571 if (cleaned_count) 3982 if (cleaned_count)
3572 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count); 3983 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3573 3984
3574 rx_ring->total_packets += total_packets; 3985 rx_ring->total_packets += total_packets;
3575 rx_ring->total_bytes += total_bytes; 3986 rx_ring->total_bytes += total_bytes;
@@ -3585,10 +3996,10 @@ out:
3585 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split 3996 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3586 * @adapter: address of board private structure 3997 * @adapter: address of board private structure
3587 **/ 3998 **/
3588static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter, 3999static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3589 struct igb_ring *rx_ring,
3590 int cleaned_count) 4000 int cleaned_count)
3591{ 4001{
4002 struct igb_adapter *adapter = rx_ring->adapter;
3592 struct net_device *netdev = adapter->netdev; 4003 struct net_device *netdev = adapter->netdev;
3593 struct pci_dev *pdev = adapter->pdev; 4004 struct pci_dev *pdev = adapter->pdev;
3594 union e1000_adv_rx_desc *rx_desc; 4005 union e1000_adv_rx_desc *rx_desc;
@@ -3602,16 +4013,22 @@ static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3602 while (cleaned_count--) { 4013 while (cleaned_count--) {
3603 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); 4014 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3604 4015
3605 if (adapter->rx_ps_hdr_size && !buffer_info->page) { 4016 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
3606 buffer_info->page = alloc_page(GFP_ATOMIC);
3607 if (!buffer_info->page) { 4017 if (!buffer_info->page) {
3608 adapter->alloc_rx_buff_failed++; 4018 buffer_info->page = alloc_page(GFP_ATOMIC);
3609 goto no_buffers; 4019 if (!buffer_info->page) {
4020 adapter->alloc_rx_buff_failed++;
4021 goto no_buffers;
4022 }
4023 buffer_info->page_offset = 0;
4024 } else {
4025 buffer_info->page_offset ^= PAGE_SIZE / 2;
3610 } 4026 }
3611 buffer_info->page_dma = 4027 buffer_info->page_dma =
3612 pci_map_page(pdev, 4028 pci_map_page(pdev,
3613 buffer_info->page, 4029 buffer_info->page,
3614 0, PAGE_SIZE, 4030 buffer_info->page_offset,
4031 PAGE_SIZE / 2,
3615 PCI_DMA_FROMDEVICE); 4032 PCI_DMA_FROMDEVICE);
3616 } 4033 }
3617 4034
@@ -3746,7 +4163,6 @@ static void igb_vlan_rx_register(struct net_device *netdev,
3746 4163
3747 /* enable VLAN receive filtering */ 4164 /* enable VLAN receive filtering */
3748 rctl = rd32(E1000_RCTL); 4165 rctl = rd32(E1000_RCTL);
3749 rctl |= E1000_RCTL_VFE;
3750 rctl &= ~E1000_RCTL_CFIEN; 4166 rctl &= ~E1000_RCTL_CFIEN;
3751 wr32(E1000_RCTL, rctl); 4167 wr32(E1000_RCTL, rctl);
3752 igb_update_mng_vlan(adapter); 4168 igb_update_mng_vlan(adapter);
@@ -3758,10 +4174,6 @@ static void igb_vlan_rx_register(struct net_device *netdev,
3758 ctrl &= ~E1000_CTRL_VME; 4174 ctrl &= ~E1000_CTRL_VME;
3759 wr32(E1000_CTRL, ctrl); 4175 wr32(E1000_CTRL, ctrl);
3760 4176
3761 /* disable VLAN filtering */
3762 rctl = rd32(E1000_RCTL);
3763 rctl &= ~E1000_RCTL_VFE;
3764 wr32(E1000_RCTL, rctl);
3765 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) { 4177 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3766 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4178 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3767 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 4179 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
@@ -3878,7 +4290,7 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3878 struct net_device *netdev = pci_get_drvdata(pdev); 4290 struct net_device *netdev = pci_get_drvdata(pdev);
3879 struct igb_adapter *adapter = netdev_priv(netdev); 4291 struct igb_adapter *adapter = netdev_priv(netdev);
3880 struct e1000_hw *hw = &adapter->hw; 4292 struct e1000_hw *hw = &adapter->hw;
3881 u32 ctrl, ctrl_ext, rctl, status; 4293 u32 ctrl, rctl, status;
3882 u32 wufc = adapter->wol; 4294 u32 wufc = adapter->wol;
3883#ifdef CONFIG_PM 4295#ifdef CONFIG_PM
3884 int retval = 0; 4296 int retval = 0;
@@ -3886,11 +4298,12 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3886 4298
3887 netif_device_detach(netdev); 4299 netif_device_detach(netdev);
3888 4300
3889 if (netif_running(netdev)) { 4301 if (netif_running(netdev))
3890 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4302 igb_close(netdev);
3891 igb_down(adapter); 4303
3892 igb_free_irq(adapter); 4304 igb_reset_interrupt_capability(adapter);
3893 } 4305
4306 igb_free_queues(adapter);
3894 4307
3895#ifdef CONFIG_PM 4308#ifdef CONFIG_PM
3896 retval = pci_save_state(pdev); 4309 retval = pci_save_state(pdev);
@@ -3921,33 +4334,24 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3921 ctrl |= E1000_CTRL_ADVD3WUC; 4334 ctrl |= E1000_CTRL_ADVD3WUC;
3922 wr32(E1000_CTRL, ctrl); 4335 wr32(E1000_CTRL, ctrl);
3923 4336
3924 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3925 adapter->hw.phy.media_type ==
3926 e1000_media_type_internal_serdes) {
3927 /* keep the laser running in D3 */
3928 ctrl_ext = rd32(E1000_CTRL_EXT);
3929 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3930 wr32(E1000_CTRL_EXT, ctrl_ext);
3931 }
3932
3933 /* Allow time for pending master requests to run */ 4337 /* Allow time for pending master requests to run */
3934 igb_disable_pcie_master(&adapter->hw); 4338 igb_disable_pcie_master(&adapter->hw);
3935 4339
3936 wr32(E1000_WUC, E1000_WUC_PME_EN); 4340 wr32(E1000_WUC, E1000_WUC_PME_EN);
3937 wr32(E1000_WUFC, wufc); 4341 wr32(E1000_WUFC, wufc);
3938 pci_enable_wake(pdev, PCI_D3hot, 1);
3939 pci_enable_wake(pdev, PCI_D3cold, 1);
3940 } else { 4342 } else {
3941 wr32(E1000_WUC, 0); 4343 wr32(E1000_WUC, 0);
3942 wr32(E1000_WUFC, 0); 4344 wr32(E1000_WUFC, 0);
3943 pci_enable_wake(pdev, PCI_D3hot, 0);
3944 pci_enable_wake(pdev, PCI_D3cold, 0);
3945 } 4345 }
3946 4346
3947 /* make sure adapter isn't asleep if manageability is enabled */ 4347 /* make sure adapter isn't asleep if manageability/wol is enabled */
3948 if (adapter->en_mng_pt) { 4348 if (wufc || adapter->en_mng_pt) {
3949 pci_enable_wake(pdev, PCI_D3hot, 1); 4349 pci_enable_wake(pdev, PCI_D3hot, 1);
3950 pci_enable_wake(pdev, PCI_D3cold, 1); 4350 pci_enable_wake(pdev, PCI_D3cold, 1);
4351 } else {
4352 igb_shutdown_fiber_serdes_link_82575(hw);
4353 pci_enable_wake(pdev, PCI_D3hot, 0);
4354 pci_enable_wake(pdev, PCI_D3cold, 0);
3951 } 4355 }
3952 4356
3953 /* Release control of h/w to f/w. If f/w is AMT enabled, this 4357 /* Release control of h/w to f/w. If f/w is AMT enabled, this
@@ -3971,7 +4375,11 @@ static int igb_resume(struct pci_dev *pdev)
3971 4375
3972 pci_set_power_state(pdev, PCI_D0); 4376 pci_set_power_state(pdev, PCI_D0);
3973 pci_restore_state(pdev); 4377 pci_restore_state(pdev);
3974 err = pci_enable_device(pdev); 4378
4379 if (adapter->need_ioport)
4380 err = pci_enable_device(pdev);
4381 else
4382 err = pci_enable_device_mem(pdev);
3975 if (err) { 4383 if (err) {
3976 dev_err(&pdev->dev, 4384 dev_err(&pdev->dev,
3977 "igb: Cannot enable PCI device from suspend\n"); 4385 "igb: Cannot enable PCI device from suspend\n");
@@ -3982,10 +4390,11 @@ static int igb_resume(struct pci_dev *pdev)
3982 pci_enable_wake(pdev, PCI_D3hot, 0); 4390 pci_enable_wake(pdev, PCI_D3hot, 0);
3983 pci_enable_wake(pdev, PCI_D3cold, 0); 4391 pci_enable_wake(pdev, PCI_D3cold, 0);
3984 4392
3985 if (netif_running(netdev)) { 4393 igb_set_interrupt_capability(adapter);
3986 err = igb_request_irq(adapter); 4394
3987 if (err) 4395 if (igb_alloc_queues(adapter)) {
3988 return err; 4396 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4397 return -ENOMEM;
3989 } 4398 }
3990 4399
3991 /* e1000_power_up_phy(adapter); */ 4400 /* e1000_power_up_phy(adapter); */
@@ -3993,10 +4402,11 @@ static int igb_resume(struct pci_dev *pdev)
3993 igb_reset(adapter); 4402 igb_reset(adapter);
3994 wr32(E1000_WUS, ~0); 4403 wr32(E1000_WUS, ~0);
3995 4404
3996 igb_init_manageability(adapter); 4405 if (netif_running(netdev)) {
3997 4406 err = igb_open(netdev);
3998 if (netif_running(netdev)) 4407 if (err)
3999 igb_up(adapter); 4408 return err;
4409 }
4000 4410
4001 netif_device_attach(netdev); 4411 netif_device_attach(netdev);
4002 4412
@@ -4026,14 +4436,17 @@ static void igb_netpoll(struct net_device *netdev)
4026 int work_done = 0; 4436 int work_done = 0;
4027 4437
4028 igb_irq_disable(adapter); 4438 igb_irq_disable(adapter);
4439 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4440
4029 for (i = 0; i < adapter->num_tx_queues; i++) 4441 for (i = 0; i < adapter->num_tx_queues; i++)
4030 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]); 4442 igb_clean_tx_irq(&adapter->tx_ring[i]);
4031 4443
4032 for (i = 0; i < adapter->num_rx_queues; i++) 4444 for (i = 0; i < adapter->num_rx_queues; i++)
4033 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], 4445 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4034 &work_done, 4446 &work_done,
4035 adapter->rx_ring[i].napi.weight); 4447 adapter->rx_ring[i].napi.weight);
4036 4448
4449 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
4037 igb_irq_enable(adapter); 4450 igb_irq_enable(adapter);
4038} 4451}
4039#endif /* CONFIG_NET_POLL_CONTROLLER */ 4452#endif /* CONFIG_NET_POLL_CONTROLLER */
@@ -4074,8 +4487,13 @@ static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4074 struct net_device *netdev = pci_get_drvdata(pdev); 4487 struct net_device *netdev = pci_get_drvdata(pdev);
4075 struct igb_adapter *adapter = netdev_priv(netdev); 4488 struct igb_adapter *adapter = netdev_priv(netdev);
4076 struct e1000_hw *hw = &adapter->hw; 4489 struct e1000_hw *hw = &adapter->hw;
4490 int err;
4077 4491
4078 if (pci_enable_device(pdev)) { 4492 if (adapter->need_ioport)
4493 err = pci_enable_device(pdev);
4494 else
4495 err = pci_enable_device_mem(pdev);
4496 if (err) {
4079 dev_err(&pdev->dev, 4497 dev_err(&pdev->dev,
4080 "Cannot re-enable PCI device after reset.\n"); 4498 "Cannot re-enable PCI device after reset.\n");
4081 return PCI_ERS_RESULT_DISCONNECT; 4499 return PCI_ERS_RESULT_DISCONNECT;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 07:58:44 -0500