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-rw-r--r--drivers/net/igb/e1000_defines.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index c58c4fdfee0c..6e036ae3138f 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -330,6 +330,7 @@
330#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 330#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
331#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 331#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
332#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 332#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
333#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
333/* If this bit asserted, the driver should claim the interrupt */ 334/* If this bit asserted, the driver should claim the interrupt */
334#define E1000_ICR_INT_ASSERTED 0x80000000 335#define E1000_ICR_INT_ASSERTED 0x80000000
335/* LAN connected device generates an interrupt */ 336/* LAN connected device generates an interrupt */
@@ -371,6 +372,7 @@
371#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 372#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
372#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 373#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
373#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 374#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
375#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
374#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 376#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
375 377
376/* Extended Interrupt Mask Set */ 378/* Extended Interrupt Mask Set */
@@ -379,6 +381,7 @@
379/* Interrupt Cause Set */ 381/* Interrupt Cause Set */
380#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 382#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
381#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 383#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
384#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
382 385
383/* Extended Interrupt Cause Set */ 386/* Extended Interrupt Cause Set */
384 387
@@ -717,4 +720,8 @@
717#define E1000_VFTA_ENTRY_MASK 0x7F 720#define E1000_VFTA_ENTRY_MASK 0x7F
718#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 721#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
719 722
723/* DMA Coalescing register fields */
724#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based
725 on DMA coal */
726
720#endif 727#endif