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path: root/drivers/net/igb/e1000_82575.h
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Diffstat (limited to 'drivers/net/igb/e1000_82575.h')
-rw-r--r--drivers/net/igb/e1000_82575.h16
1 files changed, 2 insertions, 14 deletions
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index e613d5a606d8..49b41c92a8c8 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -58,9 +58,6 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
58 E1000_EICR_RX_QUEUE2 | \ 58 E1000_EICR_RX_QUEUE2 | \
59 E1000_EICR_RX_QUEUE3) 59 E1000_EICR_RX_QUEUE3)
60 60
61#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
62#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
63
64/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 61/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
65 62
66/* Receive Descriptor - Advanced */ 63/* Receive Descriptor - Advanced */
@@ -95,12 +92,6 @@ union e1000_adv_rx_desc {
95#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 92#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
96#define E1000_RXDADV_HDRBUFLEN_SHIFT 5 93#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
97 94
98/* RSS Hash results */
99
100/* RSS Packet Types as indicated in the receive descriptor */
101#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
102#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
103
104/* Transmit Descriptor - Advanced */ 95/* Transmit Descriptor - Advanced */
105union e1000_adv_tx_desc { 96union e1000_adv_tx_desc {
106 struct { 97 struct {
@@ -150,11 +141,8 @@ struct e1000_adv_tx_context_desc {
150#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 141#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
151 142
152/* Direct Cache Access (DCA) definitions */ 143/* Direct Cache Access (DCA) definitions */
153#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 144#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
154#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 145#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
155
156#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
157#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
158 146
159#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 147#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
160#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 148#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */