diff options
Diffstat (limited to 'drivers/net/igb/e1000_82575.c')
-rw-r--r-- | drivers/net/igb/e1000_82575.c | 208 |
1 files changed, 195 insertions, 13 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c index 2c8b91060d98..e098f234770f 100644 --- a/drivers/net/igb/e1000_82575.c +++ b/drivers/net/igb/e1000_82575.c | |||
@@ -31,6 +31,7 @@ | |||
31 | 31 | ||
32 | #include <linux/types.h> | 32 | #include <linux/types.h> |
33 | #include <linux/slab.h> | 33 | #include <linux/slab.h> |
34 | #include <linux/if_ether.h> | ||
34 | 35 | ||
35 | #include "e1000_mac.h" | 36 | #include "e1000_mac.h" |
36 | #include "e1000_82575.h" | 37 | #include "e1000_82575.h" |
@@ -45,7 +46,6 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |||
45 | static s32 igb_init_hw_82575(struct e1000_hw *); | 46 | static s32 igb_init_hw_82575(struct e1000_hw *); |
46 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | 47 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); |
47 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | 48 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); |
48 | static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32); | ||
49 | static s32 igb_reset_hw_82575(struct e1000_hw *); | 49 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); | 50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | 51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); |
@@ -84,6 +84,12 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) | |||
84 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | 84 | case E1000_DEV_ID_82575GB_QUAD_COPPER: |
85 | mac->type = e1000_82575; | 85 | mac->type = e1000_82575; |
86 | break; | 86 | break; |
87 | case E1000_DEV_ID_82576: | ||
88 | case E1000_DEV_ID_82576_FIBER: | ||
89 | case E1000_DEV_ID_82576_SERDES: | ||
90 | case E1000_DEV_ID_82576_QUAD_COPPER: | ||
91 | mac->type = e1000_82576; | ||
92 | break; | ||
87 | default: | 93 | default: |
88 | return -E1000_ERR_MAC_INIT; | 94 | return -E1000_ERR_MAC_INIT; |
89 | break; | 95 | break; |
@@ -128,6 +134,8 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) | |||
128 | mac->mta_reg_count = 128; | 134 | mac->mta_reg_count = 128; |
129 | /* Set rar entry count */ | 135 | /* Set rar entry count */ |
130 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | 136 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; |
137 | if (mac->type == e1000_82576) | ||
138 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | ||
131 | /* Set if part includes ASF firmware */ | 139 | /* Set if part includes ASF firmware */ |
132 | mac->asf_firmware_present = true; | 140 | mac->asf_firmware_present = true; |
133 | /* Set if manageability features are enabled. */ | 141 | /* Set if manageability features are enabled. */ |
@@ -694,13 +702,12 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |||
694 | if ((hw->phy.media_type != e1000_media_type_copper) || | 702 | if ((hw->phy.media_type != e1000_media_type_copper) || |
695 | (igb_sgmii_active_82575(hw))) | 703 | (igb_sgmii_active_82575(hw))) |
696 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, | 704 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
697 | &duplex); | 705 | &duplex); |
698 | else | 706 | else |
699 | ret_val = igb_check_for_copper_link(hw); | 707 | ret_val = igb_check_for_copper_link(hw); |
700 | 708 | ||
701 | return ret_val; | 709 | return ret_val; |
702 | } | 710 | } |
703 | |||
704 | /** | 711 | /** |
705 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex | 712 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
706 | * @hw: pointer to the HW structure | 713 | * @hw: pointer to the HW structure |
@@ -757,18 +764,129 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |||
757 | } | 764 | } |
758 | 765 | ||
759 | /** | 766 | /** |
760 | * igb_rar_set_82575 - Set receive address register | 767 | * igb_init_rx_addrs_82575 - Initialize receive address's |
768 | * @hw: pointer to the HW structure | ||
769 | * @rar_count: receive address registers | ||
770 | * | ||
771 | * Setups the receive address registers by setting the base receive address | ||
772 | * register to the devices MAC address and clearing all the other receive | ||
773 | * address registers to 0. | ||
774 | **/ | ||
775 | static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count) | ||
776 | { | ||
777 | u32 i; | ||
778 | u8 addr[6] = {0,0,0,0,0,0}; | ||
779 | /* | ||
780 | * This function is essentially the same as that of | ||
781 | * e1000_init_rx_addrs_generic. However it also takes care | ||
782 | * of the special case where the register offset of the | ||
783 | * second set of RARs begins elsewhere. This is implicitly taken care by | ||
784 | * function e1000_rar_set_generic. | ||
785 | */ | ||
786 | |||
787 | hw_dbg("e1000_init_rx_addrs_82575"); | ||
788 | |||
789 | /* Setup the receive address */ | ||
790 | hw_dbg("Programming MAC Address into RAR[0]\n"); | ||
791 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); | ||
792 | |||
793 | /* Zero out the other (rar_entry_count - 1) receive addresses */ | ||
794 | hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); | ||
795 | for (i = 1; i < rar_count; i++) | ||
796 | hw->mac.ops.rar_set(hw, addr, i); | ||
797 | } | ||
798 | |||
799 | /** | ||
800 | * igb_update_mc_addr_list_82575 - Update Multicast addresses | ||
801 | * @hw: pointer to the HW structure | ||
802 | * @mc_addr_list: array of multicast addresses to program | ||
803 | * @mc_addr_count: number of multicast addresses to program | ||
804 | * @rar_used_count: the first RAR register free to program | ||
805 | * @rar_count: total number of supported Receive Address Registers | ||
806 | * | ||
807 | * Updates the Receive Address Registers and Multicast Table Array. | ||
808 | * The caller must have a packed mc_addr_list of multicast addresses. | ||
809 | * The parameter rar_count will usually be hw->mac.rar_entry_count | ||
810 | * unless there are workarounds that change this. | ||
811 | **/ | ||
812 | void igb_update_mc_addr_list_82575(struct e1000_hw *hw, | ||
813 | u8 *mc_addr_list, u32 mc_addr_count, | ||
814 | u32 rar_used_count, u32 rar_count) | ||
815 | { | ||
816 | u32 hash_value; | ||
817 | u32 i; | ||
818 | u8 addr[6] = {0,0,0,0,0,0}; | ||
819 | /* | ||
820 | * This function is essentially the same as that of | ||
821 | * igb_update_mc_addr_list_generic. However it also takes care | ||
822 | * of the special case where the register offset of the | ||
823 | * second set of RARs begins elsewhere. This is implicitly taken care by | ||
824 | * function e1000_rar_set_generic. | ||
825 | */ | ||
826 | |||
827 | /* | ||
828 | * Load the first set of multicast addresses into the exact | ||
829 | * filters (RAR). If there are not enough to fill the RAR | ||
830 | * array, clear the filters. | ||
831 | */ | ||
832 | for (i = rar_used_count; i < rar_count; i++) { | ||
833 | if (mc_addr_count) { | ||
834 | igb_rar_set(hw, mc_addr_list, i); | ||
835 | mc_addr_count--; | ||
836 | mc_addr_list += ETH_ALEN; | ||
837 | } else { | ||
838 | igb_rar_set(hw, addr, i); | ||
839 | } | ||
840 | } | ||
841 | |||
842 | /* Clear the old settings from the MTA */ | ||
843 | hw_dbg("Clearing MTA\n"); | ||
844 | for (i = 0; i < hw->mac.mta_reg_count; i++) { | ||
845 | array_wr32(E1000_MTA, i, 0); | ||
846 | wrfl(); | ||
847 | } | ||
848 | |||
849 | /* Load any remaining multicast addresses into the hash table. */ | ||
850 | for (; mc_addr_count > 0; mc_addr_count--) { | ||
851 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); | ||
852 | hw_dbg("Hash value = 0x%03X\n", hash_value); | ||
853 | hw->mac.ops.mta_set(hw, hash_value); | ||
854 | mc_addr_list += ETH_ALEN; | ||
855 | } | ||
856 | } | ||
857 | |||
858 | /** | ||
859 | * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down | ||
761 | * @hw: pointer to the HW structure | 860 | * @hw: pointer to the HW structure |
762 | * @addr: pointer to the receive address | ||
763 | * @index: receive address array register | ||
764 | * | 861 | * |
765 | * Sets the receive address array register at index to the address passed | 862 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
766 | * in by addr. | 863 | * when management pass thru is not enabled. |
767 | **/ | 864 | **/ |
768 | static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index) | 865 | void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) |
769 | { | 866 | { |
770 | if (index < E1000_RAR_ENTRIES_82575) | 867 | u32 reg; |
771 | igb_rar_set(hw, addr, index); | 868 | |
869 | if (hw->mac.type != e1000_82576 || | ||
870 | (hw->phy.media_type != e1000_media_type_fiber && | ||
871 | hw->phy.media_type != e1000_media_type_internal_serdes)) | ||
872 | return; | ||
873 | |||
874 | /* if the management interface is not enabled, then power down */ | ||
875 | if (!igb_enable_mng_pass_thru(hw)) { | ||
876 | /* Disable PCS to turn off link */ | ||
877 | reg = rd32(E1000_PCS_CFG0); | ||
878 | reg &= ~E1000_PCS_CFG_PCS_EN; | ||
879 | wr32(E1000_PCS_CFG0, reg); | ||
880 | |||
881 | /* shutdown the laser */ | ||
882 | reg = rd32(E1000_CTRL_EXT); | ||
883 | reg |= E1000_CTRL_EXT_SDP7_DATA; | ||
884 | wr32(E1000_CTRL_EXT, reg); | ||
885 | |||
886 | /* flush the write to verify completion */ | ||
887 | wrfl(); | ||
888 | msleep(1); | ||
889 | } | ||
772 | 890 | ||
773 | return; | 891 | return; |
774 | } | 892 | } |
@@ -854,7 +972,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw) | |||
854 | igb_clear_vfta(hw); | 972 | igb_clear_vfta(hw); |
855 | 973 | ||
856 | /* Setup the receive address */ | 974 | /* Setup the receive address */ |
857 | igb_init_rx_addrs(hw, rar_count); | 975 | igb_init_rx_addrs_82575(hw, rar_count); |
858 | /* Zero out the Multicast HASH table */ | 976 | /* Zero out the Multicast HASH table */ |
859 | hw_dbg("Zeroing the MTA\n"); | 977 | hw_dbg("Zeroing the MTA\n"); |
860 | for (i = 0; i < mac->mta_reg_count; i++) | 978 | for (i = 0; i < mac->mta_reg_count; i++) |
@@ -1114,6 +1232,70 @@ out: | |||
1114 | } | 1232 | } |
1115 | 1233 | ||
1116 | /** | 1234 | /** |
1235 | * igb_translate_register_82576 - Translate the proper register offset | ||
1236 | * @reg: e1000 register to be read | ||
1237 | * | ||
1238 | * Registers in 82576 are located in different offsets than other adapters | ||
1239 | * even though they function in the same manner. This function takes in | ||
1240 | * the name of the register to read and returns the correct offset for | ||
1241 | * 82576 silicon. | ||
1242 | **/ | ||
1243 | u32 igb_translate_register_82576(u32 reg) | ||
1244 | { | ||
1245 | /* | ||
1246 | * Some of the Kawela registers are located at different | ||
1247 | * offsets than they are in older adapters. | ||
1248 | * Despite the difference in location, the registers | ||
1249 | * function in the same manner. | ||
1250 | */ | ||
1251 | switch (reg) { | ||
1252 | case E1000_TDBAL(0): | ||
1253 | reg = 0x0E000; | ||
1254 | break; | ||
1255 | case E1000_TDBAH(0): | ||
1256 | reg = 0x0E004; | ||
1257 | break; | ||
1258 | case E1000_TDLEN(0): | ||
1259 | reg = 0x0E008; | ||
1260 | break; | ||
1261 | case E1000_TDH(0): | ||
1262 | reg = 0x0E010; | ||
1263 | break; | ||
1264 | case E1000_TDT(0): | ||
1265 | reg = 0x0E018; | ||
1266 | break; | ||
1267 | case E1000_TXDCTL(0): | ||
1268 | reg = 0x0E028; | ||
1269 | break; | ||
1270 | case E1000_RDBAL(0): | ||
1271 | reg = 0x0C000; | ||
1272 | break; | ||
1273 | case E1000_RDBAH(0): | ||
1274 | reg = 0x0C004; | ||
1275 | break; | ||
1276 | case E1000_RDLEN(0): | ||
1277 | reg = 0x0C008; | ||
1278 | break; | ||
1279 | case E1000_RDH(0): | ||
1280 | reg = 0x0C010; | ||
1281 | break; | ||
1282 | case E1000_RDT(0): | ||
1283 | reg = 0x0C018; | ||
1284 | break; | ||
1285 | case E1000_RXDCTL(0): | ||
1286 | reg = 0x0C028; | ||
1287 | break; | ||
1288 | case E1000_SRRCTL(0): | ||
1289 | reg = 0x0C00C; | ||
1290 | break; | ||
1291 | default: | ||
1292 | break; | ||
1293 | } | ||
1294 | |||
1295 | return reg; | ||
1296 | } | ||
1297 | |||
1298 | /** | ||
1117 | * igb_reset_init_script_82575 - Inits HW defaults after reset | 1299 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
1118 | * @hw: pointer to the HW structure | 1300 | * @hw: pointer to the HW structure |
1119 | * | 1301 | * |
@@ -1304,7 +1486,7 @@ static struct e1000_mac_operations e1000_mac_ops_82575 = { | |||
1304 | .reset_hw = igb_reset_hw_82575, | 1486 | .reset_hw = igb_reset_hw_82575, |
1305 | .init_hw = igb_init_hw_82575, | 1487 | .init_hw = igb_init_hw_82575, |
1306 | .check_for_link = igb_check_for_link_82575, | 1488 | .check_for_link = igb_check_for_link_82575, |
1307 | .rar_set = igb_rar_set_82575, | 1489 | .rar_set = igb_rar_set, |
1308 | .read_mac_addr = igb_read_mac_addr_82575, | 1490 | .read_mac_addr = igb_read_mac_addr_82575, |
1309 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | 1491 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, |
1310 | }; | 1492 | }; |