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path: root/drivers/net/ibm_newemac/phy.c
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-rw-r--r--drivers/net/ibm_newemac/phy.c373
1 files changed, 373 insertions, 0 deletions
diff --git a/drivers/net/ibm_newemac/phy.c b/drivers/net/ibm_newemac/phy.c
new file mode 100644
index 000000000000..aa1f0ddf1e3e
--- /dev/null
+++ b/drivers/net/ibm_newemac/phy.c
@@ -0,0 +1,373 @@
1/*
2 * drivers/net/ibm_newemac/phy.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * Borrowed from sungem_phy.c, though I only kept the generic MII
6 * driver for now.
7 *
8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib
10 *
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
13 *
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/delay.h>
22
23#include "emac.h"
24#include "phy.h"
25
26static inline int phy_read(struct mii_phy *phy, int reg)
27{
28 return phy->mdio_read(phy->dev, phy->address, reg);
29}
30
31static inline void phy_write(struct mii_phy *phy, int reg, int val)
32{
33 phy->mdio_write(phy->dev, phy->address, reg, val);
34}
35
36int emac_mii_reset_phy(struct mii_phy *phy)
37{
38 int val;
39 int limit = 10000;
40
41 val = phy_read(phy, MII_BMCR);
42 val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
43 val |= BMCR_RESET;
44 phy_write(phy, MII_BMCR, val);
45
46 udelay(300);
47
48 while (limit--) {
49 val = phy_read(phy, MII_BMCR);
50 if (val >= 0 && (val & BMCR_RESET) == 0)
51 break;
52 udelay(10);
53 }
54 if ((val & BMCR_ISOLATE) && limit > 0)
55 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
56
57 return limit <= 0;
58}
59
60static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
61{
62 int ctl, adv;
63
64 phy->autoneg = AUTONEG_ENABLE;
65 phy->speed = SPEED_10;
66 phy->duplex = DUPLEX_HALF;
67 phy->pause = phy->asym_pause = 0;
68 phy->advertising = advertise;
69
70 ctl = phy_read(phy, MII_BMCR);
71 if (ctl < 0)
72 return ctl;
73 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
74
75 /* First clear the PHY */
76 phy_write(phy, MII_BMCR, ctl);
77
78 /* Setup standard advertise */
79 adv = phy_read(phy, MII_ADVERTISE);
80 if (adv < 0)
81 return adv;
82 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
83 ADVERTISE_PAUSE_ASYM);
84 if (advertise & ADVERTISED_10baseT_Half)
85 adv |= ADVERTISE_10HALF;
86 if (advertise & ADVERTISED_10baseT_Full)
87 adv |= ADVERTISE_10FULL;
88 if (advertise & ADVERTISED_100baseT_Half)
89 adv |= ADVERTISE_100HALF;
90 if (advertise & ADVERTISED_100baseT_Full)
91 adv |= ADVERTISE_100FULL;
92 if (advertise & ADVERTISED_Pause)
93 adv |= ADVERTISE_PAUSE_CAP;
94 if (advertise & ADVERTISED_Asym_Pause)
95 adv |= ADVERTISE_PAUSE_ASYM;
96 phy_write(phy, MII_ADVERTISE, adv);
97
98 if (phy->features &
99 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
100 adv = phy_read(phy, MII_CTRL1000);
101 if (adv < 0)
102 return adv;
103 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
104 if (advertise & ADVERTISED_1000baseT_Full)
105 adv |= ADVERTISE_1000FULL;
106 if (advertise & ADVERTISED_1000baseT_Half)
107 adv |= ADVERTISE_1000HALF;
108 phy_write(phy, MII_CTRL1000, adv);
109 }
110
111 /* Start/Restart aneg */
112 ctl = phy_read(phy, MII_BMCR);
113 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
114 phy_write(phy, MII_BMCR, ctl);
115
116 return 0;
117}
118
119static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
120{
121 int ctl;
122
123 phy->autoneg = AUTONEG_DISABLE;
124 phy->speed = speed;
125 phy->duplex = fd;
126 phy->pause = phy->asym_pause = 0;
127
128 ctl = phy_read(phy, MII_BMCR);
129 if (ctl < 0)
130 return ctl;
131 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
132
133 /* First clear the PHY */
134 phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
135
136 /* Select speed & duplex */
137 switch (speed) {
138 case SPEED_10:
139 break;
140 case SPEED_100:
141 ctl |= BMCR_SPEED100;
142 break;
143 case SPEED_1000:
144 ctl |= BMCR_SPEED1000;
145 break;
146 default:
147 return -EINVAL;
148 }
149 if (fd == DUPLEX_FULL)
150 ctl |= BMCR_FULLDPLX;
151 phy_write(phy, MII_BMCR, ctl);
152
153 return 0;
154}
155
156static int genmii_poll_link(struct mii_phy *phy)
157{
158 int status;
159
160 /* Clear latched value with dummy read */
161 phy_read(phy, MII_BMSR);
162 status = phy_read(phy, MII_BMSR);
163 if (status < 0 || (status & BMSR_LSTATUS) == 0)
164 return 0;
165 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
166 return 0;
167 return 1;
168}
169
170static int genmii_read_link(struct mii_phy *phy)
171{
172 if (phy->autoneg == AUTONEG_ENABLE) {
173 int glpa = 0;
174 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
175 if (lpa < 0)
176 return lpa;
177
178 if (phy->features &
179 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
180 int adv = phy_read(phy, MII_CTRL1000);
181 glpa = phy_read(phy, MII_STAT1000);
182
183 if (glpa < 0 || adv < 0)
184 return adv;
185
186 glpa &= adv << 2;
187 }
188
189 phy->speed = SPEED_10;
190 phy->duplex = DUPLEX_HALF;
191 phy->pause = phy->asym_pause = 0;
192
193 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
194 phy->speed = SPEED_1000;
195 if (glpa & LPA_1000FULL)
196 phy->duplex = DUPLEX_FULL;
197 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
198 phy->speed = SPEED_100;
199 if (lpa & LPA_100FULL)
200 phy->duplex = DUPLEX_FULL;
201 } else if (lpa & LPA_10FULL)
202 phy->duplex = DUPLEX_FULL;
203
204 if (phy->duplex == DUPLEX_FULL) {
205 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
206 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
207 }
208 } else {
209 int bmcr = phy_read(phy, MII_BMCR);
210 if (bmcr < 0)
211 return bmcr;
212
213 if (bmcr & BMCR_FULLDPLX)
214 phy->duplex = DUPLEX_FULL;
215 else
216 phy->duplex = DUPLEX_HALF;
217 if (bmcr & BMCR_SPEED1000)
218 phy->speed = SPEED_1000;
219 else if (bmcr & BMCR_SPEED100)
220 phy->speed = SPEED_100;
221 else
222 phy->speed = SPEED_10;
223
224 phy->pause = phy->asym_pause = 0;
225 }
226 return 0;
227}
228
229/* Generic implementation for most 10/100/1000 PHYs */
230static struct mii_phy_ops generic_phy_ops = {
231 .setup_aneg = genmii_setup_aneg,
232 .setup_forced = genmii_setup_forced,
233 .poll_link = genmii_poll_link,
234 .read_link = genmii_read_link
235};
236
237static struct mii_phy_def genmii_phy_def = {
238 .phy_id = 0x00000000,
239 .phy_id_mask = 0x00000000,
240 .name = "Generic MII",
241 .ops = &generic_phy_ops
242};
243
244/* CIS8201 */
245#define MII_CIS8201_10BTCSR 0x16
246#define TENBTCSR_ECHO_DISABLE 0x2000
247#define MII_CIS8201_EPCR 0x17
248#define EPCR_MODE_MASK 0x3000
249#define EPCR_GMII_MODE 0x0000
250#define EPCR_RGMII_MODE 0x1000
251#define EPCR_TBI_MODE 0x2000
252#define EPCR_RTBI_MODE 0x3000
253#define MII_CIS8201_ACSR 0x1c
254#define ACSR_PIN_PRIO_SELECT 0x0004
255
256static int cis8201_init(struct mii_phy *phy)
257{
258 int epcr;
259
260 epcr = phy_read(phy, MII_CIS8201_EPCR);
261 if (epcr < 0)
262 return epcr;
263
264 epcr &= ~EPCR_MODE_MASK;
265
266 switch (phy->mode) {
267 case PHY_MODE_TBI:
268 epcr |= EPCR_TBI_MODE;
269 break;
270 case PHY_MODE_RTBI:
271 epcr |= EPCR_RTBI_MODE;
272 break;
273 case PHY_MODE_GMII:
274 epcr |= EPCR_GMII_MODE;
275 break;
276 case PHY_MODE_RGMII:
277 default:
278 epcr |= EPCR_RGMII_MODE;
279 }
280
281 phy_write(phy, MII_CIS8201_EPCR, epcr);
282
283 /* MII regs override strap pins */
284 phy_write(phy, MII_CIS8201_ACSR,
285 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
286
287 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
288 phy_write(phy, MII_CIS8201_10BTCSR,
289 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
290
291 return 0;
292}
293
294static struct mii_phy_ops cis8201_phy_ops = {
295 .init = cis8201_init,
296 .setup_aneg = genmii_setup_aneg,
297 .setup_forced = genmii_setup_forced,
298 .poll_link = genmii_poll_link,
299 .read_link = genmii_read_link
300};
301
302static struct mii_phy_def cis8201_phy_def = {
303 .phy_id = 0x000fc410,
304 .phy_id_mask = 0x000ffff0,
305 .name = "CIS8201 Gigabit Ethernet",
306 .ops = &cis8201_phy_ops
307};
308
309static struct mii_phy_def *mii_phy_table[] = {
310 &cis8201_phy_def,
311 &genmii_phy_def,
312 NULL
313};
314
315int emac_mii_phy_probe(struct mii_phy *phy, int address)
316{
317 struct mii_phy_def *def;
318 int i;
319 u32 id;
320
321 phy->autoneg = AUTONEG_DISABLE;
322 phy->advertising = 0;
323 phy->address = address;
324 phy->speed = SPEED_10;
325 phy->duplex = DUPLEX_HALF;
326 phy->pause = phy->asym_pause = 0;
327
328 /* Take PHY out of isolate mode and reset it. */
329 if (emac_mii_reset_phy(phy))
330 return -ENODEV;
331
332 /* Read ID and find matching entry */
333 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
334 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
335 if ((id & def->phy_id_mask) == def->phy_id)
336 break;
337 /* Should never be NULL (we have a generic entry), but... */
338 if (!def)
339 return -ENODEV;
340
341 phy->def = def;
342
343 /* Determine PHY features if needed */
344 phy->features = def->features;
345 if (!phy->features) {
346 u16 bmsr = phy_read(phy, MII_BMSR);
347 if (bmsr & BMSR_ANEGCAPABLE)
348 phy->features |= SUPPORTED_Autoneg;
349 if (bmsr & BMSR_10HALF)
350 phy->features |= SUPPORTED_10baseT_Half;
351 if (bmsr & BMSR_10FULL)
352 phy->features |= SUPPORTED_10baseT_Full;
353 if (bmsr & BMSR_100HALF)
354 phy->features |= SUPPORTED_100baseT_Half;
355 if (bmsr & BMSR_100FULL)
356 phy->features |= SUPPORTED_100baseT_Full;
357 if (bmsr & BMSR_ESTATEN) {
358 u16 esr = phy_read(phy, MII_ESTATUS);
359 if (esr & ESTATUS_1000_TFULL)
360 phy->features |= SUPPORTED_1000baseT_Full;
361 if (esr & ESTATUS_1000_THALF)
362 phy->features |= SUPPORTED_1000baseT_Half;
363 }
364 phy->features |= SUPPORTED_MII;
365 }
366
367 /* Setup default advertising */
368 phy->advertising = phy->features;
369
370 return 0;
371}
372
373MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 23:33:36 -0500