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diff --git a/drivers/net/ibm_newemac/mal.h b/drivers/net/ibm_newemac/mal.h
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1/*
2 * drivers/net/ibm_newemac/mal.h
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2002 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef __IBM_NEWEMAC_MAL_H
20#define __IBM_NEWEMAC_MAL_H
21
22/*
23 * There are some variations on the MAL, we express them in this driver as
24 * MAL Version 1 and 2 though that doesn't match any IBM terminology.
25 *
26 * We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
27 * NP405H.
28 *
29 * We call MAL 2 the version in 440GP, 440GX, 440SP, 440SPE and Axon
30 *
31 * The driver expects a "version" property in the emac node containing
32 * a number 1 or 2. New device-trees for EMAC capable platforms are thus
33 * required to include that when porting to arch/powerpc.
34 */
35
36/* MALx DCR registers */
37#define MAL_CFG 0x00
38#define MAL_CFG_SR 0x80000000
39#define MAL_CFG_PLBB 0x00004000
40#define MAL_CFG_OPBBL 0x00000080
41#define MAL_CFG_EOPIE 0x00000004
42#define MAL_CFG_LEA 0x00000002
43#define MAL_CFG_SD 0x00000001
44
45/* MAL V1 CFG bits */
46#define MAL1_CFG_PLBP_MASK 0x00c00000
47#define MAL1_CFG_PLBP_10 0x00800000
48#define MAL1_CFG_GA 0x00200000
49#define MAL1_CFG_OA 0x00100000
50#define MAL1_CFG_PLBLE 0x00080000
51#define MAL1_CFG_PLBT_MASK 0x00078000
52#define MAL1_CFG_DEFAULT (MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
53
54/* MAL V2 CFG bits */
55#define MAL2_CFG_RPP_MASK 0x00c00000
56#define MAL2_CFG_RPP_10 0x00800000
57#define MAL2_CFG_RMBS_MASK 0x00300000
58#define MAL2_CFG_WPP_MASK 0x000c0000
59#define MAL2_CFG_WPP_10 0x00080000
60#define MAL2_CFG_WMBS_MASK 0x00030000
61#define MAL2_CFG_PLBLE 0x00008000
62#define MAL2_CFG_DEFAULT (MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
63 MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
64
65#define MAL_ESR 0x01
66#define MAL_ESR_EVB 0x80000000
67#define MAL_ESR_CIDT 0x40000000
68#define MAL_ESR_CID_MASK 0x3e000000
69#define MAL_ESR_CID_SHIFT 25
70#define MAL_ESR_DE 0x00100000
71#define MAL_ESR_OTE 0x00040000
72#define MAL_ESR_OSE 0x00020000
73#define MAL_ESR_PEIN 0x00010000
74#define MAL_ESR_DEI 0x00000010
75#define MAL_ESR_OTEI 0x00000004
76#define MAL_ESR_OSEI 0x00000002
77#define MAL_ESR_PBEI 0x00000001
78
79/* MAL V1 ESR bits */
80#define MAL1_ESR_ONE 0x00080000
81#define MAL1_ESR_ONEI 0x00000008
82
83/* MAL V2 ESR bits */
84#define MAL2_ESR_PTE 0x00800000
85#define MAL2_ESR_PRE 0x00400000
86#define MAL2_ESR_PWE 0x00200000
87#define MAL2_ESR_PTEI 0x00000080
88#define MAL2_ESR_PREI 0x00000040
89#define MAL2_ESR_PWEI 0x00000020
90
91
92#define MAL_IER 0x02
93#define MAL_IER_DE 0x00000010
94#define MAL_IER_OTE 0x00000004
95#define MAL_IER_OE 0x00000002
96#define MAL_IER_PE 0x00000001
97/* MAL V1 IER bits */
98#define MAL1_IER_NWE 0x00000008
99#define MAL1_IER_SOC_EVENTS MAL1_IER_NWE
100#define MAL1_IER_EVENTS (MAL1_IER_SOC_EVENTS | MAL_IER_OTE | \
101 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
102
103/* MAL V2 IER bits */
104#define MAL2_IER_PT 0x00000080
105#define MAL2_IER_PRE 0x00000040
106#define MAL2_IER_PWE 0x00000020
107#define MAL2_IER_SOC_EVENTS (MAL2_IER_PT | MAL2_IER_PRE | MAL2_IER_PWE)
108#define MAL2_IER_EVENTS (MAL2_IER_SOC_EVENTS | MAL_IER_OTE | \
109 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
110
111
112#define MAL_TXCASR 0x04
113#define MAL_TXCARR 0x05
114#define MAL_TXEOBISR 0x06
115#define MAL_TXDEIR 0x07
116#define MAL_RXCASR 0x10
117#define MAL_RXCARR 0x11
118#define MAL_RXEOBISR 0x12
119#define MAL_RXDEIR 0x13
120#define MAL_TXCTPR(n) ((n) + 0x20)
121#define MAL_RXCTPR(n) ((n) + 0x40)
122#define MAL_RCBS(n) ((n) + 0x60)
123
124/* In reality MAL can handle TX buffers up to 4095 bytes long,
125 * but this isn't a good round number :) --ebs
126 */
127#define MAL_MAX_TX_SIZE 4080
128#define MAL_MAX_RX_SIZE 4080
129
130static inline int mal_rx_size(int len)
131{
132 len = (len + 0xf) & ~0xf;
133 return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
134}
135
136static inline int mal_tx_chunks(int len)
137{
138 return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
139}
140
141#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
142
143/* MAL Buffer Descriptor structure */
144struct mal_descriptor {
145 u16 ctrl; /* MAL / Commac status control bits */
146 u16 data_len; /* Max length is 4K-1 (12 bits) */
147 u32 data_ptr; /* pointer to actual data buffer */
148};
149
150/* the following defines are for the MadMAL status and control registers. */
151/* MADMAL transmit and receive status/control bits */
152#define MAL_RX_CTRL_EMPTY 0x8000
153#define MAL_RX_CTRL_WRAP 0x4000
154#define MAL_RX_CTRL_CM 0x2000
155#define MAL_RX_CTRL_LAST 0x1000
156#define MAL_RX_CTRL_FIRST 0x0800
157#define MAL_RX_CTRL_INTR 0x0400
158#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
159#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
160
161#define MAL_TX_CTRL_READY 0x8000
162#define MAL_TX_CTRL_WRAP 0x4000
163#define MAL_TX_CTRL_CM 0x2000
164#define MAL_TX_CTRL_LAST 0x1000
165#define MAL_TX_CTRL_INTR 0x0400
166
167struct mal_commac_ops {
168 void (*poll_tx) (void *dev);
169 int (*poll_rx) (void *dev, int budget);
170 int (*peek_rx) (void *dev);
171 void (*rxde) (void *dev);
172};
173
174struct mal_commac {
175 struct mal_commac_ops *ops;
176 void *dev;
177 struct list_head poll_list;
178 long flags;
179#define MAL_COMMAC_RX_STOPPED 0
180#define MAL_COMMAC_POLL_DISABLED 1
181 u32 tx_chan_mask;
182 u32 rx_chan_mask;
183 struct list_head list;
184};
185
186struct mal_instance {
187 int version;
188 int dcr_base;
189 dcr_host_t dcr_host;
190
191 int num_tx_chans; /* Number of TX channels */
192 int num_rx_chans; /* Number of RX channels */
193 int txeob_irq; /* TX End Of Buffer IRQ */
194 int rxeob_irq; /* RX End Of Buffer IRQ */
195 int txde_irq; /* TX Descriptor Error IRQ */
196 int rxde_irq; /* RX Descriptor Error IRQ */
197 int serr_irq; /* MAL System Error IRQ */
198
199 struct list_head poll_list;
200 struct net_device poll_dev;
201
202 struct list_head list;
203 u32 tx_chan_mask;
204 u32 rx_chan_mask;
205
206 dma_addr_t bd_dma;
207 struct mal_descriptor *bd_virt;
208
209 struct of_device *ofdev;
210 int index;
211 spinlock_t lock;
212};
213
214static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
215{
216 return dcr_read(mal->dcr_host, mal->dcr_base + reg);
217}
218
219static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
220{
221 dcr_write(mal->dcr_host, mal->dcr_base + reg, val);
222}
223
224/* Register MAL devices */
225int mal_init(void);
226void mal_exit(void);
227
228int mal_register_commac(struct mal_instance *mal,
229 struct mal_commac *commac);
230void mal_unregister_commac(struct mal_instance *mal,
231 struct mal_commac *commac);
232int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
233
234/* Returns BD ring offset for a particular channel
235 (in 'struct mal_descriptor' elements)
236*/
237int mal_tx_bd_offset(struct mal_instance *mal, int channel);
238int mal_rx_bd_offset(struct mal_instance *mal, int channel);
239
240void mal_enable_tx_channel(struct mal_instance *mal, int channel);
241void mal_disable_tx_channel(struct mal_instance *mal, int channel);
242void mal_enable_rx_channel(struct mal_instance *mal, int channel);
243void mal_disable_rx_channel(struct mal_instance *mal, int channel);
244
245void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
246void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
247
248/* Add/remove EMAC to/from MAL polling list */
249void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
250void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
251
252/* Ethtool MAL registers */
253struct mal_regs {
254 u32 tx_count;
255 u32 rx_count;
256
257 u32 cfg;
258 u32 esr;
259 u32 ier;
260 u32 tx_casr;
261 u32 tx_carr;
262 u32 tx_eobisr;
263 u32 tx_deir;
264 u32 rx_casr;
265 u32 rx_carr;
266 u32 rx_eobisr;
267 u32 rx_deir;
268 u32 tx_ctpr[32];
269 u32 rx_ctpr[32];
270 u32 rcbs[32];
271};
272
273int mal_get_regs_len(struct mal_instance *mal);
274void *mal_dump_regs(struct mal_instance *mal, void *buf);
275
276#endif /* __IBM_NEWEMAC_MAL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 02:14:41 -0500