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-rw-r--r--drivers/net/hp100.h44
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/net/hp100.h b/drivers/net/hp100.h
index 236d945987af..e6ca128a5564 100644
--- a/drivers/net/hp100.h
+++ b/drivers/net/hp100.h
@@ -8,9 +8,9 @@
8 * 8 *
9 * This driver is based on the 'hpfepkt' crynwr packet driver. 9 * This driver is based on the 'hpfepkt' crynwr packet driver.
10 * 10 *
11 * This source/code is public free; you can distribute it and/or modify 11 * This source/code is public free; you can distribute it and/or modify
12 * it under terms of the GNU General Public License (published by the 12 * it under terms of the GNU General Public License (published by the
13 * Free Software Foundation) either version two of this License, or any 13 * Free Software Foundation) either version two of this License, or any
14 * later version. 14 * later version.
15 */ 15 */
16 16
@@ -18,7 +18,7 @@
18 * Hardware Constants 18 * Hardware Constants
19 ****************************************************************************/ 19 ****************************************************************************/
20 20
21/* 21/*
22 * Page Identifiers 22 * Page Identifiers
23 * (Swap Paging Register, PAGING, bits 3:0, Offset 0x02) 23 * (Swap Paging Register, PAGING, bits 3:0, Offset 0x02)
24 */ 24 */
@@ -143,15 +143,15 @@
143/* ------------------------------------------------------------------------ */ 143/* ------------------------------------------------------------------------ */
144 144
145 145
146/* 146/*
147 * Hardware ID Register I (Always available, HW_ID, Offset 0x00) 147 * Hardware ID Register I (Always available, HW_ID, Offset 0x00)
148 */ 148 */
149#define HP100_HW_ID_CASCADE 0x4850 /* Identifies Cascade Chip */ 149#define HP100_HW_ID_CASCADE 0x4850 /* Identifies Cascade Chip */
150 150
151/* 151/*
152 * Hardware ID Register 2 & Paging Register 152 * Hardware ID Register 2 & Paging Register
153 * (Always available, PAGING, Offset 0x02) 153 * (Always available, PAGING, Offset 0x02)
154 * Bits 15:4 are for the Chip ID 154 * Bits 15:4 are for the Chip ID
155 */ 155 */
156#define HP100_CHIPID_MASK 0xFFF0 156#define HP100_CHIPID_MASK 0xFFF0
157#define HP100_CHIPID_SHASTA 0x5350 /* Not 802.12 compliant */ 157#define HP100_CHIPID_SHASTA 0x5350 /* Not 802.12 compliant */
@@ -162,7 +162,7 @@
162 /* LRF supported */ 162 /* LRF supported */
163 163
164/* 164/*
165 * Option Registers I and II 165 * Option Registers I and II
166 * (Always available, OPTION_LSW, Offset 0x04-0x05) 166 * (Always available, OPTION_LSW, Offset 0x04-0x05)
167 */ 167 */
168#define HP100_DEBUG_EN 0x8000 /* 0:Dis., 1:Enable Debug Dump Ptr. */ 168#define HP100_DEBUG_EN 0x8000 /* 0:Dis., 1:Enable Debug Dump Ptr. */
@@ -187,7 +187,7 @@
187 /* NIC reset on 0 to 1 transition */ 187 /* NIC reset on 0 to 1 transition */
188 188
189/* 189/*
190 * Option Register III 190 * Option Register III
191 * (Always available, OPTION_MSW, Offset 0x06) 191 * (Always available, OPTION_MSW, Offset 0x06)
192 */ 192 */
193#define HP100_PRIORITY_TX 0x0080 /* 1:Do all Tx pkts as priority */ 193#define HP100_PRIORITY_TX 0x0080 /* 1:Do all Tx pkts as priority */
@@ -253,7 +253,7 @@
253#define HP100_BM_PCI_8CLK 0x40 /* ... cycles 8 clocks apart */ 253#define HP100_BM_PCI_8CLK 0x40 /* ... cycles 8 clocks apart */
254 254
255 255
256/* 256/*
257 * Mode Control Register I 257 * Mode Control Register I
258 * (Page HW_MAP, MODECTRL1, Offset0x10) 258 * (Page HW_MAP, MODECTRL1, Offset0x10)
259 */ 259 */
@@ -281,7 +281,7 @@
281#define HP100_EN_BUS_FAIL 0x80 /* Enables bus-fail portion of misc */ 281#define HP100_EN_BUS_FAIL 0x80 /* Enables bus-fail portion of misc */
282 /* interrupt */ 282 /* interrupt */
283 283
284/* 284/*
285 * PCI Configuration and Control Register I 285 * PCI Configuration and Control Register I
286 * (Page HW_MAP, PCICTRL1, Offset 0x12) 286 * (Page HW_MAP, PCICTRL1, Offset 0x12)
287 */ 287 */
@@ -378,7 +378,7 @@
378 378
379/* 379/*
380 * 100MB LAN Control and Configuration Register 380 * 100MB LAN Control and Configuration Register
381 * (Page MAC_CTRL, VG_LAN_CFG_1, Offset 0x0a) 381 * (Page MAC_CTRL, VG_LAN_CFG_1, Offset 0x0a)
382 */ 382 */
383#define HP100_VG_SEL 0x80 /* 0:No, 1:Yes use 100 Mbit MAC */ 383#define HP100_VG_SEL 0x80 /* 0:No, 1:Yes use 100 Mbit MAC */
384#define HP100_LINK_UP_ST 0x40 /* 0:No, 1:Yes endnode logged in */ 384#define HP100_LINK_UP_ST 0x40 /* 0:No, 1:Yes endnode logged in */
@@ -422,7 +422,7 @@
422#define HP100_MAC1MODE7 HP100_MAC1MODE6 | HP100_ACC_ERRORED 422#define HP100_MAC1MODE7 HP100_MAC1MODE6 | HP100_ACC_ERRORED
423 423
424/* 424/*
425 * MAC Configuration Register II 425 * MAC Configuration Register II
426 * (Page MAC_CTRL, MAC_CFG_2, Offset 0x0d) 426 * (Page MAC_CTRL, MAC_CFG_2, Offset 0x0d)
427 */ 427 */
428#define HP100_TR_MODE 0x80 /* 0:No, 1:Yes support Token Ring formats */ 428#define HP100_TR_MODE 0x80 /* 0:No, 1:Yes support Token Ring formats */
@@ -447,8 +447,8 @@
447#define HP100_MAC2MODE7 KEEP_CRC 447#define HP100_MAC2MODE7 KEEP_CRC
448 448
449/* 449/*
450 * MAC Configuration Register III 450 * MAC Configuration Register III
451 * (Page MAC_CTRL, MAC_CFG_3, Offset 0x0e) 451 * (Page MAC_CTRL, MAC_CFG_3, Offset 0x0e)
452 */ 452 */
453#define HP100_PACKET_PACE 0x03 /* Packet Pacing: 453#define HP100_PACKET_PACE 0x03 /* Packet Pacing:
454 * 00: No packet pacing 454 * 00: No packet pacing
@@ -461,7 +461,7 @@
461#define HP100_AUTO_MODE 0x10 /* 1: AutoSelect between 10/100 */ 461#define HP100_AUTO_MODE 0x10 /* 1: AutoSelect between 10/100 */
462 462
463/* 463/*
464 * MAC Configuration Register IV 464 * MAC Configuration Register IV
465 * (Page MAC_CTRL, MAC_CFG_4, Offset 0x0f) 465 * (Page MAC_CTRL, MAC_CFG_4, Offset 0x0f)
466 */ 466 */
467#define HP100_MAC_SEL_ST 0x01 /* (R): Status of external VGSEL 467#define HP100_MAC_SEL_ST 0x01 /* (R): Status of external VGSEL
@@ -469,18 +469,18 @@
469#define HP100_LINK_FAIL_ST 0x02 /* (R): Status of Link Fail portion 469#define HP100_LINK_FAIL_ST 0x02 /* (R): Status of Link Fail portion
470 * of the Misc. Interrupt */ 470 * of the Misc. Interrupt */
471 471
472/* 472/*
473 * 100 MB LAN Training Request/Allowed Registers 473 * 100 MB LAN Training Request/Allowed Registers
474 * (Page MAC_CTRL, TRAIN_REQUEST and TRAIN_ALLOW, Offset 0x14-0x16)(ETR parts only) 474 * (Page MAC_CTRL, TRAIN_REQUEST and TRAIN_ALLOW, Offset 0x14-0x16)(ETR parts only)
475 */ 475 */
476#define HP100_MACRQ_REPEATER 0x0001 /* 1: MAC tells HUB it wants to be 476#define HP100_MACRQ_REPEATER 0x0001 /* 1: MAC tells HUB it wants to be
477 * a cascaded repeater 477 * a cascaded repeater
478 * 0: ... wants to be a DTE */ 478 * 0: ... wants to be a DTE */
479#define HP100_MACRQ_PROMSC 0x0006 /* 2 bits: Promiscious mode 479#define HP100_MACRQ_PROMSC 0x0006 /* 2 bits: Promiscious mode
480 * 00: Rcv only unicast packets 480 * 00: Rcv only unicast packets
481 * specifically addr to this 481 * specifically addr to this
482 * endnode 482 * endnode
483 * 10: Rcv all pckts fwded by 483 * 10: Rcv all pckts fwded by
484 * the local repeater */ 484 * the local repeater */
485#define HP100_MACRQ_FRAMEFMT_EITHER 0x0018 /* 11: either format allowed */ 485#define HP100_MACRQ_FRAMEFMT_EITHER 0x0018 /* 11: either format allowed */
486#define HP100_MACRQ_FRAMEFMT_802_3 0x0000 /* 00: 802.3 is requested */ 486#define HP100_MACRQ_FRAMEFMT_802_3 0x0000 /* 00: 802.3 is requested */
@@ -492,7 +492,7 @@
492 * 00: Rcv only unicast packets 492 * 00: Rcv only unicast packets
493 * specifically addr to this 493 * specifically addr to this
494 * endnode 494 * endnode
495 * 10: Rcv all pckts fwded by 495 * 10: Rcv all pckts fwded by
496 * the local repeater */ 496 * the local repeater */
497#define HP100_MALLOW_FRAMEFMT 0x00e0 /* 2 bits: Frame Format 497#define HP100_MALLOW_FRAMEFMT 0x00e0 /* 2 bits: Frame Format
498 * 00: 802.3 format will be used 498 * 00: 802.3 format will be used
@@ -521,7 +521,7 @@
521#define HP100_LAN_COAX 9 /* lan_type value for Coax */ 521#define HP100_LAN_COAX 9 /* lan_type value for Coax */
522#define HP100_LAN_ERR (-1) /* lan_type value for link down */ 522#define HP100_LAN_ERR (-1) /* lan_type value for link down */
523 523
524/* 524/*
525 * Bus Master Data Structures ---------------------------------------------- 525 * Bus Master Data Structures ----------------------------------------------
526 */ 526 */
527 527
@@ -554,7 +554,7 @@ typedef struct hp100_ring {
554#define HP100_PKT_LEN_MASK 0x1FFF /* AND with RxLength to get length */ 554#define HP100_PKT_LEN_MASK 0x1FFF /* AND with RxLength to get length */
555 555
556 556
557/* Receive Packet Status. Note, the error bits are only valid if ACC_ERRORED 557/* Receive Packet Status. Note, the error bits are only valid if ACC_ERRORED
558 bit in the MAC Configuration Register 1 is set. */ 558 bit in the MAC Configuration Register 1 is set. */
559#define HP100_RX_PRI 0x8000 /* 0:No, 1:Yes packet is priority */ 559#define HP100_RX_PRI 0x8000 /* 0:No, 1:Yes packet is priority */
560#define HP100_SDF_ERR 0x4000 /* 0:No, 1:Yes start of frame error */ 560#define HP100_SDF_ERR 0x4000 /* 0:No, 1:Yes start of frame error */