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-rw-r--r--drivers/net/gt96100eth.h346
1 files changed, 0 insertions, 346 deletions
diff --git a/drivers/net/gt96100eth.h b/drivers/net/gt96100eth.h
deleted file mode 100644
index 509d8166bb59..000000000000
--- a/drivers/net/gt96100eth.h
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@@ -1,346 +0,0 @@
1/*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * Ethernet driver definitions for the MIPS GT96100 Advanced
24 * Communication Controller.
25 *
26 */
27#ifndef _GT96100ETH_H
28#define _GT96100ETH_H
29
30#include <asm/galileo-boards/gt96100.h>
31
32#define dbg(lvl, format, arg...) \
33 if (lvl <= GT96100_DEBUG) \
34 printk(KERN_DEBUG "%s: " format, dev->name , ## arg)
35#define err(format, arg...) \
36 printk(KERN_ERR "%s: " format, dev->name , ## arg)
37#define info(format, arg...) \
38 printk(KERN_INFO "%s: " format, dev->name , ## arg)
39#define warn(format, arg...) \
40 printk(KERN_WARNING "%s: " format, dev->name , ## arg)
41
42/* Keep the ring sizes a power of two for efficiency. */
43#define TX_RING_SIZE 16
44#define RX_RING_SIZE 32
45#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
46
47#define RX_HASH_TABLE_SIZE 16384
48#define HASH_HOP_NUMBER 12
49
50#define NUM_INTERFACES 2
51
52#define GT96100ETH_TX_TIMEOUT HZ/4
53
54#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG)
55#define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE)
56
57#ifdef CONFIG_MIPS_EV96100
58#define GT96100_ETHER0_IRQ 3
59#define GT96100_ETHER1_IRQ 4
60#else
61#define GT96100_ETHER0_IRQ -1
62#define GT96100_ETHER1_IRQ -1
63#endif
64
65#define REV_GT96100 1
66#define REV_GT96100A_1 2
67#define REV_GT96100A 3
68
69#define GT96100ETH_READ(gp, offset) \
70 GT96100_READ((gp->port_offset + offset))
71
72#define GT96100ETH_WRITE(gp, offset, data) \
73 GT96100_WRITE((gp->port_offset + offset), data)
74
75#define GT96100ETH_SETBIT(gp, offset, bits) {\
76 u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \
77 GT96100ETH_WRITE(gp, offset, val); }
78
79#define GT96100ETH_CLRBIT(gp, offset, bits) {\
80 u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \
81 GT96100ETH_WRITE(gp, offset, val); }
82
83
84/* Bit definitions of the SMI Reg */
85enum {
86 smirDataMask = 0xffff,
87 smirPhyAdMask = 0x1f<<16,
88 smirPhyAdBit = 16,
89 smirRegAdMask = 0x1f<<21,
90 smirRegAdBit = 21,
91 smirOpCode = 1<<26,
92 smirReadValid = 1<<27,
93 smirBusy = 1<<28
94};
95
96/* Bit definitions of the Port Config Reg */
97enum pcr_bits {
98 pcrPM = 1,
99 pcrRBM = 2,
100 pcrPBF = 4,
101 pcrEN = 1<<7,
102 pcrLPBKMask = 0x3<<8,
103 pcrLPBKBit = 8,
104 pcrFC = 1<<10,
105 pcrHS = 1<<12,
106 pcrHM = 1<<13,
107 pcrHDM = 1<<14,
108 pcrHD = 1<<15,
109 pcrISLMask = 0x7<<28,
110 pcrISLBit = 28,
111 pcrACCS = 1<<31
112};
113
114/* Bit definitions of the Port Config Extend Reg */
115enum pcxr_bits {
116 pcxrIGMP = 1,
117 pcxrSPAN = 2,
118 pcxrPAR = 4,
119 pcxrPRIOtxMask = 0x7<<3,
120 pcxrPRIOtxBit = 3,
121 pcxrPRIOrxMask = 0x3<<6,
122 pcxrPRIOrxBit = 6,
123 pcxrPRIOrxOverride = 1<<8,
124 pcxrDPLXen = 1<<9,
125 pcxrFCTLen = 1<<10,
126 pcxrFLP = 1<<11,
127 pcxrFCTL = 1<<12,
128 pcxrMFLMask = 0x3<<14,
129 pcxrMFLBit = 14,
130 pcxrMIBclrMode = 1<<16,
131 pcxrSpeed = 1<<18,
132 pcxrSpeeden = 1<<19,
133 pcxrRMIIen = 1<<20,
134 pcxrDSCPen = 1<<21
135};
136
137/* Bit definitions of the Port Command Reg */
138enum pcmr_bits {
139 pcmrFJ = 1<<15
140};
141
142
143/* Bit definitions of the Port Status Reg */
144enum psr_bits {
145 psrSpeed = 1,
146 psrDuplex = 2,
147 psrFctl = 4,
148 psrLink = 8,
149 psrPause = 1<<4,
150 psrTxLow = 1<<5,
151 psrTxHigh = 1<<6,
152 psrTxInProg = 1<<7
153};
154
155/* Bit definitions of the SDMA Config Reg */
156enum sdcr_bits {
157 sdcrRCMask = 0xf<<2,
158 sdcrRCBit = 2,
159 sdcrBLMR = 1<<6,
160 sdcrBLMT = 1<<7,
161 sdcrPOVR = 1<<8,
162 sdcrRIFB = 1<<9,
163 sdcrBSZMask = 0x3<<12,
164 sdcrBSZBit = 12
165};
166
167/* Bit definitions of the SDMA Command Reg */
168enum sdcmr_bits {
169 sdcmrERD = 1<<7,
170 sdcmrAR = 1<<15,
171 sdcmrSTDH = 1<<16,
172 sdcmrSTDL = 1<<17,
173 sdcmrTXDH = 1<<23,
174 sdcmrTXDL = 1<<24,
175 sdcmrAT = 1<<31
176};
177
178/* Bit definitions of the Interrupt Cause Reg */
179enum icr_bits {
180 icrRxBuffer = 1,
181 icrTxBufferHigh = 1<<2,
182 icrTxBufferLow = 1<<3,
183 icrTxEndHigh = 1<<6,
184 icrTxEndLow = 1<<7,
185 icrRxError = 1<<8,
186 icrTxErrorHigh = 1<<10,
187 icrTxErrorLow = 1<<11,
188 icrRxOVR = 1<<12,
189 icrTxUdr = 1<<13,
190 icrRxBufferQ0 = 1<<16,
191 icrRxBufferQ1 = 1<<17,
192 icrRxBufferQ2 = 1<<18,
193 icrRxBufferQ3 = 1<<19,
194 icrRxErrorQ0 = 1<<20,
195 icrRxErrorQ1 = 1<<21,
196 icrRxErrorQ2 = 1<<22,
197 icrRxErrorQ3 = 1<<23,
198 icrMIIPhySTC = 1<<28,
199 icrSMIdone = 1<<29,
200 icrEtherIntSum = 1<<31
201};
202
203
204/* The Rx and Tx descriptor lists. */
205typedef struct {
206#ifdef DESC_BE
207 u16 byte_cnt;
208 u16 reserved;
209#else
210 u16 reserved;
211 u16 byte_cnt;
212#endif
213 u32 cmdstat;
214 u32 next;
215 u32 buff_ptr;
216} __attribute__ ((packed)) gt96100_td_t;
217
218typedef struct {
219#ifdef DESC_BE
220 u16 buff_sz;
221 u16 byte_cnt;
222#else
223 u16 byte_cnt;
224 u16 buff_sz;
225#endif
226 u32 cmdstat;
227 u32 next;
228 u32 buff_ptr;
229} __attribute__ ((packed)) gt96100_rd_t;
230
231
232/* Values for the Tx command-status descriptor entry. */
233enum td_cmdstat {
234 txOwn = 1<<31,
235 txAutoMode = 1<<30,
236 txEI = 1<<23,
237 txGenCRC = 1<<22,
238 txPad = 1<<18,
239 txFirst = 1<<17,
240 txLast = 1<<16,
241 txErrorSummary = 1<<15,
242 txReTxCntMask = 0x0f<<10,
243 txReTxCntBit = 10,
244 txCollision = 1<<9,
245 txReTxLimit = 1<<8,
246 txUnderrun = 1<<6,
247 txLateCollision = 1<<5
248};
249
250
251/* Values for the Rx command-status descriptor entry. */
252enum rd_cmdstat {
253 rxOwn = 1<<31,
254 rxAutoMode = 1<<30,
255 rxEI = 1<<23,
256 rxFirst = 1<<17,
257 rxLast = 1<<16,
258 rxErrorSummary = 1<<15,
259 rxIGMP = 1<<14,
260 rxHashExpired = 1<<13,
261 rxMissedFrame = 1<<12,
262 rxFrameType = 1<<11,
263 rxShortFrame = 1<<8,
264 rxMaxFrameLen = 1<<7,
265 rxOverrun = 1<<6,
266 rxCollision = 1<<4,
267 rxCRCError = 1
268};
269
270/* Bit fields of a Hash Table Entry */
271enum hash_table_entry {
272 hteValid = 1,
273 hteSkip = 2,
274 hteRD = 4
275};
276
277// The MIB counters
278typedef struct {
279 u32 byteReceived;
280 u32 byteSent;
281 u32 framesReceived;
282 u32 framesSent;
283 u32 totalByteReceived;
284 u32 totalFramesReceived;
285 u32 broadcastFramesReceived;
286 u32 multicastFramesReceived;
287 u32 cRCError;
288 u32 oversizeFrames;
289 u32 fragments;
290 u32 jabber;
291 u32 collision;
292 u32 lateCollision;
293 u32 frames64;
294 u32 frames65_127;
295 u32 frames128_255;
296 u32 frames256_511;
297 u32 frames512_1023;
298 u32 frames1024_MaxSize;
299 u32 macRxError;
300 u32 droppedFrames;
301 u32 outMulticastFrames;
302 u32 outBroadcastFrames;
303 u32 undersizeFrames;
304} mib_counters_t;
305
306
307struct gt96100_private {
308 gt96100_rd_t* rx_ring;
309 gt96100_td_t* tx_ring;
310 // The Rx and Tx rings must be 16-byte aligned
311 dma_addr_t rx_ring_dma;
312 dma_addr_t tx_ring_dma;
313 char* hash_table;
314 // The Hash Table must be 8-byte aligned
315 dma_addr_t hash_table_dma;
316 int hash_mode;
317
318 // The Rx buffers must be 8-byte aligned
319 char* rx_buff;
320 dma_addr_t rx_buff_dma;
321 // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
322 // of payload must be 8-byte aligned
323 struct sk_buff* tx_skbuff[TX_RING_SIZE];
324 int rx_next_out; /* The next free ring entry to receive */
325 int tx_next_in; /* The next free ring entry to send */
326 int tx_next_out; /* The last ring entry the ISR processed */
327 int tx_count; /* current # of pkts waiting to be sent in Tx ring */
328 int intr_work_done; /* number of Rx and Tx pkts processed in the isr */
329 int tx_full; /* Tx ring is full */
330
331 mib_counters_t mib;
332 struct net_device_stats stats;
333
334 int port_num; // 0 or 1
335 int chip_rev;
336 u32 port_offset;
337
338 int phy_addr; // PHY address
339 u32 last_psr; // last value of the port status register
340
341 int options; /* User-settable misc. driver options. */
342 struct timer_list timer;
343 spinlock_t lock; /* Serialise access to device */
344};
345
346#endif
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