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-rw-r--r--drivers/net/gianfar.h412
1 files changed, 351 insertions, 61 deletions
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index 2cd94338b5d3..cbb451011cb5 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -7,8 +7,9 @@
7 * 7 *
8 * Author: Andy Fleming 8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala 9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
10 * 11 *
11 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. 12 * Copyright 2002-2009 Freescale Semiconductor, Inc.
12 * 13 *
13 * This program is free software; you can redistribute it and/or modify it 14 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the 15 * under the terms of the GNU General Public License as published by the
@@ -74,6 +75,13 @@
74extern const char gfar_driver_name[]; 75extern const char gfar_driver_name[];
75extern const char gfar_driver_version[]; 76extern const char gfar_driver_version[];
76 77
78/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
79#define MAX_TX_QS 0x8
80#define MAX_RX_QS 0x8
81
82/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
83#define MAXGROUPS 0x2
84
77/* These need to be powers of 2 for this driver */ 85/* These need to be powers of 2 for this driver */
78#define DEFAULT_TX_RING_SIZE 256 86#define DEFAULT_TX_RING_SIZE 256
79#define DEFAULT_RX_RING_SIZE 256 87#define DEFAULT_RX_RING_SIZE 256
@@ -171,12 +179,63 @@ extern const char gfar_driver_version[];
171 179
172#define MINFLR_INIT_SETTINGS 0x00000040 180#define MINFLR_INIT_SETTINGS 0x00000040
173 181
182/* Tqueue control */
183#define TQUEUE_EN0 0x00008000
184#define TQUEUE_EN1 0x00004000
185#define TQUEUE_EN2 0x00002000
186#define TQUEUE_EN3 0x00001000
187#define TQUEUE_EN4 0x00000800
188#define TQUEUE_EN5 0x00000400
189#define TQUEUE_EN6 0x00000200
190#define TQUEUE_EN7 0x00000100
191#define TQUEUE_EN_ALL 0x0000FF00
192
193#define TR03WT_WT0_MASK 0xFF000000
194#define TR03WT_WT1_MASK 0x00FF0000
195#define TR03WT_WT2_MASK 0x0000FF00
196#define TR03WT_WT3_MASK 0x000000FF
197
198#define TR47WT_WT4_MASK 0xFF000000
199#define TR47WT_WT5_MASK 0x00FF0000
200#define TR47WT_WT6_MASK 0x0000FF00
201#define TR47WT_WT7_MASK 0x000000FF
202
203/* Rqueue control */
204#define RQUEUE_EX0 0x00800000
205#define RQUEUE_EX1 0x00400000
206#define RQUEUE_EX2 0x00200000
207#define RQUEUE_EX3 0x00100000
208#define RQUEUE_EX4 0x00080000
209#define RQUEUE_EX5 0x00040000
210#define RQUEUE_EX6 0x00020000
211#define RQUEUE_EX7 0x00010000
212#define RQUEUE_EX_ALL 0x00FF0000
213
214#define RQUEUE_EN0 0x00000080
215#define RQUEUE_EN1 0x00000040
216#define RQUEUE_EN2 0x00000020
217#define RQUEUE_EN3 0x00000010
218#define RQUEUE_EN4 0x00000008
219#define RQUEUE_EN5 0x00000004
220#define RQUEUE_EN6 0x00000002
221#define RQUEUE_EN7 0x00000001
222#define RQUEUE_EN_ALL 0x000000FF
223
174/* Init to do tx snooping for buffers and descriptors */ 224/* Init to do tx snooping for buffers and descriptors */
175#define DMACTRL_INIT_SETTINGS 0x000000c3 225#define DMACTRL_INIT_SETTINGS 0x000000c3
176#define DMACTRL_GRS 0x00000010 226#define DMACTRL_GRS 0x00000010
177#define DMACTRL_GTS 0x00000008 227#define DMACTRL_GTS 0x00000008
178 228
179#define TSTAT_CLEAR_THALT 0x80000000 229#define TSTAT_CLEAR_THALT_ALL 0xFF000000
230#define TSTAT_CLEAR_THALT 0x80000000
231#define TSTAT_CLEAR_THALT0 0x80000000
232#define TSTAT_CLEAR_THALT1 0x40000000
233#define TSTAT_CLEAR_THALT2 0x20000000
234#define TSTAT_CLEAR_THALT3 0x10000000
235#define TSTAT_CLEAR_THALT4 0x08000000
236#define TSTAT_CLEAR_THALT5 0x04000000
237#define TSTAT_CLEAR_THALT6 0x02000000
238#define TSTAT_CLEAR_THALT7 0x01000000
180 239
181/* Interrupt coalescing macros */ 240/* Interrupt coalescing macros */
182#define IC_ICEN 0x80000000 241#define IC_ICEN 0x80000000
@@ -227,6 +286,13 @@ extern const char gfar_driver_version[];
227#define TCTRL_IPCSEN 0x00004000 286#define TCTRL_IPCSEN 0x00004000
228#define TCTRL_TUCSEN 0x00002000 287#define TCTRL_TUCSEN 0x00002000
229#define TCTRL_VLINS 0x00001000 288#define TCTRL_VLINS 0x00001000
289#define TCTRL_THDF 0x00000800
290#define TCTRL_RFCPAUSE 0x00000010
291#define TCTRL_TFCPAUSE 0x00000008
292#define TCTRL_TXSCHED_MASK 0x00000006
293#define TCTRL_TXSCHED_INIT 0x00000000
294#define TCTRL_TXSCHED_PRIO 0x00000002
295#define TCTRL_TXSCHED_WRRS 0x00000004
230#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 296#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
231 297
232#define IEVENT_INIT_CLEAR 0xffffffff 298#define IEVENT_INIT_CLEAR 0xffffffff
@@ -315,6 +381,84 @@ extern const char gfar_driver_version[];
315#define BD_LFLAG(flags) ((flags) << 16) 381#define BD_LFLAG(flags) ((flags) << 16)
316#define BD_LENGTH_MASK 0x0000ffff 382#define BD_LENGTH_MASK 0x0000ffff
317 383
384#define CLASS_CODE_UNRECOG 0x00
385#define CLASS_CODE_DUMMY1 0x01
386#define CLASS_CODE_ETHERTYPE1 0x02
387#define CLASS_CODE_ETHERTYPE2 0x03
388#define CLASS_CODE_USER_PROG1 0x04
389#define CLASS_CODE_USER_PROG2 0x05
390#define CLASS_CODE_USER_PROG3 0x06
391#define CLASS_CODE_USER_PROG4 0x07
392#define CLASS_CODE_TCP_IPV4 0x08
393#define CLASS_CODE_UDP_IPV4 0x09
394#define CLASS_CODE_AH_ESP_IPV4 0x0a
395#define CLASS_CODE_SCTP_IPV4 0x0b
396#define CLASS_CODE_TCP_IPV6 0x0c
397#define CLASS_CODE_UDP_IPV6 0x0d
398#define CLASS_CODE_AH_ESP_IPV6 0x0e
399#define CLASS_CODE_SCTP_IPV6 0x0f
400
401#define FPR_FILER_MASK 0xFFFFFFFF
402#define MAX_FILER_IDX 0xFF
403
404/* RQFCR register bits */
405#define RQFCR_GPI 0x80000000
406#define RQFCR_HASHTBL_Q 0x00000000
407#define RQFCR_HASHTBL_0 0x00020000
408#define RQFCR_HASHTBL_1 0x00040000
409#define RQFCR_HASHTBL_2 0x00060000
410#define RQFCR_HASHTBL_3 0x00080000
411#define RQFCR_HASH 0x00010000
412#define RQFCR_CLE 0x00000200
413#define RQFCR_RJE 0x00000100
414#define RQFCR_AND 0x00000080
415#define RQFCR_CMP_EXACT 0x00000000
416#define RQFCR_CMP_MATCH 0x00000020
417#define RQFCR_CMP_NOEXACT 0x00000040
418#define RQFCR_CMP_NOMATCH 0x00000060
419
420/* RQFCR PID values */
421#define RQFCR_PID_MASK 0x00000000
422#define RQFCR_PID_PARSE 0x00000001
423#define RQFCR_PID_ARB 0x00000002
424#define RQFCR_PID_DAH 0x00000003
425#define RQFCR_PID_DAL 0x00000004
426#define RQFCR_PID_SAH 0x00000005
427#define RQFCR_PID_SAL 0x00000006
428#define RQFCR_PID_ETY 0x00000007
429#define RQFCR_PID_VID 0x00000008
430#define RQFCR_PID_PRI 0x00000009
431#define RQFCR_PID_TOS 0x0000000A
432#define RQFCR_PID_L4P 0x0000000B
433#define RQFCR_PID_DIA 0x0000000C
434#define RQFCR_PID_SIA 0x0000000D
435#define RQFCR_PID_DPT 0x0000000E
436#define RQFCR_PID_SPT 0x0000000F
437
438/* RQFPR when PID is 0x0001 */
439#define RQFPR_HDR_GE_512 0x00200000
440#define RQFPR_LERR 0x00100000
441#define RQFPR_RAR 0x00080000
442#define RQFPR_RARQ 0x00040000
443#define RQFPR_AR 0x00020000
444#define RQFPR_ARQ 0x00010000
445#define RQFPR_EBC 0x00008000
446#define RQFPR_VLN 0x00004000
447#define RQFPR_CFI 0x00002000
448#define RQFPR_JUM 0x00001000
449#define RQFPR_IPF 0x00000800
450#define RQFPR_FIF 0x00000400
451#define RQFPR_IPV4 0x00000200
452#define RQFPR_IPV6 0x00000100
453#define RQFPR_ICC 0x00000080
454#define RQFPR_ICV 0x00000040
455#define RQFPR_TCP 0x00000020
456#define RQFPR_UDP 0x00000010
457#define RQFPR_TUC 0x00000008
458#define RQFPR_TUV 0x00000004
459#define RQFPR_PER 0x00000002
460#define RQFPR_EER 0x00000001
461
318/* TxBD status field bits */ 462/* TxBD status field bits */
319#define TXBD_READY 0x8000 463#define TXBD_READY 0x8000
320#define TXBD_PADCRC 0x4000 464#define TXBD_PADCRC 0x4000
@@ -503,25 +647,32 @@ struct gfar_stats {
503 647
504struct gfar { 648struct gfar {
505 u32 tsec_id; /* 0x.000 - Controller ID register */ 649 u32 tsec_id; /* 0x.000 - Controller ID register */
506 u8 res1[12]; 650 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
651 u8 res1[8];
507 u32 ievent; /* 0x.010 - Interrupt Event Register */ 652 u32 ievent; /* 0x.010 - Interrupt Event Register */
508 u32 imask; /* 0x.014 - Interrupt Mask Register */ 653 u32 imask; /* 0x.014 - Interrupt Mask Register */
509 u32 edis; /* 0x.018 - Error Disabled Register */ 654 u32 edis; /* 0x.018 - Error Disabled Register */
510 u8 res2[4]; 655 u32 emapg; /* 0x.01c - Group Error mapping register */
511 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 656 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
512 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 657 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
513 u32 ptv; /* 0x.028 - Pause Time Value Register */ 658 u32 ptv; /* 0x.028 - Pause Time Value Register */
514 u32 dmactrl; /* 0x.02c - DMA Control Register */ 659 u32 dmactrl; /* 0x.02c - DMA Control Register */
515 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 660 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
516 u8 res3[88]; 661 u8 res2[28];
662 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
663 register */
664 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
665 register */
666 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
667 register */
668 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
669 shutoff register */
670 u8 res3[44];
517 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 671 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
518 u8 res4[8]; 672 u8 res4[8];
519 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 673 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
520 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 674 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
521 u8 res5[4]; 675 u8 res5[96];
522 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
523 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
524 u8 res6[84];
525 u32 tctrl; /* 0x.100 - Transmit Control Register */ 676 u32 tctrl; /* 0x.100 - Transmit Control Register */
526 u32 tstat; /* 0x.104 - Transmit Status Register */ 677 u32 tstat; /* 0x.104 - Transmit Status Register */
527 u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 678 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
@@ -572,7 +723,11 @@ struct gfar {
572 u8 res12[8]; 723 u8 res12[8];
573 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 724 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
574 u32 rqueue; /* 0x.314 - Receive queue control register */ 725 u32 rqueue; /* 0x.314 - Receive queue control register */
575 u8 res13[24]; 726 u32 rir0; /* 0x.318 - Ring mapping register 0 */
727 u32 rir1; /* 0x.31c - Ring mapping register 1 */
728 u32 rir2; /* 0x.320 - Ring mapping register 2 */
729 u32 rir3; /* 0x.324 - Ring mapping register 3 */
730 u8 res13[8];
576 u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 731 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
577 u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 732 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
578 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 733 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
@@ -621,7 +776,7 @@ struct gfar {
621 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 776 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
622 u8 res18[12]; 777 u8 res18[12];
623 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 778 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
624 u8 res19[4]; 779 u32 ifctrl; /* 0x.538 - Interface control register */
625 u32 ifstat; /* 0x.53c - Interface Status Register */ 780 u32 ifstat; /* 0x.53c - Interface Status Register */
626 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 781 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
627 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 782 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
@@ -682,8 +837,30 @@ struct gfar {
682 u8 res23c[248]; 837 u8 res23c[248];
683 u32 attr; /* 0x.bf8 - Attributes Register */ 838 u32 attr; /* 0x.bf8 - Attributes Register */
684 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 839 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
685 u8 res24[1024]; 840 u8 res24[688];
686 841 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
842 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
843 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
844 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
845 u8 res25[16];
846 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
847 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
848 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
849 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
850 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
851 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
852 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
853 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
854 u8 res26[32];
855 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
856 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
857 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
858 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
859 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
860 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
861 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
862 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
863 u8 res27[208];
687}; 864};
688 865
689/* Flags related to gianfar device features */ 866/* Flags related to gianfar device features */
@@ -699,6 +876,133 @@ struct gfar {
699#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 876#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
700#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 877#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
701 878
879#if (MAXGROUPS == 2)
880#define DEFAULT_MAPPING 0xAA
881#else
882#define DEFAULT_MAPPING 0xFF
883#endif
884
885#define ISRG_SHIFT_TX 0x10
886#define ISRG_SHIFT_RX 0x18
887
888/* The same driver can operate in two modes */
889/* SQ_SG_MODE: Single Queue Single Group Mode
890 * (Backward compatible mode)
891 * MQ_MG_MODE: Multi Queue Multi Group mode
892 */
893enum {
894 SQ_SG_MODE = 0,
895 MQ_MG_MODE
896};
897
898/**
899 * struct gfar_priv_tx_q - per tx queue structure
900 * @txlock: per queue tx spin lock
901 * @tx_skbuff:skb pointers
902 * @skb_curtx: to be used skb pointer
903 * @skb_dirtytx:the last used skb pointer
904 * @qindex: index of this queue
905 * @dev: back pointer to the dev structure
906 * @grp: back pointer to the group to which this queue belongs
907 * @tx_bd_base: First tx buffer descriptor
908 * @cur_tx: Next free ring entry
909 * @dirty_tx: First buffer in line to be transmitted
910 * @tx_ring_size: Tx ring size
911 * @num_txbdfree: number of free TxBds
912 * @txcoalescing: enable/disable tx coalescing
913 * @txic: transmit interrupt coalescing value
914 * @txcount: coalescing value if based on tx frame count
915 * @txtime: coalescing value if based on time
916 */
917struct gfar_priv_tx_q {
918 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
919 struct sk_buff ** tx_skbuff;
920 /* Buffer descriptor pointers */
921 dma_addr_t tx_bd_dma_base;
922 struct txbd8 *tx_bd_base;
923 struct txbd8 *cur_tx;
924 struct txbd8 *dirty_tx;
925 struct net_device *dev;
926 struct gfar_priv_grp *grp;
927 u16 skb_curtx;
928 u16 skb_dirtytx;
929 u16 qindex;
930 unsigned int tx_ring_size;
931 unsigned int num_txbdfree;
932 /* Configuration info for the coalescing features */
933 unsigned char txcoalescing;
934 unsigned long txic;
935 unsigned short txcount;
936 unsigned short txtime;
937};
938
939/**
940 * struct gfar_priv_rx_q - per rx queue structure
941 * @rxlock: per queue rx spin lock
942 * @rx_skbuff: skb pointers
943 * @skb_currx: currently use skb pointer
944 * @rx_bd_base: First rx buffer descriptor
945 * @cur_rx: Next free rx ring entry
946 * @qindex: index of this queue
947 * @dev: back pointer to the dev structure
948 * @rx_ring_size: Rx ring size
949 * @rxcoalescing: enable/disable rx-coalescing
950 * @rxic: receive interrupt coalescing vlaue
951 */
952
953struct gfar_priv_rx_q {
954 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
955 struct sk_buff ** rx_skbuff;
956 dma_addr_t rx_bd_dma_base;
957 struct rxbd8 *rx_bd_base;
958 struct rxbd8 *cur_rx;
959 struct net_device *dev;
960 struct gfar_priv_grp *grp;
961 u16 skb_currx;
962 u16 qindex;
963 unsigned int rx_ring_size;
964 /* RX Coalescing values */
965 unsigned char rxcoalescing;
966 unsigned long rxic;
967};
968
969/**
970 * struct gfar_priv_grp - per group structure
971 * @napi: the napi poll function
972 * @priv: back pointer to the priv structure
973 * @regs: the ioremapped register space for this group
974 * @grp_id: group id for this group
975 * @interruptTransmit: The TX interrupt number for this group
976 * @interruptReceive: The RX interrupt number for this group
977 * @interruptError: The ERROR interrupt number for this group
978 * @int_name_tx: tx interrupt name for this group
979 * @int_name_rx: rx interrupt name for this group
980 * @int_name_er: er interrupt name for this group
981 */
982
983struct gfar_priv_grp {
984 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
985 struct napi_struct napi;
986 struct gfar_private *priv;
987 struct gfar __iomem *regs;
988 unsigned int grp_id;
989 unsigned long rx_bit_map;
990 unsigned long tx_bit_map;
991 unsigned long num_tx_queues;
992 unsigned long num_rx_queues;
993 unsigned int rstat;
994 unsigned int tstat;
995 unsigned int imask;
996 unsigned int ievent;
997 unsigned int interruptTransmit;
998 unsigned int interruptReceive;
999 unsigned int interruptError;
1000
1001 char int_name_tx[GFAR_INT_NAME_MAX];
1002 char int_name_rx[GFAR_INT_NAME_MAX];
1003 char int_name_er[GFAR_INT_NAME_MAX];
1004};
1005
702/* Struct stolen almost completely (and shamelessly) from the FCC enet source 1006/* Struct stolen almost completely (and shamelessly) from the FCC enet source
703 * (Ok, that's not so true anymore, but there is a family resemblence) 1007 * (Ok, that's not so true anymore, but there is a family resemblence)
704 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1008 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
@@ -709,62 +1013,36 @@ struct gfar {
709 * the buffer descriptor determines the actual condition. 1013 * the buffer descriptor determines the actual condition.
710 */ 1014 */
711struct gfar_private { 1015struct gfar_private {
712 /* Fields controlled by TX lock */
713 spinlock_t txlock;
714 1016
715 /* Pointer to the array of skbuffs */ 1017 /* Indicates how many tx, rx queues are enabled */
716 struct sk_buff ** tx_skbuff; 1018 unsigned int num_tx_queues;
1019 unsigned int num_rx_queues;
1020 unsigned int num_grps;
1021 unsigned int mode;
717 1022
718 /* next free skb in the array */ 1023 /* The total tx and rx ring size for the enabled queues */
719 u16 skb_curtx; 1024 unsigned int total_tx_ring_size;
720 1025 unsigned int total_rx_ring_size;
721 /* First skb in line to be transmitted */
722 u16 skb_dirtytx;
723
724 /* Configuration info for the coalescing features */
725 unsigned char txcoalescing;
726 unsigned long txic;
727
728 /* Buffer descriptor pointers */
729 struct txbd8 *tx_bd_base; /* First tx buffer descriptor */
730 struct txbd8 *cur_tx; /* Next free ring entry */
731 struct txbd8 *dirty_tx; /* First buffer in line
732 to be transmitted */
733 unsigned int tx_ring_size;
734 unsigned int num_txbdfree; /* number of TxBDs free */
735
736 /* RX Locked fields */
737 spinlock_t rxlock;
738 1026
739 struct device_node *node; 1027 struct device_node *node;
740 struct net_device *ndev; 1028 struct net_device *ndev;
741 struct of_device *ofdev; 1029 struct of_device *ofdev;
742 struct napi_struct napi;
743
744 /* skb array and index */
745 struct sk_buff ** rx_skbuff;
746 u16 skb_currx;
747
748 /* RX Coalescing values */
749 unsigned char rxcoalescing;
750 unsigned long rxic;
751 1030
752 struct rxbd8 *rx_bd_base; /* First Rx buffers */ 1031 struct gfar_priv_grp gfargrp[MAXGROUPS];
753 struct rxbd8 *cur_rx; /* Next free rx ring entry */ 1032 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1033 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
754 1034
755 /* RX parameters */ 1035 /* RX per device parameters */
756 unsigned int rx_ring_size;
757 unsigned int rx_buffer_size; 1036 unsigned int rx_buffer_size;
758 unsigned int rx_stash_size; 1037 unsigned int rx_stash_size;
759 unsigned int rx_stash_index; 1038 unsigned int rx_stash_index;
760 1039
1040 u32 cur_filer_idx;
1041
761 struct sk_buff_head rx_recycle; 1042 struct sk_buff_head rx_recycle;
762 1043
763 struct vlan_group *vlgrp; 1044 struct vlan_group *vlgrp;
764 1045
765 /* Unprotected fields */
766 /* Pointer to the GFAR memory mapped Registers */
767 struct gfar __iomem *regs;
768 1046
769 /* Hash registers and their width */ 1047 /* Hash registers and their width */
770 u32 __iomem *hash_regs[16]; 1048 u32 __iomem *hash_regs[16];
@@ -785,13 +1063,10 @@ struct gfar_private {
785 unsigned char rx_csum_enable:1, 1063 unsigned char rx_csum_enable:1,
786 extended_hash:1, 1064 extended_hash:1,
787 bd_stash_en:1, 1065 bd_stash_en:1,
1066 rx_filer_enable:1,
788 wol_en:1; /* Wake-on-LAN enabled */ 1067 wol_en:1; /* Wake-on-LAN enabled */
789 unsigned short padding; 1068 unsigned short padding;
790 1069
791 unsigned int interruptTransmit;
792 unsigned int interruptReceive;
793 unsigned int interruptError;
794
795 /* PHY stuff */ 1070 /* PHY stuff */
796 struct phy_device *phydev; 1071 struct phy_device *phydev;
797 struct mii_bus *mii_bus; 1072 struct mii_bus *mii_bus;
@@ -803,14 +1078,13 @@ struct gfar_private {
803 1078
804 struct work_struct reset_task; 1079 struct work_struct reset_task;
805 1080
806 char int_name_tx[GFAR_INT_NAME_MAX];
807 char int_name_rx[GFAR_INT_NAME_MAX];
808 char int_name_er[GFAR_INT_NAME_MAX];
809
810 /* Network Statistics */ 1081 /* Network Statistics */
811 struct gfar_extra_stats extra_stats; 1082 struct gfar_extra_stats extra_stats;
812}; 1083};
813 1084
1085extern unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1086extern unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1087
814static inline u32 gfar_read(volatile unsigned __iomem *addr) 1088static inline u32 gfar_read(volatile unsigned __iomem *addr)
815{ 1089{
816 u32 val; 1090 u32 val;
@@ -823,12 +1097,28 @@ static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
823 out_be32(addr, val); 1097 out_be32(addr, val);
824} 1098}
825 1099
1100static inline void gfar_write_filer(struct gfar_private *priv,
1101 unsigned int far, unsigned int fcr, unsigned int fpr)
1102{
1103 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1104
1105 gfar_write(&regs->rqfar, far);
1106 gfar_write(&regs->rqfcr, fcr);
1107 gfar_write(&regs->rqfpr, fpr);
1108}
1109
1110extern void lock_rx_qs(struct gfar_private *priv);
1111extern void lock_tx_qs(struct gfar_private *priv);
1112extern void unlock_rx_qs(struct gfar_private *priv);
1113extern void unlock_tx_qs(struct gfar_private *priv);
826extern irqreturn_t gfar_receive(int irq, void *dev_id); 1114extern irqreturn_t gfar_receive(int irq, void *dev_id);
827extern int startup_gfar(struct net_device *dev); 1115extern int startup_gfar(struct net_device *dev);
828extern void stop_gfar(struct net_device *dev); 1116extern void stop_gfar(struct net_device *dev);
829extern void gfar_halt(struct net_device *dev); 1117extern void gfar_halt(struct net_device *dev);
830extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, 1118extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
831 int enable, u32 regnum, u32 read); 1119 int enable, u32 regnum, u32 read);
1120extern void gfar_configure_coalescing(struct gfar_private *priv,
1121 unsigned long tx_mask, unsigned long rx_mask);
832void gfar_init_sysfs(struct net_device *dev); 1122void gfar_init_sysfs(struct net_device *dev);
833 1123
834extern const struct ethtool_ops gfar_ethtool_ops; 1124extern const struct ethtool_ops gfar_ethtool_ops;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 17:23:14 -0500