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path: root/drivers/net/gianfar.h
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-rw-r--r--drivers/net/gianfar.h363
1 files changed, 280 insertions, 83 deletions
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index c2f783a6a9fa..28af087d9fbb 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * drivers/net/gianfar.h 2 * drivers/net/gianfar.h
3 * 3 *
4 * Gianfar Ethernet Driver 4 * Gianfar Ethernet Driver
@@ -53,6 +53,12 @@
53/* The maximum number of packets to be handled in one call of gfar_poll */ 53/* The maximum number of packets to be handled in one call of gfar_poll */
54#define GFAR_DEV_WEIGHT 64 54#define GFAR_DEV_WEIGHT 64
55 55
56/* Length for FCB */
57#define GMAC_FCB_LEN 8
58
59/* Default padding amount */
60#define DEFAULT_PADDING 2
61
56/* Number of bytes to align the rx bufs to */ 62/* Number of bytes to align the rx bufs to */
57#define RXBUF_ALIGNMENT 64 63#define RXBUF_ALIGNMENT 64
58 64
@@ -91,7 +97,7 @@ extern const char gfar_driver_version[];
91#define JUMBO_FRAME_SIZE 9600 97#define JUMBO_FRAME_SIZE 9600
92 98
93/* Latency of interface clock in nanoseconds */ 99/* Latency of interface clock in nanoseconds */
94/* Interface clock latency , in this case, means the 100/* Interface clock latency , in this case, means the
95 * time described by a value of 1 in the interrupt 101 * time described by a value of 1 in the interrupt
96 * coalescing registers' time fields. Since those fields 102 * coalescing registers' time fields. Since those fields
97 * refer to the time it takes for 64 clocks to pass, the 103 * refer to the time it takes for 64 clocks to pass, the
@@ -166,9 +172,28 @@ extern const char gfar_driver_version[];
166 mk_ic_icft(count) | \ 172 mk_ic_icft(count) | \
167 mk_ic_ictt(time)) 173 mk_ic_ictt(time))
168 174
175#define RCTRL_PAL_MASK 0x001f0000
176#define RCTRL_VLEX 0x00002000
177#define RCTRL_FILREN 0x00001000
178#define RCTRL_GHTX 0x00000400
179#define RCTRL_IPCSEN 0x00000200
180#define RCTRL_TUCSEN 0x00000100
181#define RCTRL_PRSDEP_MASK 0x000000c0
182#define RCTRL_PRSDEP_INIT 0x000000c0
169#define RCTRL_PROM 0x00000008 183#define RCTRL_PROM 0x00000008
184#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \
185 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
186#define RCTRL_EXTHASH (RCTRL_GHTX)
187#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
188
189
170#define RSTAT_CLEAR_RHALT 0x00800000 190#define RSTAT_CLEAR_RHALT 0x00800000
171 191
192#define TCTRL_IPCSEN 0x00004000
193#define TCTRL_TUCSEN 0x00002000
194#define TCTRL_VLINS 0x00001000
195#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
196
172#define IEVENT_INIT_CLEAR 0xffffffff 197#define IEVENT_INIT_CLEAR 0xffffffff
173#define IEVENT_BABR 0x80000000 198#define IEVENT_BABR 0x80000000
174#define IEVENT_RXC 0x40000000 199#define IEVENT_RXC 0x40000000
@@ -187,12 +212,16 @@ extern const char gfar_driver_version[];
187#define IEVENT_RXB0 0x00008000 212#define IEVENT_RXB0 0x00008000
188#define IEVENT_GRSC 0x00000100 213#define IEVENT_GRSC 0x00000100
189#define IEVENT_RXF0 0x00000080 214#define IEVENT_RXF0 0x00000080
215#define IEVENT_FIR 0x00000008
216#define IEVENT_FIQ 0x00000004
217#define IEVENT_DPE 0x00000002
218#define IEVENT_PERR 0x00000001
190#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0) 219#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
191#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 220#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
192#define IEVENT_ERR_MASK \ 221#define IEVENT_ERR_MASK \
193(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 222(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
194 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 223 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
195 | IEVENT_CRL | IEVENT_XFUN) 224 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
196 225
197#define IMASK_INIT_CLEAR 0x00000000 226#define IMASK_INIT_CLEAR 0x00000000
198#define IMASK_BABR 0x80000000 227#define IMASK_BABR 0x80000000
@@ -212,10 +241,15 @@ extern const char gfar_driver_version[];
212#define IMASK_RXB0 0x00008000 241#define IMASK_RXB0 0x00008000
213#define IMASK_GTSC 0x00000100 242#define IMASK_GTSC 0x00000100
214#define IMASK_RXFEN0 0x00000080 243#define IMASK_RXFEN0 0x00000080
244#define IMASK_FIR 0x00000008
245#define IMASK_FIQ 0x00000004
246#define IMASK_DPE 0x00000002
247#define IMASK_PERR 0x00000001
215#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY) 248#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
216#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 249#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
217 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 250 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
218 IMASK_XFUN | IMASK_RXC | IMASK_BABT) 251 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
252 | IMASK_PERR)
219 253
220 254
221/* Attribute fields */ 255/* Attribute fields */
@@ -254,6 +288,18 @@ extern const char gfar_driver_version[];
254#define TXBD_RETRYLIMIT 0x0040 288#define TXBD_RETRYLIMIT 0x0040
255#define TXBD_RETRYCOUNTMASK 0x003c 289#define TXBD_RETRYCOUNTMASK 0x003c
256#define TXBD_UNDERRUN 0x0002 290#define TXBD_UNDERRUN 0x0002
291#define TXBD_TOE 0x0002
292
293/* Tx FCB param bits */
294#define TXFCB_VLN 0x80
295#define TXFCB_IP 0x40
296#define TXFCB_IP6 0x20
297#define TXFCB_TUP 0x10
298#define TXFCB_UDP 0x08
299#define TXFCB_CIP 0x04
300#define TXFCB_CTU 0x02
301#define TXFCB_NPH 0x01
302#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
257 303
258/* RxBD status field bits */ 304/* RxBD status field bits */
259#define RXBD_EMPTY 0x8000 305#define RXBD_EMPTY 0x8000
@@ -273,6 +319,18 @@ extern const char gfar_driver_version[];
273#define RXBD_TRUNCATED 0x0001 319#define RXBD_TRUNCATED 0x0001
274#define RXBD_STATS 0x01ff 320#define RXBD_STATS 0x01ff
275 321
322/* Rx FCB status field bits */
323#define RXFCB_VLN 0x8000
324#define RXFCB_IP 0x4000
325#define RXFCB_IP6 0x2000
326#define RXFCB_TUP 0x1000
327#define RXFCB_CIP 0x0800
328#define RXFCB_CTU 0x0400
329#define RXFCB_EIP 0x0200
330#define RXFCB_ETU 0x0100
331#define RXFCB_PERR_MASK 0x000c
332#define RXFCB_PERR_BADL3 0x0008
333
276struct txbd8 334struct txbd8
277{ 335{
278 u16 status; /* Status Fields */ 336 u16 status; /* Status Fields */
@@ -280,6 +338,22 @@ struct txbd8
280 u32 bufPtr; /* Buffer Pointer */ 338 u32 bufPtr; /* Buffer Pointer */
281}; 339};
282 340
341struct txfcb {
342 u8 vln:1,
343 ip:1,
344 ip6:1,
345 tup:1,
346 udp:1,
347 cip:1,
348 ctu:1,
349 nph:1;
350 u8 reserved;
351 u8 l4os; /* Level 4 Header Offset */
352 u8 l3os; /* Level 3 Header Offset */
353 u16 phcs; /* Pseudo-header Checksum */
354 u16 vlctl; /* VLAN control word */
355};
356
283struct rxbd8 357struct rxbd8
284{ 358{
285 u16 status; /* Status Fields */ 359 u16 status; /* Status Fields */
@@ -287,6 +361,21 @@ struct rxbd8
287 u32 bufPtr; /* Buffer Pointer */ 361 u32 bufPtr; /* Buffer Pointer */
288}; 362};
289 363
364struct rxfcb {
365 u16 vln:1,
366 ip:1,
367 ip6:1,
368 tup:1,
369 cip:1,
370 ctu:1,
371 eip:1,
372 etu:1;
373 u8 rq; /* Receive Queue index */
374 u8 pro; /* Layer 4 Protocol */
375 u16 reserved;
376 u16 vlctl; /* VLAN control word */
377};
378
290struct rmon_mib 379struct rmon_mib
291{ 380{
292 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 381 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
@@ -371,90 +460,191 @@ struct gfar_stats {
371 460
372 461
373struct gfar { 462struct gfar {
374 u8 res1[16]; 463 u32 tsec_id; /* 0x.000 - Controller ID register */
375 u32 ievent; /* 0x.010 - Interrupt Event Register */ 464 u8 res1[12];
376 u32 imask; /* 0x.014 - Interrupt Mask Register */ 465 u32 ievent; /* 0x.010 - Interrupt Event Register */
377 u32 edis; /* 0x.018 - Error Disabled Register */ 466 u32 imask; /* 0x.014 - Interrupt Mask Register */
467 u32 edis; /* 0x.018 - Error Disabled Register */
378 u8 res2[4]; 468 u8 res2[4];
379 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 469 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
380 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 470 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
381 u32 ptv; /* 0x.028 - Pause Time Value Register */ 471 u32 ptv; /* 0x.028 - Pause Time Value Register */
382 u32 dmactrl; /* 0x.02c - DMA Control Register */ 472 u32 dmactrl; /* 0x.02c - DMA Control Register */
383 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 473 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
384 u8 res3[88]; 474 u8 res3[88];
385 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 475 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
386 u8 res4[8]; 476 u8 res4[8];
387 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 477 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
388 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 478 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
389 u8 res5[96]; 479 u8 res5[4];
390 u32 tctrl; /* 0x.100 - Transmit Control Register */ 480 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
391 u32 tstat; /* 0x.104 - Transmit Status Register */ 481 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
392 u8 res6[4]; 482 u8 res6[84];
393 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 483 u32 tctrl; /* 0x.100 - Transmit Control Register */
394 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 484 u32 tstat; /* 0x.104 - Transmit Status Register */
395 u8 res7[16]; 485 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
396 u32 ctbptr; /* 0x.124 - Current Transmit Buffer Descriptor Pointer Register */ 486 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
397 u8 res8[92]; 487 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
398 u32 tbptr; /* 0x.184 - Transmit Buffer Descriptor Pointer Low Register */ 488 u32 tqueue; /* 0x.114 - Transmit queue control register */
399 u8 res9[124]; 489 u8 res7[40];
400 u32 tbase; /* 0x.204 - Transmit Descriptor Base Address Register */ 490 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
401 u8 res10[168]; 491 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
402 u32 ostbd; /* 0x.2b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ 492 u8 res8[52];
403 u32 ostbdp; /* 0x.2b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ 493 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
404 u8 res11[72]; 494 u8 res9a[4];
405 u32 rctrl; /* 0x.300 - Receive Control Register */ 495 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
406 u32 rstat; /* 0x.304 - Receive Status Register */ 496 u8 res9b[4];
407 u8 res12[4]; 497 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
408 u32 rbdlen; /* 0x.30c - RxBD Data Length Register */ 498 u8 res9c[4];
409 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 499 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
410 u8 res13[16]; 500 u8 res9d[4];
411 u32 crbptr; /* 0x.324 - Current Receive Buffer Descriptor Pointer */ 501 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
412 u8 res14[24]; 502 u8 res9e[4];
413 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 503 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
414 u8 res15[64]; 504 u8 res9f[4];
415 u32 rbptr; /* 0x.384 - Receive Buffer Descriptor Pointer */ 505 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
416 u8 res16[124]; 506 u8 res9g[4];
417 u32 rbase; /* 0x.404 - Receive Descriptor Base Address */ 507 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
418 u8 res17[248]; 508 u8 res9h[4];
419 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 509 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
420 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 510 u8 res9[64];
421 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 511 u32 tbaseh; /* 0x.200 - TxBD base address high */
422 u32 hafdup; /* 0x.50c - Half Duplex Register */ 512 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
423 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 513 u8 res10a[4];
514 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
515 u8 res10b[4];
516 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
517 u8 res10c[4];
518 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
519 u8 res10d[4];
520 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
521 u8 res10e[4];
522 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
523 u8 res10f[4];
524 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
525 u8 res10g[4];
526 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
527 u8 res10[192];
528 u32 rctrl; /* 0x.300 - Receive Control Register */
529 u32 rstat; /* 0x.304 - Receive Status Register */
530 u8 res12[8];
531 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
532 u32 rqueue; /* 0x.314 - Receive queue control register */
533 u8 res13[24];
534 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
535 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
536 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
537 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
538 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
539 u8 res14[56];
540 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
541 u8 res15a[4];
542 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
543 u8 res15b[4];
544 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
545 u8 res15c[4];
546 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
547 u8 res15d[4];
548 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
549 u8 res15e[4];
550 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
551 u8 res15f[4];
552 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
553 u8 res15g[4];
554 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
555 u8 res15h[4];
556 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
557 u8 res16[64];
558 u32 rbaseh; /* 0x.400 - RxBD base address high */
559 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
560 u8 res17a[4];
561 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
562 u8 res17b[4];
563 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
564 u8 res17c[4];
565 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
566 u8 res17d[4];
567 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
568 u8 res17e[4];
569 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
570 u8 res17f[4];
571 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
572 u8 res17g[4];
573 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
574 u8 res17[192];
575 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
576 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
577 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
578 u32 hafdup; /* 0x.50c - Half Duplex Register */
579 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
424 u8 res18[12]; 580 u8 res18[12];
425 u32 miimcfg; /* 0x.520 - MII Management Configuration Register */ 581 u32 miimcfg; /* 0x.520 - MII Management Configuration Register */
426 u32 miimcom; /* 0x.524 - MII Management Command Register */ 582 u32 miimcom; /* 0x.524 - MII Management Command Register */
427 u32 miimadd; /* 0x.528 - MII Management Address Register */ 583 u32 miimadd; /* 0x.528 - MII Management Address Register */
428 u32 miimcon; /* 0x.52c - MII Management Control Register */ 584 u32 miimcon; /* 0x.52c - MII Management Control Register */
429 u32 miimstat; /* 0x.530 - MII Management Status Register */ 585 u32 miimstat; /* 0x.530 - MII Management Status Register */
430 u32 miimind; /* 0x.534 - MII Management Indicator Register */ 586 u32 miimind; /* 0x.534 - MII Management Indicator Register */
431 u8 res19[4]; 587 u8 res19[4];
432 u32 ifstat; /* 0x.53c - Interface Status Register */ 588 u32 ifstat; /* 0x.53c - Interface Status Register */
433 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 589 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
434 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 590 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
435 u8 res20[312]; 591 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
436 struct rmon_mib rmon; 592 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
437 u8 res21[192]; 593 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
438 u32 iaddr0; /* 0x.800 - Indivdual address register 0 */ 594 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
439 u32 iaddr1; /* 0x.804 - Indivdual address register 1 */ 595 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
440 u32 iaddr2; /* 0x.808 - Indivdual address register 2 */ 596 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
441 u32 iaddr3; /* 0x.80c - Indivdual address register 3 */ 597 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
442 u32 iaddr4; /* 0x.810 - Indivdual address register 4 */ 598 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
443 u32 iaddr5; /* 0x.814 - Indivdual address register 5 */ 599 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
444 u32 iaddr6; /* 0x.818 - Indivdual address register 6 */ 600 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
445 u32 iaddr7; /* 0x.81c - Indivdual address register 7 */ 601 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
602 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
603 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
604 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
605 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
606 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
607 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
608 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
609 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
610 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
611 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
612 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
613 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
614 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
615 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
616 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
617 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
618 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
619 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
620 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
621 u8 res20[192];
622 struct rmon_mib rmon; /* 0x.680-0x.73c */
623 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
624 u8 res21[188];
625 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
626 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
627 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
628 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
629 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
630 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
631 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
632 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
446 u8 res22[96]; 633 u8 res22[96];
447 u32 gaddr0; /* 0x.880 - Global address register 0 */ 634 u32 gaddr0; /* 0x.880 - Group address register 0 */
448 u32 gaddr1; /* 0x.884 - Global address register 1 */ 635 u32 gaddr1; /* 0x.884 - Group address register 1 */
449 u32 gaddr2; /* 0x.888 - Global address register 2 */ 636 u32 gaddr2; /* 0x.888 - Group address register 2 */
450 u32 gaddr3; /* 0x.88c - Global address register 3 */ 637 u32 gaddr3; /* 0x.88c - Group address register 3 */
451 u32 gaddr4; /* 0x.890 - Global address register 4 */ 638 u32 gaddr4; /* 0x.890 - Group address register 4 */
452 u32 gaddr5; /* 0x.894 - Global address register 5 */ 639 u32 gaddr5; /* 0x.894 - Group address register 5 */
453 u32 gaddr6; /* 0x.898 - Global address register 6 */ 640 u32 gaddr6; /* 0x.898 - Group address register 6 */
454 u32 gaddr7; /* 0x.89c - Global address register 7 */ 641 u32 gaddr7; /* 0x.89c - Group address register 7 */
455 u8 res23[856]; 642 u8 res23a[352];
456 u32 attr; /* 0x.bf8 - Attributes Register */ 643 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
457 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 644 u8 res23b[252];
645 u8 res23c[248];
646 u32 attr; /* 0x.bf8 - Attributes Register */
647 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
458 u8 res24[1024]; 648 u8 res24[1024];
459 649
460}; 650};
@@ -496,6 +686,8 @@ struct gfar_private {
496 struct txbd8 *cur_tx; /* Next free ring entry */ 686 struct txbd8 *cur_tx; /* Next free ring entry */
497 struct txbd8 *dirty_tx; /* The Ring entry to be freed. */ 687 struct txbd8 *dirty_tx; /* The Ring entry to be freed. */
498 struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */ 688 struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */
689 u32 *hash_regs[16];
690 int hash_width;
499 struct gfar *phyregs; 691 struct gfar *phyregs;
500 struct work_struct tq; 692 struct work_struct tq;
501 struct timer_list phy_info_timer; 693 struct timer_list phy_info_timer;
@@ -506,9 +698,12 @@ struct gfar_private {
506 unsigned int rx_stash_size; 698 unsigned int rx_stash_size;
507 unsigned int tx_ring_size; 699 unsigned int tx_ring_size;
508 unsigned int rx_ring_size; 700 unsigned int rx_ring_size;
509 wait_queue_head_t rxcleanupq;
510 unsigned int rxclean;
511 701
702 unsigned char vlan_enable:1,
703 rx_csum_enable:1,
704 extended_hash:1;
705 unsigned short padding;
706 struct vlan_group *vlgrp;
512 /* Info structure initialized by board setup code */ 707 /* Info structure initialized by board setup code */
513 unsigned int interruptTransmit; 708 unsigned int interruptTransmit;
514 unsigned int interruptReceive; 709 unsigned int interruptReceive;
@@ -519,6 +714,8 @@ struct gfar_private {
519 int oldspeed; 714 int oldspeed;
520 int oldduplex; 715 int oldduplex;
521 int oldlink; 716 int oldlink;
717
718 uint32_t msg_enable;
522}; 719};
523 720
524extern inline u32 gfar_read(volatile unsigned *addr) 721extern inline u32 gfar_read(volatile unsigned *addr)