diff options
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r-- | drivers/net/forcedeth.c | 1168 |
1 files changed, 490 insertions, 678 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 0fa1776563a3..af09296ef0dd 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
@@ -39,6 +39,9 @@ | |||
39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | 39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
40 | * superfluous timer interrupts from the nic. | 40 | * superfluous timer interrupts from the nic. |
41 | */ | 41 | */ |
42 | |||
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
44 | |||
42 | #define FORCEDETH_VERSION "0.64" | 45 | #define FORCEDETH_VERSION "0.64" |
43 | #define DRV_NAME "forcedeth" | 46 | #define DRV_NAME "forcedeth" |
44 | 47 | ||
@@ -60,18 +63,12 @@ | |||
60 | #include <linux/if_vlan.h> | 63 | #include <linux/if_vlan.h> |
61 | #include <linux/dma-mapping.h> | 64 | #include <linux/dma-mapping.h> |
62 | #include <linux/slab.h> | 65 | #include <linux/slab.h> |
66 | #include <linux/uaccess.h> | ||
67 | #include <linux/io.h> | ||
63 | 68 | ||
64 | #include <asm/irq.h> | 69 | #include <asm/irq.h> |
65 | #include <asm/io.h> | ||
66 | #include <asm/uaccess.h> | ||
67 | #include <asm/system.h> | 70 | #include <asm/system.h> |
68 | 71 | ||
69 | #if 0 | ||
70 | #define dprintk printk | ||
71 | #else | ||
72 | #define dprintk(x...) do { } while (0) | ||
73 | #endif | ||
74 | |||
75 | #define TX_WORK_PER_LOOP 64 | 72 | #define TX_WORK_PER_LOOP 64 |
76 | #define RX_WORK_PER_LOOP 64 | 73 | #define RX_WORK_PER_LOOP 64 |
77 | 74 | ||
@@ -186,9 +183,9 @@ enum { | |||
186 | NvRegSlotTime = 0x9c, | 183 | NvRegSlotTime = 0x9c, |
187 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | 184 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 |
188 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | 185 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 |
189 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 | 186 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 |
190 | #define NVREG_SLOTTIME_HALF 0x0000ff00 | 187 | #define NVREG_SLOTTIME_HALF 0x0000ff00 |
191 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 | 188 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 |
192 | #define NVREG_SLOTTIME_MASK 0x000000ff | 189 | #define NVREG_SLOTTIME_MASK 0x000000ff |
193 | 190 | ||
194 | NvRegTxDeferral = 0xA0, | 191 | NvRegTxDeferral = 0xA0, |
@@ -297,7 +294,7 @@ enum { | |||
297 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | 294 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
298 | 295 | ||
299 | NvRegMgmtUnitGetVersion = 0x204, | 296 | NvRegMgmtUnitGetVersion = 0x204, |
300 | #define NVREG_MGMTUNITGETVERSION 0x01 | 297 | #define NVREG_MGMTUNITGETVERSION 0x01 |
301 | NvRegMgmtUnitVersion = 0x208, | 298 | NvRegMgmtUnitVersion = 0x208, |
302 | #define NVREG_MGMTUNITVERSION 0x08 | 299 | #define NVREG_MGMTUNITVERSION 0x08 |
303 | NvRegPowerCap = 0x268, | 300 | NvRegPowerCap = 0x268, |
@@ -368,8 +365,8 @@ struct ring_desc_ex { | |||
368 | }; | 365 | }; |
369 | 366 | ||
370 | union ring_type { | 367 | union ring_type { |
371 | struct ring_desc* orig; | 368 | struct ring_desc *orig; |
372 | struct ring_desc_ex* ex; | 369 | struct ring_desc_ex *ex; |
373 | }; | 370 | }; |
374 | 371 | ||
375 | #define FLAG_MASK_V1 0xffff0000 | 372 | #define FLAG_MASK_V1 0xffff0000 |
@@ -444,10 +441,10 @@ union ring_type { | |||
444 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | 441 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) |
445 | 442 | ||
446 | /* Miscelaneous hardware related defines: */ | 443 | /* Miscelaneous hardware related defines: */ |
447 | #define NV_PCI_REGSZ_VER1 0x270 | 444 | #define NV_PCI_REGSZ_VER1 0x270 |
448 | #define NV_PCI_REGSZ_VER2 0x2d4 | 445 | #define NV_PCI_REGSZ_VER2 0x2d4 |
449 | #define NV_PCI_REGSZ_VER3 0x604 | 446 | #define NV_PCI_REGSZ_VER3 0x604 |
450 | #define NV_PCI_REGSZ_MAX 0x604 | 447 | #define NV_PCI_REGSZ_MAX 0x604 |
451 | 448 | ||
452 | /* various timeout delays: all in usec */ | 449 | /* various timeout delays: all in usec */ |
453 | #define NV_TXRX_RESET_DELAY 4 | 450 | #define NV_TXRX_RESET_DELAY 4 |
@@ -717,7 +714,7 @@ static const struct register_test nv_registers_test[] = { | |||
717 | { NvRegMulticastAddrA, 0xffffffff }, | 714 | { NvRegMulticastAddrA, 0xffffffff }, |
718 | { NvRegTxWatermark, 0x0ff }, | 715 | { NvRegTxWatermark, 0x0ff }, |
719 | { NvRegWakeUpFlags, 0x07777 }, | 716 | { NvRegWakeUpFlags, 0x07777 }, |
720 | { 0,0 } | 717 | { 0, 0 } |
721 | }; | 718 | }; |
722 | 719 | ||
723 | struct nv_skb_map { | 720 | struct nv_skb_map { |
@@ -911,7 +908,7 @@ static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |||
911 | * Power down phy when interface is down (persists through reboot; | 908 | * Power down phy when interface is down (persists through reboot; |
912 | * older Linux and other OSes may not power it up again) | 909 | * older Linux and other OSes may not power it up again) |
913 | */ | 910 | */ |
914 | static int phy_power_down = 0; | 911 | static int phy_power_down; |
915 | 912 | ||
916 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) | 913 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
917 | { | 914 | { |
@@ -948,7 +945,7 @@ static bool nv_optimized(struct fe_priv *np) | |||
948 | } | 945 | } |
949 | 946 | ||
950 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, | 947 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
951 | int delay, int delaymax, const char *msg) | 948 | int delay, int delaymax) |
952 | { | 949 | { |
953 | u8 __iomem *base = get_hwbase(dev); | 950 | u8 __iomem *base = get_hwbase(dev); |
954 | 951 | ||
@@ -956,11 +953,8 @@ static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, | |||
956 | do { | 953 | do { |
957 | udelay(delay); | 954 | udelay(delay); |
958 | delaymax -= delay; | 955 | delaymax -= delay; |
959 | if (delaymax < 0) { | 956 | if (delaymax < 0) |
960 | if (msg) | ||
961 | printk("%s", msg); | ||
962 | return 1; | 957 | return 1; |
963 | } | ||
964 | } while ((readl(base + offset) & mask) != target); | 958 | } while ((readl(base + offset) & mask) != target); |
965 | return 0; | 959 | return 0; |
966 | } | 960 | } |
@@ -984,12 +978,10 @@ static void setup_hw_rings(struct net_device *dev, int rxtx_flags) | |||
984 | u8 __iomem *base = get_hwbase(dev); | 978 | u8 __iomem *base = get_hwbase(dev); |
985 | 979 | ||
986 | if (!nv_optimized(np)) { | 980 | if (!nv_optimized(np)) { |
987 | if (rxtx_flags & NV_SETUP_RX_RING) { | 981 | if (rxtx_flags & NV_SETUP_RX_RING) |
988 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); | 982 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
989 | } | 983 | if (rxtx_flags & NV_SETUP_TX_RING) |
990 | if (rxtx_flags & NV_SETUP_TX_RING) { | ||
991 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); | 984 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
992 | } | ||
993 | } else { | 985 | } else { |
994 | if (rxtx_flags & NV_SETUP_RX_RING) { | 986 | if (rxtx_flags & NV_SETUP_RX_RING) { |
995 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); | 987 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
@@ -1015,10 +1007,8 @@ static void free_rings(struct net_device *dev) | |||
1015 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | 1007 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
1016 | np->rx_ring.ex, np->ring_addr); | 1008 | np->rx_ring.ex, np->ring_addr); |
1017 | } | 1009 | } |
1018 | if (np->rx_skb) | 1010 | kfree(np->rx_skb); |
1019 | kfree(np->rx_skb); | 1011 | kfree(np->tx_skb); |
1020 | if (np->tx_skb) | ||
1021 | kfree(np->tx_skb); | ||
1022 | } | 1012 | } |
1023 | 1013 | ||
1024 | static int using_multi_irqs(struct net_device *dev) | 1014 | static int using_multi_irqs(struct net_device *dev) |
@@ -1145,23 +1135,15 @@ static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |||
1145 | writel(reg, base + NvRegMIIControl); | 1135 | writel(reg, base + NvRegMIIControl); |
1146 | 1136 | ||
1147 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | 1137 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, |
1148 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { | 1138 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) { |
1149 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", | ||
1150 | dev->name, miireg, addr); | ||
1151 | retval = -1; | 1139 | retval = -1; |
1152 | } else if (value != MII_READ) { | 1140 | } else if (value != MII_READ) { |
1153 | /* it was a write operation - fewer failures are detectable */ | 1141 | /* it was a write operation - fewer failures are detectable */ |
1154 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", | ||
1155 | dev->name, value, miireg, addr); | ||
1156 | retval = 0; | 1142 | retval = 0; |
1157 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | 1143 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { |
1158 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", | ||
1159 | dev->name, miireg, addr); | ||
1160 | retval = -1; | 1144 | retval = -1; |
1161 | } else { | 1145 | } else { |
1162 | retval = readl(base + NvRegMIIData); | 1146 | retval = readl(base + NvRegMIIData); |
1163 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", | ||
1164 | dev->name, miireg, addr, retval); | ||
1165 | } | 1147 | } |
1166 | 1148 | ||
1167 | return retval; | 1149 | return retval; |
@@ -1174,16 +1156,15 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup) | |||
1174 | unsigned int tries = 0; | 1156 | unsigned int tries = 0; |
1175 | 1157 | ||
1176 | miicontrol = BMCR_RESET | bmcr_setup; | 1158 | miicontrol = BMCR_RESET | bmcr_setup; |
1177 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { | 1159 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) |
1178 | return -1; | 1160 | return -1; |
1179 | } | ||
1180 | 1161 | ||
1181 | /* wait for 500ms */ | 1162 | /* wait for 500ms */ |
1182 | msleep(500); | 1163 | msleep(500); |
1183 | 1164 | ||
1184 | /* must wait till reset is deasserted */ | 1165 | /* must wait till reset is deasserted */ |
1185 | while (miicontrol & BMCR_RESET) { | 1166 | while (miicontrol & BMCR_RESET) { |
1186 | msleep(10); | 1167 | usleep_range(10000, 20000); |
1187 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 1168 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1188 | /* FIXME: 100 tries seem excessive */ | 1169 | /* FIXME: 100 tries seem excessive */ |
1189 | if (tries++ > 100) | 1170 | if (tries++ > 100) |
@@ -1192,106 +1173,239 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup) | |||
1192 | return 0; | 1173 | return 0; |
1193 | } | 1174 | } |
1194 | 1175 | ||
1176 | static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np) | ||
1177 | { | ||
1178 | static const struct { | ||
1179 | int reg; | ||
1180 | int init; | ||
1181 | } ri[] = { | ||
1182 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | ||
1183 | { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 }, | ||
1184 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 }, | ||
1185 | { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 }, | ||
1186 | { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 }, | ||
1187 | { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 }, | ||
1188 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | ||
1189 | }; | ||
1190 | int i; | ||
1191 | |||
1192 | for (i = 0; i < ARRAY_SIZE(ri); i++) { | ||
1193 | if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) | ||
1194 | return PHY_ERROR; | ||
1195 | } | ||
1196 | |||
1197 | return 0; | ||
1198 | } | ||
1199 | |||
1200 | static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np) | ||
1201 | { | ||
1202 | u32 reg; | ||
1203 | u8 __iomem *base = get_hwbase(dev); | ||
1204 | u32 powerstate = readl(base + NvRegPowerState2); | ||
1205 | |||
1206 | /* need to perform hw phy reset */ | ||
1207 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | ||
1208 | writel(powerstate, base + NvRegPowerState2); | ||
1209 | msleep(25); | ||
1210 | |||
1211 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | ||
1212 | writel(powerstate, base + NvRegPowerState2); | ||
1213 | msleep(25); | ||
1214 | |||
1215 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | ||
1216 | reg |= PHY_REALTEK_INIT9; | ||
1217 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) | ||
1218 | return PHY_ERROR; | ||
1219 | if (mii_rw(dev, np->phyaddr, | ||
1220 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) | ||
1221 | return PHY_ERROR; | ||
1222 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | ||
1223 | if (!(reg & PHY_REALTEK_INIT11)) { | ||
1224 | reg |= PHY_REALTEK_INIT11; | ||
1225 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) | ||
1226 | return PHY_ERROR; | ||
1227 | } | ||
1228 | if (mii_rw(dev, np->phyaddr, | ||
1229 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | ||
1230 | return PHY_ERROR; | ||
1231 | |||
1232 | return 0; | ||
1233 | } | ||
1234 | |||
1235 | static int init_realtek_8201(struct net_device *dev, struct fe_priv *np) | ||
1236 | { | ||
1237 | u32 phy_reserved; | ||
1238 | |||
1239 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { | ||
1240 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1241 | PHY_REALTEK_INIT_REG6, MII_READ); | ||
1242 | phy_reserved |= PHY_REALTEK_INIT7; | ||
1243 | if (mii_rw(dev, np->phyaddr, | ||
1244 | PHY_REALTEK_INIT_REG6, phy_reserved)) | ||
1245 | return PHY_ERROR; | ||
1246 | } | ||
1247 | |||
1248 | return 0; | ||
1249 | } | ||
1250 | |||
1251 | static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np) | ||
1252 | { | ||
1253 | u32 phy_reserved; | ||
1254 | |||
1255 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | ||
1256 | if (mii_rw(dev, np->phyaddr, | ||
1257 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) | ||
1258 | return PHY_ERROR; | ||
1259 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1260 | PHY_REALTEK_INIT_REG2, MII_READ); | ||
1261 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | ||
1262 | phy_reserved |= PHY_REALTEK_INIT3; | ||
1263 | if (mii_rw(dev, np->phyaddr, | ||
1264 | PHY_REALTEK_INIT_REG2, phy_reserved)) | ||
1265 | return PHY_ERROR; | ||
1266 | if (mii_rw(dev, np->phyaddr, | ||
1267 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | ||
1268 | return PHY_ERROR; | ||
1269 | } | ||
1270 | |||
1271 | return 0; | ||
1272 | } | ||
1273 | |||
1274 | static int init_cicada(struct net_device *dev, struct fe_priv *np, | ||
1275 | u32 phyinterface) | ||
1276 | { | ||
1277 | u32 phy_reserved; | ||
1278 | |||
1279 | if (phyinterface & PHY_RGMII) { | ||
1280 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | ||
1281 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); | ||
1282 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | ||
1283 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) | ||
1284 | return PHY_ERROR; | ||
1285 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | ||
1286 | phy_reserved |= PHY_CICADA_INIT5; | ||
1287 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) | ||
1288 | return PHY_ERROR; | ||
1289 | } | ||
1290 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | ||
1291 | phy_reserved |= PHY_CICADA_INIT6; | ||
1292 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) | ||
1293 | return PHY_ERROR; | ||
1294 | |||
1295 | return 0; | ||
1296 | } | ||
1297 | |||
1298 | static int init_vitesse(struct net_device *dev, struct fe_priv *np) | ||
1299 | { | ||
1300 | u32 phy_reserved; | ||
1301 | |||
1302 | if (mii_rw(dev, np->phyaddr, | ||
1303 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) | ||
1304 | return PHY_ERROR; | ||
1305 | if (mii_rw(dev, np->phyaddr, | ||
1306 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) | ||
1307 | return PHY_ERROR; | ||
1308 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1309 | PHY_VITESSE_INIT_REG4, MII_READ); | ||
1310 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | ||
1311 | return PHY_ERROR; | ||
1312 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1313 | PHY_VITESSE_INIT_REG3, MII_READ); | ||
1314 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | ||
1315 | phy_reserved |= PHY_VITESSE_INIT3; | ||
1316 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | ||
1317 | return PHY_ERROR; | ||
1318 | if (mii_rw(dev, np->phyaddr, | ||
1319 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) | ||
1320 | return PHY_ERROR; | ||
1321 | if (mii_rw(dev, np->phyaddr, | ||
1322 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) | ||
1323 | return PHY_ERROR; | ||
1324 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1325 | PHY_VITESSE_INIT_REG4, MII_READ); | ||
1326 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | ||
1327 | phy_reserved |= PHY_VITESSE_INIT3; | ||
1328 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | ||
1329 | return PHY_ERROR; | ||
1330 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1331 | PHY_VITESSE_INIT_REG3, MII_READ); | ||
1332 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | ||
1333 | return PHY_ERROR; | ||
1334 | if (mii_rw(dev, np->phyaddr, | ||
1335 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) | ||
1336 | return PHY_ERROR; | ||
1337 | if (mii_rw(dev, np->phyaddr, | ||
1338 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) | ||
1339 | return PHY_ERROR; | ||
1340 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1341 | PHY_VITESSE_INIT_REG4, MII_READ); | ||
1342 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | ||
1343 | return PHY_ERROR; | ||
1344 | phy_reserved = mii_rw(dev, np->phyaddr, | ||
1345 | PHY_VITESSE_INIT_REG3, MII_READ); | ||
1346 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | ||
1347 | phy_reserved |= PHY_VITESSE_INIT8; | ||
1348 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | ||
1349 | return PHY_ERROR; | ||
1350 | if (mii_rw(dev, np->phyaddr, | ||
1351 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) | ||
1352 | return PHY_ERROR; | ||
1353 | if (mii_rw(dev, np->phyaddr, | ||
1354 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) | ||
1355 | return PHY_ERROR; | ||
1356 | |||
1357 | return 0; | ||
1358 | } | ||
1359 | |||
1195 | static int phy_init(struct net_device *dev) | 1360 | static int phy_init(struct net_device *dev) |
1196 | { | 1361 | { |
1197 | struct fe_priv *np = get_nvpriv(dev); | 1362 | struct fe_priv *np = get_nvpriv(dev); |
1198 | u8 __iomem *base = get_hwbase(dev); | 1363 | u8 __iomem *base = get_hwbase(dev); |
1199 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; | 1364 | u32 phyinterface; |
1365 | u32 mii_status, mii_control, mii_control_1000, reg; | ||
1200 | 1366 | ||
1201 | /* phy errata for E3016 phy */ | 1367 | /* phy errata for E3016 phy */ |
1202 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | 1368 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
1203 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | 1369 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
1204 | reg &= ~PHY_MARVELL_E3016_INITMASK; | 1370 | reg &= ~PHY_MARVELL_E3016_INITMASK; |
1205 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | 1371 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { |
1206 | printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); | 1372 | netdev_info(dev, "%s: phy write to errata reg failed\n", |
1373 | pci_name(np->pci_dev)); | ||
1207 | return PHY_ERROR; | 1374 | return PHY_ERROR; |
1208 | } | 1375 | } |
1209 | } | 1376 | } |
1210 | if (np->phy_oui == PHY_OUI_REALTEK) { | 1377 | if (np->phy_oui == PHY_OUI_REALTEK) { |
1211 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && | 1378 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1212 | np->phy_rev == PHY_REV_REALTEK_8211B) { | 1379 | np->phy_rev == PHY_REV_REALTEK_8211B) { |
1213 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1380 | if (init_realtek_8211b(dev, np)) { |
1214 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1381 | netdev_info(dev, "%s: phy init failed\n", |
1215 | return PHY_ERROR; | 1382 | pci_name(np->pci_dev)); |
1216 | } | ||
1217 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | ||
1218 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1219 | return PHY_ERROR; | ||
1220 | } | ||
1221 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | ||
1222 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1223 | return PHY_ERROR; | ||
1224 | } | ||
1225 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | ||
1226 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1227 | return PHY_ERROR; | 1383 | return PHY_ERROR; |
1228 | } | 1384 | } |
1229 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | 1385 | } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1230 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1386 | np->phy_rev == PHY_REV_REALTEK_8211C) { |
1387 | if (init_realtek_8211c(dev, np)) { | ||
1388 | netdev_info(dev, "%s: phy init failed\n", | ||
1389 | pci_name(np->pci_dev)); | ||
1231 | return PHY_ERROR; | 1390 | return PHY_ERROR; |
1232 | } | 1391 | } |
1233 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | 1392 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1234 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1393 | if (init_realtek_8201(dev, np)) { |
1235 | return PHY_ERROR; | 1394 | netdev_info(dev, "%s: phy init failed\n", |
1236 | } | 1395 | pci_name(np->pci_dev)); |
1237 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | ||
1238 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1239 | return PHY_ERROR; | ||
1240 | } | ||
1241 | } | ||
1242 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && | ||
1243 | np->phy_rev == PHY_REV_REALTEK_8211C) { | ||
1244 | u32 powerstate = readl(base + NvRegPowerState2); | ||
1245 | |||
1246 | /* need to perform hw phy reset */ | ||
1247 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | ||
1248 | writel(powerstate, base + NvRegPowerState2); | ||
1249 | msleep(25); | ||
1250 | |||
1251 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | ||
1252 | writel(powerstate, base + NvRegPowerState2); | ||
1253 | msleep(25); | ||
1254 | |||
1255 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | ||
1256 | reg |= PHY_REALTEK_INIT9; | ||
1257 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { | ||
1258 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1259 | return PHY_ERROR; | ||
1260 | } | ||
1261 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { | ||
1262 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1263 | return PHY_ERROR; | ||
1264 | } | ||
1265 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | ||
1266 | if (!(reg & PHY_REALTEK_INIT11)) { | ||
1267 | reg |= PHY_REALTEK_INIT11; | ||
1268 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { | ||
1269 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1270 | return PHY_ERROR; | ||
1271 | } | ||
1272 | } | ||
1273 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | ||
1274 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1275 | return PHY_ERROR; | 1396 | return PHY_ERROR; |
1276 | } | 1397 | } |
1277 | } | 1398 | } |
1278 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { | ||
1279 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { | ||
1280 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | ||
1281 | phy_reserved |= PHY_REALTEK_INIT7; | ||
1282 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | ||
1283 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1284 | return PHY_ERROR; | ||
1285 | } | ||
1286 | } | ||
1287 | } | ||
1288 | } | 1399 | } |
1289 | 1400 | ||
1290 | /* set advertise register */ | 1401 | /* set advertise register */ |
1291 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | 1402 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
1292 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); | 1403 | reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
1404 | ADVERTISE_100HALF | ADVERTISE_100FULL | | ||
1405 | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | ||
1293 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { | 1406 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1294 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); | 1407 | netdev_info(dev, "%s: phy write to advertise failed\n", |
1408 | pci_name(np->pci_dev)); | ||
1295 | return PHY_ERROR; | 1409 | return PHY_ERROR; |
1296 | } | 1410 | } |
1297 | 1411 | ||
@@ -1302,7 +1416,8 @@ static int phy_init(struct net_device *dev) | |||
1302 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | 1416 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
1303 | if (mii_status & PHY_GIGABIT) { | 1417 | if (mii_status & PHY_GIGABIT) { |
1304 | np->gigabit = PHY_GIGABIT; | 1418 | np->gigabit = PHY_GIGABIT; |
1305 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | 1419 | mii_control_1000 = mii_rw(dev, np->phyaddr, |
1420 | MII_CTRL1000, MII_READ); | ||
1306 | mii_control_1000 &= ~ADVERTISE_1000HALF; | 1421 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1307 | if (phyinterface & PHY_RGMII) | 1422 | if (phyinterface & PHY_RGMII) |
1308 | mii_control_1000 |= ADVERTISE_1000FULL; | 1423 | mii_control_1000 |= ADVERTISE_1000FULL; |
@@ -1310,11 +1425,11 @@ static int phy_init(struct net_device *dev) | |||
1310 | mii_control_1000 &= ~ADVERTISE_1000FULL; | 1425 | mii_control_1000 &= ~ADVERTISE_1000FULL; |
1311 | 1426 | ||
1312 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { | 1427 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1313 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1428 | netdev_info(dev, "%s: phy init failed\n", |
1429 | pci_name(np->pci_dev)); | ||
1314 | return PHY_ERROR; | 1430 | return PHY_ERROR; |
1315 | } | 1431 | } |
1316 | } | 1432 | } else |
1317 | else | ||
1318 | np->gigabit = 0; | 1433 | np->gigabit = 0; |
1319 | 1434 | ||
1320 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 1435 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
@@ -1326,7 +1441,8 @@ static int phy_init(struct net_device *dev) | |||
1326 | /* start autoneg since we already performed hw reset above */ | 1441 | /* start autoneg since we already performed hw reset above */ |
1327 | mii_control |= BMCR_ANRESTART; | 1442 | mii_control |= BMCR_ANRESTART; |
1328 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | 1443 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
1329 | printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev)); | 1444 | netdev_info(dev, "%s: phy init failed\n", |
1445 | pci_name(np->pci_dev)); | ||
1330 | return PHY_ERROR; | 1446 | return PHY_ERROR; |
1331 | } | 1447 | } |
1332 | } else { | 1448 | } else { |
@@ -1334,164 +1450,41 @@ static int phy_init(struct net_device *dev) | |||
1334 | * (certain phys need bmcr to be setup with reset) | 1450 | * (certain phys need bmcr to be setup with reset) |
1335 | */ | 1451 | */ |
1336 | if (phy_reset(dev, mii_control)) { | 1452 | if (phy_reset(dev, mii_control)) { |
1337 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); | 1453 | netdev_info(dev, "%s: phy reset failed\n", |
1454 | pci_name(np->pci_dev)); | ||
1338 | return PHY_ERROR; | 1455 | return PHY_ERROR; |
1339 | } | 1456 | } |
1340 | } | 1457 | } |
1341 | 1458 | ||
1342 | /* phy vendor specific configuration */ | 1459 | /* phy vendor specific configuration */ |
1343 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { | 1460 | if ((np->phy_oui == PHY_OUI_CICADA)) { |
1344 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | 1461 | if (init_cicada(dev, np, phyinterface)) { |
1345 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); | 1462 | netdev_info(dev, "%s: phy init failed\n", |
1346 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | 1463 | pci_name(np->pci_dev)); |
1347 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { | ||
1348 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1349 | return PHY_ERROR; | 1464 | return PHY_ERROR; |
1350 | } | 1465 | } |
1351 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | 1466 | } else if (np->phy_oui == PHY_OUI_VITESSE) { |
1352 | phy_reserved |= PHY_CICADA_INIT5; | 1467 | if (init_vitesse(dev, np)) { |
1353 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { | 1468 | netdev_info(dev, "%s: phy init failed\n", |
1354 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1469 | pci_name(np->pci_dev)); |
1355 | return PHY_ERROR; | 1470 | return PHY_ERROR; |
1356 | } | 1471 | } |
1357 | } | 1472 | } else if (np->phy_oui == PHY_OUI_REALTEK) { |
1358 | if (np->phy_oui == PHY_OUI_CICADA) { | ||
1359 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | ||
1360 | phy_reserved |= PHY_CICADA_INIT6; | ||
1361 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { | ||
1362 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1363 | return PHY_ERROR; | ||
1364 | } | ||
1365 | } | ||
1366 | if (np->phy_oui == PHY_OUI_VITESSE) { | ||
1367 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { | ||
1368 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1369 | return PHY_ERROR; | ||
1370 | } | ||
1371 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { | ||
1372 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1373 | return PHY_ERROR; | ||
1374 | } | ||
1375 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | ||
1376 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | ||
1377 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1378 | return PHY_ERROR; | ||
1379 | } | ||
1380 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | ||
1381 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | ||
1382 | phy_reserved |= PHY_VITESSE_INIT3; | ||
1383 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | ||
1384 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1385 | return PHY_ERROR; | ||
1386 | } | ||
1387 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { | ||
1388 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1389 | return PHY_ERROR; | ||
1390 | } | ||
1391 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { | ||
1392 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1393 | return PHY_ERROR; | ||
1394 | } | ||
1395 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | ||
1396 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | ||
1397 | phy_reserved |= PHY_VITESSE_INIT3; | ||
1398 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | ||
1399 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1400 | return PHY_ERROR; | ||
1401 | } | ||
1402 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | ||
1403 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | ||
1404 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1405 | return PHY_ERROR; | ||
1406 | } | ||
1407 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { | ||
1408 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1409 | return PHY_ERROR; | ||
1410 | } | ||
1411 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { | ||
1412 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1413 | return PHY_ERROR; | ||
1414 | } | ||
1415 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | ||
1416 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | ||
1417 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1418 | return PHY_ERROR; | ||
1419 | } | ||
1420 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | ||
1421 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | ||
1422 | phy_reserved |= PHY_VITESSE_INIT8; | ||
1423 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | ||
1424 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1425 | return PHY_ERROR; | ||
1426 | } | ||
1427 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { | ||
1428 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1429 | return PHY_ERROR; | ||
1430 | } | ||
1431 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { | ||
1432 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1433 | return PHY_ERROR; | ||
1434 | } | ||
1435 | } | ||
1436 | if (np->phy_oui == PHY_OUI_REALTEK) { | ||
1437 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && | 1473 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1438 | np->phy_rev == PHY_REV_REALTEK_8211B) { | 1474 | np->phy_rev == PHY_REV_REALTEK_8211B) { |
1439 | /* reset could have cleared these out, set them back */ | 1475 | /* reset could have cleared these out, set them back */ |
1440 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1476 | if (init_realtek_8211b(dev, np)) { |
1441 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1477 | netdev_info(dev, "%s: phy init failed\n", |
1442 | return PHY_ERROR; | 1478 | pci_name(np->pci_dev)); |
1443 | } | ||
1444 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | ||
1445 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1446 | return PHY_ERROR; | ||
1447 | } | ||
1448 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | ||
1449 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1450 | return PHY_ERROR; | ||
1451 | } | ||
1452 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | ||
1453 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1454 | return PHY_ERROR; | 1479 | return PHY_ERROR; |
1455 | } | 1480 | } |
1456 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | 1481 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1457 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | 1482 | if (init_realtek_8201(dev, np) || |
1483 | init_realtek_8201_cross(dev, np)) { | ||
1484 | netdev_info(dev, "%s: phy init failed\n", | ||
1485 | pci_name(np->pci_dev)); | ||
1458 | return PHY_ERROR; | 1486 | return PHY_ERROR; |
1459 | } | 1487 | } |
1460 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | ||
1461 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1462 | return PHY_ERROR; | ||
1463 | } | ||
1464 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | ||
1465 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1466 | return PHY_ERROR; | ||
1467 | } | ||
1468 | } | ||
1469 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { | ||
1470 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { | ||
1471 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | ||
1472 | phy_reserved |= PHY_REALTEK_INIT7; | ||
1473 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | ||
1474 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1475 | return PHY_ERROR; | ||
1476 | } | ||
1477 | } | ||
1478 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | ||
1479 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | ||
1480 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1481 | return PHY_ERROR; | ||
1482 | } | ||
1483 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | ||
1484 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | ||
1485 | phy_reserved |= PHY_REALTEK_INIT3; | ||
1486 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { | ||
1487 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1488 | return PHY_ERROR; | ||
1489 | } | ||
1490 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | ||
1491 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | ||
1492 | return PHY_ERROR; | ||
1493 | } | ||
1494 | } | ||
1495 | } | 1488 | } |
1496 | } | 1489 | } |
1497 | 1490 | ||
@@ -1501,12 +1494,10 @@ static int phy_init(struct net_device *dev) | |||
1501 | /* restart auto negotiation, power down phy */ | 1494 | /* restart auto negotiation, power down phy */ |
1502 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 1495 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1503 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | 1496 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
1504 | if (phy_power_down) { | 1497 | if (phy_power_down) |
1505 | mii_control |= BMCR_PDOWN; | 1498 | mii_control |= BMCR_PDOWN; |
1506 | } | 1499 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) |
1507 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | ||
1508 | return PHY_ERROR; | 1500 | return PHY_ERROR; |
1509 | } | ||
1510 | 1501 | ||
1511 | return 0; | 1502 | return 0; |
1512 | } | 1503 | } |
@@ -1517,7 +1508,6 @@ static void nv_start_rx(struct net_device *dev) | |||
1517 | u8 __iomem *base = get_hwbase(dev); | 1508 | u8 __iomem *base = get_hwbase(dev); |
1518 | u32 rx_ctrl = readl(base + NvRegReceiverControl); | 1509 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1519 | 1510 | ||
1520 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | ||
1521 | /* Already running? Stop it. */ | 1511 | /* Already running? Stop it. */ |
1522 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { | 1512 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1523 | rx_ctrl &= ~NVREG_RCVCTL_START; | 1513 | rx_ctrl &= ~NVREG_RCVCTL_START; |
@@ -1526,12 +1516,10 @@ static void nv_start_rx(struct net_device *dev) | |||
1526 | } | 1516 | } |
1527 | writel(np->linkspeed, base + NvRegLinkSpeed); | 1517 | writel(np->linkspeed, base + NvRegLinkSpeed); |
1528 | pci_push(base); | 1518 | pci_push(base); |
1529 | rx_ctrl |= NVREG_RCVCTL_START; | 1519 | rx_ctrl |= NVREG_RCVCTL_START; |
1530 | if (np->mac_in_use) | 1520 | if (np->mac_in_use) |
1531 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; | 1521 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1532 | writel(rx_ctrl, base + NvRegReceiverControl); | 1522 | writel(rx_ctrl, base + NvRegReceiverControl); |
1533 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", | ||
1534 | dev->name, np->duplex, np->linkspeed); | ||
1535 | pci_push(base); | 1523 | pci_push(base); |
1536 | } | 1524 | } |
1537 | 1525 | ||
@@ -1541,15 +1529,15 @@ static void nv_stop_rx(struct net_device *dev) | |||
1541 | u8 __iomem *base = get_hwbase(dev); | 1529 | u8 __iomem *base = get_hwbase(dev); |
1542 | u32 rx_ctrl = readl(base + NvRegReceiverControl); | 1530 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1543 | 1531 | ||
1544 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | ||
1545 | if (!np->mac_in_use) | 1532 | if (!np->mac_in_use) |
1546 | rx_ctrl &= ~NVREG_RCVCTL_START; | 1533 | rx_ctrl &= ~NVREG_RCVCTL_START; |
1547 | else | 1534 | else |
1548 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | 1535 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; |
1549 | writel(rx_ctrl, base + NvRegReceiverControl); | 1536 | writel(rx_ctrl, base + NvRegReceiverControl); |
1550 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, | 1537 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1551 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | 1538 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) |
1552 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | 1539 | netdev_info(dev, "%s: ReceiverStatus remained busy\n", |
1540 | __func__); | ||
1553 | 1541 | ||
1554 | udelay(NV_RXSTOP_DELAY2); | 1542 | udelay(NV_RXSTOP_DELAY2); |
1555 | if (!np->mac_in_use) | 1543 | if (!np->mac_in_use) |
@@ -1562,7 +1550,6 @@ static void nv_start_tx(struct net_device *dev) | |||
1562 | u8 __iomem *base = get_hwbase(dev); | 1550 | u8 __iomem *base = get_hwbase(dev); |
1563 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); | 1551 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1564 | 1552 | ||
1565 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | ||
1566 | tx_ctrl |= NVREG_XMITCTL_START; | 1553 | tx_ctrl |= NVREG_XMITCTL_START; |
1567 | if (np->mac_in_use) | 1554 | if (np->mac_in_use) |
1568 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | 1555 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; |
@@ -1576,15 +1563,15 @@ static void nv_stop_tx(struct net_device *dev) | |||
1576 | u8 __iomem *base = get_hwbase(dev); | 1563 | u8 __iomem *base = get_hwbase(dev); |
1577 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); | 1564 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1578 | 1565 | ||
1579 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | ||
1580 | if (!np->mac_in_use) | 1566 | if (!np->mac_in_use) |
1581 | tx_ctrl &= ~NVREG_XMITCTL_START; | 1567 | tx_ctrl &= ~NVREG_XMITCTL_START; |
1582 | else | 1568 | else |
1583 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | 1569 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; |
1584 | writel(tx_ctrl, base + NvRegTransmitterControl); | 1570 | writel(tx_ctrl, base + NvRegTransmitterControl); |
1585 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, | 1571 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1586 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | 1572 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) |
1587 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | 1573 | netdev_info(dev, "%s: TransmitterStatus remained busy\n", |
1574 | __func__); | ||
1588 | 1575 | ||
1589 | udelay(NV_TXSTOP_DELAY2); | 1576 | udelay(NV_TXSTOP_DELAY2); |
1590 | if (!np->mac_in_use) | 1577 | if (!np->mac_in_use) |
@@ -1609,7 +1596,6 @@ static void nv_txrx_reset(struct net_device *dev) | |||
1609 | struct fe_priv *np = netdev_priv(dev); | 1596 | struct fe_priv *np = netdev_priv(dev); |
1610 | u8 __iomem *base = get_hwbase(dev); | 1597 | u8 __iomem *base = get_hwbase(dev); |
1611 | 1598 | ||
1612 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | ||
1613 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); | 1599 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1614 | pci_push(base); | 1600 | pci_push(base); |
1615 | udelay(NV_TXRX_RESET_DELAY); | 1601 | udelay(NV_TXRX_RESET_DELAY); |
@@ -1623,8 +1609,6 @@ static void nv_mac_reset(struct net_device *dev) | |||
1623 | u8 __iomem *base = get_hwbase(dev); | 1609 | u8 __iomem *base = get_hwbase(dev); |
1624 | u32 temp1, temp2, temp3; | 1610 | u32 temp1, temp2, temp3; |
1625 | 1611 | ||
1626 | dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); | ||
1627 | |||
1628 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); | 1612 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1629 | pci_push(base); | 1613 | pci_push(base); |
1630 | 1614 | ||
@@ -1745,7 +1729,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev) | |||
1745 | static int nv_alloc_rx(struct net_device *dev) | 1729 | static int nv_alloc_rx(struct net_device *dev) |
1746 | { | 1730 | { |
1747 | struct fe_priv *np = netdev_priv(dev); | 1731 | struct fe_priv *np = netdev_priv(dev); |
1748 | struct ring_desc* less_rx; | 1732 | struct ring_desc *less_rx; |
1749 | 1733 | ||
1750 | less_rx = np->get_rx.orig; | 1734 | less_rx = np->get_rx.orig; |
1751 | if (less_rx-- == np->first_rx.orig) | 1735 | if (less_rx-- == np->first_rx.orig) |
@@ -1767,9 +1751,8 @@ static int nv_alloc_rx(struct net_device *dev) | |||
1767 | np->put_rx.orig = np->first_rx.orig; | 1751 | np->put_rx.orig = np->first_rx.orig; |
1768 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) | 1752 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
1769 | np->put_rx_ctx = np->first_rx_ctx; | 1753 | np->put_rx_ctx = np->first_rx_ctx; |
1770 | } else { | 1754 | } else |
1771 | return 1; | 1755 | return 1; |
1772 | } | ||
1773 | } | 1756 | } |
1774 | return 0; | 1757 | return 0; |
1775 | } | 1758 | } |
@@ -1777,7 +1760,7 @@ static int nv_alloc_rx(struct net_device *dev) | |||
1777 | static int nv_alloc_rx_optimized(struct net_device *dev) | 1760 | static int nv_alloc_rx_optimized(struct net_device *dev) |
1778 | { | 1761 | { |
1779 | struct fe_priv *np = netdev_priv(dev); | 1762 | struct fe_priv *np = netdev_priv(dev); |
1780 | struct ring_desc_ex* less_rx; | 1763 | struct ring_desc_ex *less_rx; |
1781 | 1764 | ||
1782 | less_rx = np->get_rx.ex; | 1765 | less_rx = np->get_rx.ex; |
1783 | if (less_rx-- == np->first_rx.ex) | 1766 | if (less_rx-- == np->first_rx.ex) |
@@ -1800,9 +1783,8 @@ static int nv_alloc_rx_optimized(struct net_device *dev) | |||
1800 | np->put_rx.ex = np->first_rx.ex; | 1783 | np->put_rx.ex = np->first_rx.ex; |
1801 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) | 1784 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
1802 | np->put_rx_ctx = np->first_rx_ctx; | 1785 | np->put_rx_ctx = np->first_rx_ctx; |
1803 | } else { | 1786 | } else |
1804 | return 1; | 1787 | return 1; |
1805 | } | ||
1806 | } | 1788 | } |
1807 | return 0; | 1789 | return 0; |
1808 | } | 1790 | } |
@@ -2018,24 +2000,24 @@ static void nv_legacybackoff_reseed(struct net_device *dev) | |||
2018 | 2000 | ||
2019 | /* Known Good seed sets */ | 2001 | /* Known Good seed sets */ |
2020 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | 2002 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { |
2021 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | 2003 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2022 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | 2004 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, |
2023 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | 2005 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2024 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | 2006 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, |
2025 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | 2007 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, |
2026 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | 2008 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, |
2027 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | 2009 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, |
2028 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}}; | 2010 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} }; |
2029 | 2011 | ||
2030 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | 2012 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { |
2031 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | 2013 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2032 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | 2014 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, |
2033 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | 2015 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, |
2034 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | 2016 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2035 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | 2017 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2036 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | 2018 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, |
2037 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | 2019 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, |
2038 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}}; | 2020 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} }; |
2039 | 2021 | ||
2040 | static void nv_gear_backoff_reseed(struct net_device *dev) | 2022 | static void nv_gear_backoff_reseed(struct net_device *dev) |
2041 | { | 2023 | { |
@@ -2083,13 +2065,12 @@ static void nv_gear_backoff_reseed(struct net_device *dev) | |||
2083 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | 2065 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); |
2084 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | 2066 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; |
2085 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | 2067 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; |
2086 | writel(temp,base + NvRegBackOffControl); | 2068 | writel(temp, base + NvRegBackOffControl); |
2087 | 2069 | ||
2088 | /* Setup seeds for all gear LFSRs. */ | 2070 | /* Setup seeds for all gear LFSRs. */ |
2089 | get_random_bytes(&seedset, sizeof(seedset)); | 2071 | get_random_bytes(&seedset, sizeof(seedset)); |
2090 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | 2072 | seedset = seedset % BACKOFF_SEEDSET_ROWS; |
2091 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) | 2073 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) { |
2092 | { | ||
2093 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); | 2074 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); |
2094 | temp |= main_seedset[seedset][i-1] & 0x3ff; | 2075 | temp |= main_seedset[seedset][i-1] & 0x3ff; |
2095 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | 2076 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); |
@@ -2113,10 +2094,10 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
2113 | u32 size = skb_headlen(skb); | 2094 | u32 size = skb_headlen(skb); |
2114 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | 2095 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2115 | u32 empty_slots; | 2096 | u32 empty_slots; |
2116 | struct ring_desc* put_tx; | 2097 | struct ring_desc *put_tx; |
2117 | struct ring_desc* start_tx; | 2098 | struct ring_desc *start_tx; |
2118 | struct ring_desc* prev_tx; | 2099 | struct ring_desc *prev_tx; |
2119 | struct nv_skb_map* prev_tx_ctx; | 2100 | struct nv_skb_map *prev_tx_ctx; |
2120 | unsigned long flags; | 2101 | unsigned long flags; |
2121 | 2102 | ||
2122 | /* add fragments to entries count */ | 2103 | /* add fragments to entries count */ |
@@ -2204,18 +2185,6 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
2204 | 2185 | ||
2205 | spin_unlock_irqrestore(&np->lock, flags); | 2186 | spin_unlock_irqrestore(&np->lock, flags); |
2206 | 2187 | ||
2207 | dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n", | ||
2208 | dev->name, entries, tx_flags_extra); | ||
2209 | { | ||
2210 | int j; | ||
2211 | for (j=0; j<64; j++) { | ||
2212 | if ((j%16) == 0) | ||
2213 | dprintk("\n%03x:", j); | ||
2214 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | ||
2215 | } | ||
2216 | dprintk("\n"); | ||
2217 | } | ||
2218 | |||
2219 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | 2188 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
2220 | return NETDEV_TX_OK; | 2189 | return NETDEV_TX_OK; |
2221 | } | 2190 | } |
@@ -2233,11 +2202,11 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, | |||
2233 | u32 size = skb_headlen(skb); | 2202 | u32 size = skb_headlen(skb); |
2234 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | 2203 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2235 | u32 empty_slots; | 2204 | u32 empty_slots; |
2236 | struct ring_desc_ex* put_tx; | 2205 | struct ring_desc_ex *put_tx; |
2237 | struct ring_desc_ex* start_tx; | 2206 | struct ring_desc_ex *start_tx; |
2238 | struct ring_desc_ex* prev_tx; | 2207 | struct ring_desc_ex *prev_tx; |
2239 | struct nv_skb_map* prev_tx_ctx; | 2208 | struct nv_skb_map *prev_tx_ctx; |
2240 | struct nv_skb_map* start_tx_ctx; | 2209 | struct nv_skb_map *start_tx_ctx; |
2241 | unsigned long flags; | 2210 | unsigned long flags; |
2242 | 2211 | ||
2243 | /* add fragments to entries count */ | 2212 | /* add fragments to entries count */ |
@@ -2355,18 +2324,6 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, | |||
2355 | 2324 | ||
2356 | spin_unlock_irqrestore(&np->lock, flags); | 2325 | spin_unlock_irqrestore(&np->lock, flags); |
2357 | 2326 | ||
2358 | dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n", | ||
2359 | dev->name, entries, tx_flags_extra); | ||
2360 | { | ||
2361 | int j; | ||
2362 | for (j=0; j<64; j++) { | ||
2363 | if ((j%16) == 0) | ||
2364 | dprintk("\n%03x:", j); | ||
2365 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | ||
2366 | } | ||
2367 | dprintk("\n"); | ||
2368 | } | ||
2369 | |||
2370 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | 2327 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
2371 | return NETDEV_TX_OK; | 2328 | return NETDEV_TX_OK; |
2372 | } | 2329 | } |
@@ -2399,15 +2356,12 @@ static int nv_tx_done(struct net_device *dev, int limit) | |||
2399 | struct fe_priv *np = netdev_priv(dev); | 2356 | struct fe_priv *np = netdev_priv(dev); |
2400 | u32 flags; | 2357 | u32 flags; |
2401 | int tx_work = 0; | 2358 | int tx_work = 0; |
2402 | struct ring_desc* orig_get_tx = np->get_tx.orig; | 2359 | struct ring_desc *orig_get_tx = np->get_tx.orig; |
2403 | 2360 | ||
2404 | while ((np->get_tx.orig != np->put_tx.orig) && | 2361 | while ((np->get_tx.orig != np->put_tx.orig) && |
2405 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && | 2362 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && |
2406 | (tx_work < limit)) { | 2363 | (tx_work < limit)) { |
2407 | 2364 | ||
2408 | dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n", | ||
2409 | dev->name, flags); | ||
2410 | |||
2411 | nv_unmap_txskb(np, np->get_tx_ctx); | 2365 | nv_unmap_txskb(np, np->get_tx_ctx); |
2412 | 2366 | ||
2413 | if (np->desc_ver == DESC_VER_1) { | 2367 | if (np->desc_ver == DESC_VER_1) { |
@@ -2464,15 +2418,12 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit) | |||
2464 | struct fe_priv *np = netdev_priv(dev); | 2418 | struct fe_priv *np = netdev_priv(dev); |
2465 | u32 flags; | 2419 | u32 flags; |
2466 | int tx_work = 0; | 2420 | int tx_work = 0; |
2467 | struct ring_desc_ex* orig_get_tx = np->get_tx.ex; | 2421 | struct ring_desc_ex *orig_get_tx = np->get_tx.ex; |
2468 | 2422 | ||
2469 | while ((np->get_tx.ex != np->put_tx.ex) && | 2423 | while ((np->get_tx.ex != np->put_tx.ex) && |
2470 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && | 2424 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && |
2471 | (tx_work < limit)) { | 2425 | (tx_work < limit)) { |
2472 | 2426 | ||
2473 | dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n", | ||
2474 | dev->name, flags); | ||
2475 | |||
2476 | nv_unmap_txskb(np, np->get_tx_ctx); | 2427 | nv_unmap_txskb(np, np->get_tx_ctx); |
2477 | 2428 | ||
2478 | if (flags & NV_TX2_LASTPACKET) { | 2429 | if (flags & NV_TX2_LASTPACKET) { |
@@ -2491,9 +2442,8 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit) | |||
2491 | np->get_tx_ctx->skb = NULL; | 2442 | np->get_tx_ctx->skb = NULL; |
2492 | tx_work++; | 2443 | tx_work++; |
2493 | 2444 | ||
2494 | if (np->tx_limit) { | 2445 | if (np->tx_limit) |
2495 | nv_tx_flip_ownership(dev); | 2446 | nv_tx_flip_ownership(dev); |
2496 | } | ||
2497 | } | 2447 | } |
2498 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) | 2448 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
2499 | np->get_tx.ex = np->first_tx.ex; | 2449 | np->get_tx.ex = np->first_tx.ex; |
@@ -2518,57 +2468,56 @@ static void nv_tx_timeout(struct net_device *dev) | |||
2518 | u32 status; | 2468 | u32 status; |
2519 | union ring_type put_tx; | 2469 | union ring_type put_tx; |
2520 | int saved_tx_limit; | 2470 | int saved_tx_limit; |
2471 | int i; | ||
2521 | 2472 | ||
2522 | if (np->msi_flags & NV_MSI_X_ENABLED) | 2473 | if (np->msi_flags & NV_MSI_X_ENABLED) |
2523 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | 2474 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
2524 | else | 2475 | else |
2525 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | 2476 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
2526 | 2477 | ||
2527 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); | 2478 | netdev_info(dev, "Got tx_timeout. irq: %08x\n", status); |
2528 | 2479 | ||
2529 | { | 2480 | netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); |
2530 | int i; | 2481 | netdev_info(dev, "Dumping tx registers\n"); |
2531 | 2482 | for (i = 0; i <= np->register_size; i += 32) { | |
2532 | printk(KERN_INFO "%s: Ring at %lx\n", | 2483 | netdev_info(dev, |
2533 | dev->name, (unsigned long)np->ring_addr); | 2484 | "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
2534 | printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); | 2485 | i, |
2535 | for (i=0;i<=np->register_size;i+= 32) { | 2486 | readl(base + i + 0), readl(base + i + 4), |
2536 | printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", | 2487 | readl(base + i + 8), readl(base + i + 12), |
2537 | i, | 2488 | readl(base + i + 16), readl(base + i + 20), |
2538 | readl(base + i + 0), readl(base + i + 4), | 2489 | readl(base + i + 24), readl(base + i + 28)); |
2539 | readl(base + i + 8), readl(base + i + 12), | 2490 | } |
2540 | readl(base + i + 16), readl(base + i + 20), | 2491 | netdev_info(dev, "Dumping tx ring\n"); |
2541 | readl(base + i + 24), readl(base + i + 28)); | 2492 | for (i = 0; i < np->tx_ring_size; i += 4) { |
2542 | } | 2493 | if (!nv_optimized(np)) { |
2543 | printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); | 2494 | netdev_info(dev, |
2544 | for (i=0;i<np->tx_ring_size;i+= 4) { | 2495 | "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
2545 | if (!nv_optimized(np)) { | 2496 | i, |
2546 | printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", | 2497 | le32_to_cpu(np->tx_ring.orig[i].buf), |
2547 | i, | 2498 | le32_to_cpu(np->tx_ring.orig[i].flaglen), |
2548 | le32_to_cpu(np->tx_ring.orig[i].buf), | 2499 | le32_to_cpu(np->tx_ring.orig[i+1].buf), |
2549 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | 2500 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), |
2550 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | 2501 | le32_to_cpu(np->tx_ring.orig[i+2].buf), |
2551 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | 2502 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), |
2552 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | 2503 | le32_to_cpu(np->tx_ring.orig[i+3].buf), |
2553 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | 2504 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); |
2554 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | 2505 | } else { |
2555 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | 2506 | netdev_info(dev, |
2556 | } else { | 2507 | "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
2557 | printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | 2508 | i, |
2558 | i, | 2509 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
2559 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), | 2510 | le32_to_cpu(np->tx_ring.ex[i].buflow), |
2560 | le32_to_cpu(np->tx_ring.ex[i].buflow), | 2511 | le32_to_cpu(np->tx_ring.ex[i].flaglen), |
2561 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | 2512 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), |
2562 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | 2513 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), |
2563 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | 2514 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), |
2564 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | 2515 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), |
2565 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | 2516 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), |
2566 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | 2517 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), |
2567 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | 2518 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), |
2568 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | 2519 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), |
2569 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | 2520 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); |
2570 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | ||
2571 | } | ||
2572 | } | 2521 | } |
2573 | } | 2522 | } |
2574 | 2523 | ||
@@ -2616,15 +2565,13 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |||
2616 | int protolen; /* length as stored in the proto field */ | 2565 | int protolen; /* length as stored in the proto field */ |
2617 | 2566 | ||
2618 | /* 1) calculate len according to header */ | 2567 | /* 1) calculate len according to header */ |
2619 | if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { | 2568 | if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
2620 | protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); | 2569 | protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); |
2621 | hdrlen = VLAN_HLEN; | 2570 | hdrlen = VLAN_HLEN; |
2622 | } else { | 2571 | } else { |
2623 | protolen = ntohs( ((struct ethhdr *)packet)->h_proto); | 2572 | protolen = ntohs(((struct ethhdr *)packet)->h_proto); |
2624 | hdrlen = ETH_HLEN; | 2573 | hdrlen = ETH_HLEN; |
2625 | } | 2574 | } |
2626 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | ||
2627 | dev->name, datalen, protolen, hdrlen); | ||
2628 | if (protolen > ETH_DATA_LEN) | 2575 | if (protolen > ETH_DATA_LEN) |
2629 | return datalen; /* Value in proto field not a len, no checks possible */ | 2576 | return datalen; /* Value in proto field not a len, no checks possible */ |
2630 | 2577 | ||
@@ -2635,26 +2582,18 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |||
2635 | /* more data on wire than in 802 header, trim of | 2582 | /* more data on wire than in 802 header, trim of |
2636 | * additional data. | 2583 | * additional data. |
2637 | */ | 2584 | */ |
2638 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | ||
2639 | dev->name, protolen); | ||
2640 | return protolen; | 2585 | return protolen; |
2641 | } else { | 2586 | } else { |
2642 | /* less data on wire than mentioned in header. | 2587 | /* less data on wire than mentioned in header. |
2643 | * Discard the packet. | 2588 | * Discard the packet. |
2644 | */ | 2589 | */ |
2645 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | ||
2646 | dev->name); | ||
2647 | return -1; | 2590 | return -1; |
2648 | } | 2591 | } |
2649 | } else { | 2592 | } else { |
2650 | /* short packet. Accept only if 802 values are also short */ | 2593 | /* short packet. Accept only if 802 values are also short */ |
2651 | if (protolen > ETH_ZLEN) { | 2594 | if (protolen > ETH_ZLEN) { |
2652 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | ||
2653 | dev->name); | ||
2654 | return -1; | 2595 | return -1; |
2655 | } | 2596 | } |
2656 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | ||
2657 | dev->name, datalen); | ||
2658 | return datalen; | 2597 | return datalen; |
2659 | } | 2598 | } |
2660 | } | 2599 | } |
@@ -2667,13 +2606,10 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
2667 | struct sk_buff *skb; | 2606 | struct sk_buff *skb; |
2668 | int len; | 2607 | int len; |
2669 | 2608 | ||
2670 | while((np->get_rx.orig != np->put_rx.orig) && | 2609 | while ((np->get_rx.orig != np->put_rx.orig) && |
2671 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && | 2610 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && |
2672 | (rx_work < limit)) { | 2611 | (rx_work < limit)) { |
2673 | 2612 | ||
2674 | dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n", | ||
2675 | dev->name, flags); | ||
2676 | |||
2677 | /* | 2613 | /* |
2678 | * the packet is for us - immediately tear down the pci mapping. | 2614 | * the packet is for us - immediately tear down the pci mapping. |
2679 | * TODO: check if a prefetch of the first cacheline improves | 2615 | * TODO: check if a prefetch of the first cacheline improves |
@@ -2685,16 +2621,6 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
2685 | skb = np->get_rx_ctx->skb; | 2621 | skb = np->get_rx_ctx->skb; |
2686 | np->get_rx_ctx->skb = NULL; | 2622 | np->get_rx_ctx->skb = NULL; |
2687 | 2623 | ||
2688 | { | ||
2689 | int j; | ||
2690 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); | ||
2691 | for (j=0; j<64; j++) { | ||
2692 | if ((j%16) == 0) | ||
2693 | dprintk("\n%03x:", j); | ||
2694 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | ||
2695 | } | ||
2696 | dprintk("\n"); | ||
2697 | } | ||
2698 | /* look at what we actually got: */ | 2624 | /* look at what we actually got: */ |
2699 | if (np->desc_ver == DESC_VER_1) { | 2625 | if (np->desc_ver == DESC_VER_1) { |
2700 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { | 2626 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
@@ -2710,9 +2636,8 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
2710 | } | 2636 | } |
2711 | /* framing errors are soft errors */ | 2637 | /* framing errors are soft errors */ |
2712 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { | 2638 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
2713 | if (flags & NV_RX_SUBSTRACT1) { | 2639 | if (flags & NV_RX_SUBSTRACT1) |
2714 | len--; | 2640 | len--; |
2715 | } | ||
2716 | } | 2641 | } |
2717 | /* the rest are hard errors */ | 2642 | /* the rest are hard errors */ |
2718 | else { | 2643 | else { |
@@ -2745,9 +2670,8 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
2745 | } | 2670 | } |
2746 | /* framing errors are soft errors */ | 2671 | /* framing errors are soft errors */ |
2747 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { | 2672 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
2748 | if (flags & NV_RX2_SUBSTRACT1) { | 2673 | if (flags & NV_RX2_SUBSTRACT1) |
2749 | len--; | 2674 | len--; |
2750 | } | ||
2751 | } | 2675 | } |
2752 | /* the rest are hard errors */ | 2676 | /* the rest are hard errors */ |
2753 | else { | 2677 | else { |
@@ -2771,8 +2695,6 @@ static int nv_rx_process(struct net_device *dev, int limit) | |||
2771 | /* got a valid packet - forward it to the network core */ | 2695 | /* got a valid packet - forward it to the network core */ |
2772 | skb_put(skb, len); | 2696 | skb_put(skb, len); |
2773 | skb->protocol = eth_type_trans(skb, dev); | 2697 | skb->protocol = eth_type_trans(skb, dev); |
2774 | dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n", | ||
2775 | dev->name, len, skb->protocol); | ||
2776 | napi_gro_receive(&np->napi, skb); | 2698 | napi_gro_receive(&np->napi, skb); |
2777 | dev->stats.rx_packets++; | 2699 | dev->stats.rx_packets++; |
2778 | dev->stats.rx_bytes += len; | 2700 | dev->stats.rx_bytes += len; |
@@ -2797,13 +2719,10 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit) | |||
2797 | struct sk_buff *skb; | 2719 | struct sk_buff *skb; |
2798 | int len; | 2720 | int len; |
2799 | 2721 | ||
2800 | while((np->get_rx.ex != np->put_rx.ex) && | 2722 | while ((np->get_rx.ex != np->put_rx.ex) && |
2801 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && | 2723 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && |
2802 | (rx_work < limit)) { | 2724 | (rx_work < limit)) { |
2803 | 2725 | ||
2804 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n", | ||
2805 | dev->name, flags); | ||
2806 | |||
2807 | /* | 2726 | /* |
2808 | * the packet is for us - immediately tear down the pci mapping. | 2727 | * the packet is for us - immediately tear down the pci mapping. |
2809 | * TODO: check if a prefetch of the first cacheline improves | 2728 | * TODO: check if a prefetch of the first cacheline improves |
@@ -2815,16 +2734,6 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit) | |||
2815 | skb = np->get_rx_ctx->skb; | 2734 | skb = np->get_rx_ctx->skb; |
2816 | np->get_rx_ctx->skb = NULL; | 2735 | np->get_rx_ctx->skb = NULL; |
2817 | 2736 | ||
2818 | { | ||
2819 | int j; | ||
2820 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); | ||
2821 | for (j=0; j<64; j++) { | ||
2822 | if ((j%16) == 0) | ||
2823 | dprintk("\n%03x:", j); | ||
2824 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | ||
2825 | } | ||
2826 | dprintk("\n"); | ||
2827 | } | ||
2828 | /* look at what we actually got: */ | 2737 | /* look at what we actually got: */ |
2829 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | 2738 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2830 | len = flags & LEN_MASK_V2; | 2739 | len = flags & LEN_MASK_V2; |
@@ -2838,9 +2747,8 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit) | |||
2838 | } | 2747 | } |
2839 | /* framing errors are soft errors */ | 2748 | /* framing errors are soft errors */ |
2840 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { | 2749 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
2841 | if (flags & NV_RX2_SUBSTRACT1) { | 2750 | if (flags & NV_RX2_SUBSTRACT1) |
2842 | len--; | 2751 | len--; |
2843 | } | ||
2844 | } | 2752 | } |
2845 | /* the rest are hard errors */ | 2753 | /* the rest are hard errors */ |
2846 | else { | 2754 | else { |
@@ -2858,9 +2766,6 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit) | |||
2858 | skb->protocol = eth_type_trans(skb, dev); | 2766 | skb->protocol = eth_type_trans(skb, dev); |
2859 | prefetch(skb->data); | 2767 | prefetch(skb->data); |
2860 | 2768 | ||
2861 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n", | ||
2862 | dev->name, len, skb->protocol); | ||
2863 | |||
2864 | if (likely(!np->vlangrp)) { | 2769 | if (likely(!np->vlangrp)) { |
2865 | napi_gro_receive(&np->napi, skb); | 2770 | napi_gro_receive(&np->napi, skb); |
2866 | } else { | 2771 | } else { |
@@ -2949,7 +2854,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu) | |||
2949 | /* reinit nic view of the rx queue */ | 2854 | /* reinit nic view of the rx queue */ |
2950 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | 2855 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
2951 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | 2856 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
2952 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | 2857 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
2953 | base + NvRegRingSizes); | 2858 | base + NvRegRingSizes); |
2954 | pci_push(base); | 2859 | pci_push(base); |
2955 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | 2860 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
@@ -2986,7 +2891,7 @@ static void nv_copy_mac_to_hw(struct net_device *dev) | |||
2986 | static int nv_set_mac_address(struct net_device *dev, void *addr) | 2891 | static int nv_set_mac_address(struct net_device *dev, void *addr) |
2987 | { | 2892 | { |
2988 | struct fe_priv *np = netdev_priv(dev); | 2893 | struct fe_priv *np = netdev_priv(dev); |
2989 | struct sockaddr *macaddr = (struct sockaddr*)addr; | 2894 | struct sockaddr *macaddr = (struct sockaddr *)addr; |
2990 | 2895 | ||
2991 | if (!is_valid_ether_addr(macaddr->sa_data)) | 2896 | if (!is_valid_ether_addr(macaddr->sa_data)) |
2992 | return -EADDRNOTAVAIL; | 2897 | return -EADDRNOTAVAIL; |
@@ -3076,8 +2981,6 @@ static void nv_set_multicast(struct net_device *dev) | |||
3076 | writel(mask[0], base + NvRegMulticastMaskA); | 2981 | writel(mask[0], base + NvRegMulticastMaskA); |
3077 | writel(mask[1], base + NvRegMulticastMaskB); | 2982 | writel(mask[1], base + NvRegMulticastMaskB); |
3078 | writel(pff, base + NvRegPacketFilterFlags); | 2983 | writel(pff, base + NvRegPacketFilterFlags); |
3079 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", | ||
3080 | dev->name); | ||
3081 | nv_start_rx(dev); | 2984 | nv_start_rx(dev); |
3082 | spin_unlock_irq(&np->lock); | 2985 | spin_unlock_irq(&np->lock); |
3083 | } | 2986 | } |
@@ -3152,8 +3055,6 @@ static int nv_update_linkspeed(struct net_device *dev) | |||
3152 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | 3055 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
3153 | 3056 | ||
3154 | if (!(mii_status & BMSR_LSTATUS)) { | 3057 | if (!(mii_status & BMSR_LSTATUS)) { |
3155 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", | ||
3156 | dev->name); | ||
3157 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | 3058 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3158 | newdup = 0; | 3059 | newdup = 0; |
3159 | retval = 0; | 3060 | retval = 0; |
@@ -3161,8 +3062,6 @@ static int nv_update_linkspeed(struct net_device *dev) | |||
3161 | } | 3062 | } |
3162 | 3063 | ||
3163 | if (np->autoneg == 0) { | 3064 | if (np->autoneg == 0) { |
3164 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", | ||
3165 | dev->name, np->fixed_mode); | ||
3166 | if (np->fixed_mode & LPA_100FULL) { | 3065 | if (np->fixed_mode & LPA_100FULL) { |
3167 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | 3066 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3168 | newdup = 1; | 3067 | newdup = 1; |
@@ -3185,14 +3084,11 @@ static int nv_update_linkspeed(struct net_device *dev) | |||
3185 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | 3084 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3186 | newdup = 0; | 3085 | newdup = 0; |
3187 | retval = 0; | 3086 | retval = 0; |
3188 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); | ||
3189 | goto set_speed; | 3087 | goto set_speed; |
3190 | } | 3088 | } |
3191 | 3089 | ||
3192 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | 3090 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3193 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | 3091 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
3194 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", | ||
3195 | dev->name, adv, lpa); | ||
3196 | 3092 | ||
3197 | retval = 1; | 3093 | retval = 1; |
3198 | if (np->gigabit == PHY_GIGABIT) { | 3094 | if (np->gigabit == PHY_GIGABIT) { |
@@ -3201,8 +3097,6 @@ static int nv_update_linkspeed(struct net_device *dev) | |||
3201 | 3097 | ||
3202 | if ((control_1000 & ADVERTISE_1000FULL) && | 3098 | if ((control_1000 & ADVERTISE_1000FULL) && |
3203 | (status_1000 & LPA_1000FULL)) { | 3099 | (status_1000 & LPA_1000FULL)) { |
3204 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", | ||
3205 | dev->name); | ||
3206 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; | 3100 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
3207 | newdup = 1; | 3101 | newdup = 1; |
3208 | goto set_speed; | 3102 | goto set_speed; |
@@ -3224,7 +3118,6 @@ static int nv_update_linkspeed(struct net_device *dev) | |||
3224 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | 3118 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3225 | newdup = 0; | 3119 | newdup = 0; |
3226 | } else { | 3120 | } else { |
3227 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa); | ||
3228 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | 3121 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3229 | newdup = 0; | 3122 | newdup = 0; |
3230 | } | 3123 | } |
@@ -3233,9 +3126,6 @@ set_speed: | |||
3233 | if (np->duplex == newdup && np->linkspeed == newls) | 3126 | if (np->duplex == newdup && np->linkspeed == newls) |
3234 | return retval; | 3127 | return retval; |
3235 | 3128 | ||
3236 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", | ||
3237 | dev->name, np->linkspeed, np->duplex, newls, newdup); | ||
3238 | |||
3239 | np->duplex = newdup; | 3129 | np->duplex = newdup; |
3240 | np->linkspeed = newls; | 3130 | np->linkspeed = newls; |
3241 | 3131 | ||
@@ -3302,7 +3192,7 @@ set_speed: | |||
3302 | } | 3192 | } |
3303 | writel(txreg, base + NvRegTxWatermark); | 3193 | writel(txreg, base + NvRegTxWatermark); |
3304 | 3194 | ||
3305 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), | 3195 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), |
3306 | base + NvRegMisc1); | 3196 | base + NvRegMisc1); |
3307 | pci_push(base); | 3197 | pci_push(base); |
3308 | writel(np->linkspeed, base + NvRegLinkSpeed); | 3198 | writel(np->linkspeed, base + NvRegLinkSpeed); |
@@ -3312,8 +3202,8 @@ set_speed: | |||
3312 | /* setup pause frame */ | 3202 | /* setup pause frame */ |
3313 | if (np->duplex != 0) { | 3203 | if (np->duplex != 0) { |
3314 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { | 3204 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
3315 | adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM); | 3205 | adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
3316 | lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); | 3206 | lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); |
3317 | 3207 | ||
3318 | switch (adv_pause) { | 3208 | switch (adv_pause) { |
3319 | case ADVERTISE_PAUSE_CAP: | 3209 | case ADVERTISE_PAUSE_CAP: |
@@ -3324,22 +3214,17 @@ set_speed: | |||
3324 | } | 3214 | } |
3325 | break; | 3215 | break; |
3326 | case ADVERTISE_PAUSE_ASYM: | 3216 | case ADVERTISE_PAUSE_ASYM: |
3327 | if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) | 3217 | if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM)) |
3328 | { | ||
3329 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | 3218 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
3330 | } | ||
3331 | break; | 3219 | break; |
3332 | case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM: | 3220 | case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM: |
3333 | if (lpa_pause & LPA_PAUSE_CAP) | 3221 | if (lpa_pause & LPA_PAUSE_CAP) { |
3334 | { | ||
3335 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | 3222 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3336 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | 3223 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
3337 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | 3224 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
3338 | } | 3225 | } |
3339 | if (lpa_pause == LPA_PAUSE_ASYM) | 3226 | if (lpa_pause == LPA_PAUSE_ASYM) |
3340 | { | ||
3341 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | 3227 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3342 | } | ||
3343 | break; | 3228 | break; |
3344 | } | 3229 | } |
3345 | } else { | 3230 | } else { |
@@ -3361,14 +3246,14 @@ static void nv_linkchange(struct net_device *dev) | |||
3361 | if (nv_update_linkspeed(dev)) { | 3246 | if (nv_update_linkspeed(dev)) { |
3362 | if (!netif_carrier_ok(dev)) { | 3247 | if (!netif_carrier_ok(dev)) { |
3363 | netif_carrier_on(dev); | 3248 | netif_carrier_on(dev); |
3364 | printk(KERN_INFO "%s: link up.\n", dev->name); | 3249 | netdev_info(dev, "link up\n"); |
3365 | nv_txrx_gate(dev, false); | 3250 | nv_txrx_gate(dev, false); |
3366 | nv_start_rx(dev); | 3251 | nv_start_rx(dev); |
3367 | } | 3252 | } |
3368 | } else { | 3253 | } else { |
3369 | if (netif_carrier_ok(dev)) { | 3254 | if (netif_carrier_ok(dev)) { |
3370 | netif_carrier_off(dev); | 3255 | netif_carrier_off(dev); |
3371 | printk(KERN_INFO "%s: link down.\n", dev->name); | 3256 | netdev_info(dev, "link down\n"); |
3372 | nv_txrx_gate(dev, true); | 3257 | nv_txrx_gate(dev, true); |
3373 | nv_stop_rx(dev); | 3258 | nv_stop_rx(dev); |
3374 | } | 3259 | } |
@@ -3382,11 +3267,9 @@ static void nv_link_irq(struct net_device *dev) | |||
3382 | 3267 | ||
3383 | miistat = readl(base + NvRegMIIStatus); | 3268 | miistat = readl(base + NvRegMIIStatus); |
3384 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); | 3269 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
3385 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); | ||
3386 | 3270 | ||
3387 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | 3271 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) |
3388 | nv_linkchange(dev); | 3272 | nv_linkchange(dev); |
3389 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); | ||
3390 | } | 3273 | } |
3391 | 3274 | ||
3392 | static void nv_msi_workaround(struct fe_priv *np) | 3275 | static void nv_msi_workaround(struct fe_priv *np) |
@@ -3437,8 +3320,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data) | |||
3437 | struct fe_priv *np = netdev_priv(dev); | 3320 | struct fe_priv *np = netdev_priv(dev); |
3438 | u8 __iomem *base = get_hwbase(dev); | 3321 | u8 __iomem *base = get_hwbase(dev); |
3439 | 3322 | ||
3440 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); | ||
3441 | |||
3442 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | 3323 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3443 | np->events = readl(base + NvRegIrqStatus); | 3324 | np->events = readl(base + NvRegIrqStatus); |
3444 | writel(np->events, base + NvRegIrqStatus); | 3325 | writel(np->events, base + NvRegIrqStatus); |
@@ -3446,7 +3327,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data) | |||
3446 | np->events = readl(base + NvRegMSIXIrqStatus); | 3327 | np->events = readl(base + NvRegMSIXIrqStatus); |
3447 | writel(np->events, base + NvRegMSIXIrqStatus); | 3328 | writel(np->events, base + NvRegMSIXIrqStatus); |
3448 | } | 3329 | } |
3449 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events); | ||
3450 | if (!(np->events & np->irqmask)) | 3330 | if (!(np->events & np->irqmask)) |
3451 | return IRQ_NONE; | 3331 | return IRQ_NONE; |
3452 | 3332 | ||
@@ -3460,8 +3340,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data) | |||
3460 | __napi_schedule(&np->napi); | 3340 | __napi_schedule(&np->napi); |
3461 | } | 3341 | } |
3462 | 3342 | ||
3463 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); | ||
3464 | |||
3465 | return IRQ_HANDLED; | 3343 | return IRQ_HANDLED; |
3466 | } | 3344 | } |
3467 | 3345 | ||
@@ -3476,8 +3354,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data) | |||
3476 | struct fe_priv *np = netdev_priv(dev); | 3354 | struct fe_priv *np = netdev_priv(dev); |
3477 | u8 __iomem *base = get_hwbase(dev); | 3355 | u8 __iomem *base = get_hwbase(dev); |
3478 | 3356 | ||
3479 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name); | ||
3480 | |||
3481 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | 3357 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3482 | np->events = readl(base + NvRegIrqStatus); | 3358 | np->events = readl(base + NvRegIrqStatus); |
3483 | writel(np->events, base + NvRegIrqStatus); | 3359 | writel(np->events, base + NvRegIrqStatus); |
@@ -3485,7 +3361,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data) | |||
3485 | np->events = readl(base + NvRegMSIXIrqStatus); | 3361 | np->events = readl(base + NvRegMSIXIrqStatus); |
3486 | writel(np->events, base + NvRegMSIXIrqStatus); | 3362 | writel(np->events, base + NvRegMSIXIrqStatus); |
3487 | } | 3363 | } |
3488 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events); | ||
3489 | if (!(np->events & np->irqmask)) | 3364 | if (!(np->events & np->irqmask)) |
3490 | return IRQ_NONE; | 3365 | return IRQ_NONE; |
3491 | 3366 | ||
@@ -3498,7 +3373,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data) | |||
3498 | writel(0, base + NvRegIrqMask); | 3373 | writel(0, base + NvRegIrqMask); |
3499 | __napi_schedule(&np->napi); | 3374 | __napi_schedule(&np->napi); |
3500 | } | 3375 | } |
3501 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name); | ||
3502 | 3376 | ||
3503 | return IRQ_HANDLED; | 3377 | return IRQ_HANDLED; |
3504 | } | 3378 | } |
@@ -3512,12 +3386,9 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data) | |||
3512 | int i; | 3386 | int i; |
3513 | unsigned long flags; | 3387 | unsigned long flags; |
3514 | 3388 | ||
3515 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); | 3389 | for (i = 0;; i++) { |
3516 | |||
3517 | for (i=0; ; i++) { | ||
3518 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; | 3390 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
3519 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | 3391 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); |
3520 | dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); | ||
3521 | if (!(events & np->irqmask)) | 3392 | if (!(events & np->irqmask)) |
3522 | break; | 3393 | break; |
3523 | 3394 | ||
@@ -3536,12 +3407,12 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data) | |||
3536 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | 3407 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
3537 | } | 3408 | } |
3538 | spin_unlock_irqrestore(&np->lock, flags); | 3409 | spin_unlock_irqrestore(&np->lock, flags); |
3539 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); | 3410 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3411 | __func__, i); | ||
3540 | break; | 3412 | break; |
3541 | } | 3413 | } |
3542 | 3414 | ||
3543 | } | 3415 | } |
3544 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); | ||
3545 | 3416 | ||
3546 | return IRQ_RETVAL(i); | 3417 | return IRQ_RETVAL(i); |
3547 | } | 3418 | } |
@@ -3553,7 +3424,7 @@ static int nv_napi_poll(struct napi_struct *napi, int budget) | |||
3553 | u8 __iomem *base = get_hwbase(dev); | 3424 | u8 __iomem *base = get_hwbase(dev); |
3554 | unsigned long flags; | 3425 | unsigned long flags; |
3555 | int retcode; | 3426 | int retcode; |
3556 | int rx_count, tx_work=0, rx_work=0; | 3427 | int rx_count, tx_work = 0, rx_work = 0; |
3557 | 3428 | ||
3558 | do { | 3429 | do { |
3559 | if (!nv_optimized(np)) { | 3430 | if (!nv_optimized(np)) { |
@@ -3626,12 +3497,9 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data) | |||
3626 | int i; | 3497 | int i; |
3627 | unsigned long flags; | 3498 | unsigned long flags; |
3628 | 3499 | ||
3629 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); | 3500 | for (i = 0;; i++) { |
3630 | |||
3631 | for (i=0; ; i++) { | ||
3632 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | 3501 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
3633 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | 3502 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
3634 | dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); | ||
3635 | if (!(events & np->irqmask)) | 3503 | if (!(events & np->irqmask)) |
3636 | break; | 3504 | break; |
3637 | 3505 | ||
@@ -3655,11 +3523,11 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data) | |||
3655 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | 3523 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
3656 | } | 3524 | } |
3657 | spin_unlock_irqrestore(&np->lock, flags); | 3525 | spin_unlock_irqrestore(&np->lock, flags); |
3658 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); | 3526 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3527 | __func__, i); | ||
3659 | break; | 3528 | break; |
3660 | } | 3529 | } |
3661 | } | 3530 | } |
3662 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); | ||
3663 | 3531 | ||
3664 | return IRQ_RETVAL(i); | 3532 | return IRQ_RETVAL(i); |
3665 | } | 3533 | } |
@@ -3673,12 +3541,9 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data) | |||
3673 | int i; | 3541 | int i; |
3674 | unsigned long flags; | 3542 | unsigned long flags; |
3675 | 3543 | ||
3676 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); | 3544 | for (i = 0;; i++) { |
3677 | |||
3678 | for (i=0; ; i++) { | ||
3679 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; | 3545 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
3680 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | 3546 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); |
3681 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | ||
3682 | if (!(events & np->irqmask)) | 3547 | if (!(events & np->irqmask)) |
3683 | break; | 3548 | break; |
3684 | 3549 | ||
@@ -3723,12 +3588,12 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data) | |||
3723 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | 3588 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
3724 | } | 3589 | } |
3725 | spin_unlock_irqrestore(&np->lock, flags); | 3590 | spin_unlock_irqrestore(&np->lock, flags); |
3726 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); | 3591 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3592 | __func__, i); | ||
3727 | break; | 3593 | break; |
3728 | } | 3594 | } |
3729 | 3595 | ||
3730 | } | 3596 | } |
3731 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); | ||
3732 | 3597 | ||
3733 | return IRQ_RETVAL(i); | 3598 | return IRQ_RETVAL(i); |
3734 | } | 3599 | } |
@@ -3740,8 +3605,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data) | |||
3740 | u8 __iomem *base = get_hwbase(dev); | 3605 | u8 __iomem *base = get_hwbase(dev); |
3741 | u32 events; | 3606 | u32 events; |
3742 | 3607 | ||
3743 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name); | ||
3744 | |||
3745 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | 3608 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3746 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | 3609 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
3747 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | 3610 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); |
@@ -3750,7 +3613,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data) | |||
3750 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | 3613 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); |
3751 | } | 3614 | } |
3752 | pci_push(base); | 3615 | pci_push(base); |
3753 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | ||
3754 | if (!(events & NVREG_IRQ_TIMER)) | 3616 | if (!(events & NVREG_IRQ_TIMER)) |
3755 | return IRQ_RETVAL(0); | 3617 | return IRQ_RETVAL(0); |
3756 | 3618 | ||
@@ -3760,8 +3622,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data) | |||
3760 | np->intr_test = 1; | 3622 | np->intr_test = 1; |
3761 | spin_unlock(&np->lock); | 3623 | spin_unlock(&np->lock); |
3762 | 3624 | ||
3763 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); | ||
3764 | |||
3765 | return IRQ_RETVAL(1); | 3625 | return IRQ_RETVAL(1); |
3766 | } | 3626 | } |
3767 | 3627 | ||
@@ -3776,17 +3636,15 @@ static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) | |||
3776 | * the remaining 8 interrupts. | 3636 | * the remaining 8 interrupts. |
3777 | */ | 3637 | */ |
3778 | for (i = 0; i < 8; i++) { | 3638 | for (i = 0; i < 8; i++) { |
3779 | if ((irqmask >> i) & 0x1) { | 3639 | if ((irqmask >> i) & 0x1) |
3780 | msixmap |= vector << (i << 2); | 3640 | msixmap |= vector << (i << 2); |
3781 | } | ||
3782 | } | 3641 | } |
3783 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | 3642 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); |
3784 | 3643 | ||
3785 | msixmap = 0; | 3644 | msixmap = 0; |
3786 | for (i = 0; i < 8; i++) { | 3645 | for (i = 0; i < 8; i++) { |
3787 | if ((irqmask >> (i + 8)) & 0x1) { | 3646 | if ((irqmask >> (i + 8)) & 0x1) |
3788 | msixmap |= vector << (i << 2); | 3647 | msixmap |= vector << (i << 2); |
3789 | } | ||
3790 | } | 3648 | } |
3791 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | 3649 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); |
3792 | } | 3650 | } |
@@ -3809,17 +3667,19 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3809 | } | 3667 | } |
3810 | 3668 | ||
3811 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | 3669 | if (np->msi_flags & NV_MSI_X_CAPABLE) { |
3812 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | 3670 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
3813 | np->msi_x_entry[i].entry = i; | 3671 | np->msi_x_entry[i].entry = i; |
3814 | } | 3672 | ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK)); |
3815 | if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { | 3673 | if (ret == 0) { |
3816 | np->msi_flags |= NV_MSI_X_ENABLED; | 3674 | np->msi_flags |= NV_MSI_X_ENABLED; |
3817 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { | 3675 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
3818 | /* Request irq for rx handling */ | 3676 | /* Request irq for rx handling */ |
3819 | sprintf(np->name_rx, "%s-rx", dev->name); | 3677 | sprintf(np->name_rx, "%s-rx", dev->name); |
3820 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, | 3678 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, |
3821 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { | 3679 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { |
3822 | printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); | 3680 | netdev_info(dev, |
3681 | "request_irq failed for rx %d\n", | ||
3682 | ret); | ||
3823 | pci_disable_msix(np->pci_dev); | 3683 | pci_disable_msix(np->pci_dev); |
3824 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3684 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3825 | goto out_err; | 3685 | goto out_err; |
@@ -3828,7 +3688,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3828 | sprintf(np->name_tx, "%s-tx", dev->name); | 3688 | sprintf(np->name_tx, "%s-tx", dev->name); |
3829 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, | 3689 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, |
3830 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { | 3690 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { |
3831 | printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); | 3691 | netdev_info(dev, |
3692 | "request_irq failed for tx %d\n", | ||
3693 | ret); | ||
3832 | pci_disable_msix(np->pci_dev); | 3694 | pci_disable_msix(np->pci_dev); |
3833 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3695 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3834 | goto out_free_rx; | 3696 | goto out_free_rx; |
@@ -3837,7 +3699,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3837 | sprintf(np->name_other, "%s-other", dev->name); | 3699 | sprintf(np->name_other, "%s-other", dev->name); |
3838 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, | 3700 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, |
3839 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { | 3701 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { |
3840 | printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); | 3702 | netdev_info(dev, |
3703 | "request_irq failed for link %d\n", | ||
3704 | ret); | ||
3841 | pci_disable_msix(np->pci_dev); | 3705 | pci_disable_msix(np->pci_dev); |
3842 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3706 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3843 | goto out_free_tx; | 3707 | goto out_free_tx; |
@@ -3851,7 +3715,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3851 | } else { | 3715 | } else { |
3852 | /* Request irq for all interrupts */ | 3716 | /* Request irq for all interrupts */ |
3853 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { | 3717 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
3854 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); | 3718 | netdev_info(dev, |
3719 | "request_irq failed %d\n", | ||
3720 | ret); | ||
3855 | pci_disable_msix(np->pci_dev); | 3721 | pci_disable_msix(np->pci_dev); |
3856 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3722 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3857 | goto out_err; | 3723 | goto out_err; |
@@ -3864,11 +3730,13 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3864 | } | 3730 | } |
3865 | } | 3731 | } |
3866 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | 3732 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
3867 | if ((ret = pci_enable_msi(np->pci_dev)) == 0) { | 3733 | ret = pci_enable_msi(np->pci_dev); |
3734 | if (ret == 0) { | ||
3868 | np->msi_flags |= NV_MSI_ENABLED; | 3735 | np->msi_flags |= NV_MSI_ENABLED; |
3869 | dev->irq = np->pci_dev->irq; | 3736 | dev->irq = np->pci_dev->irq; |
3870 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { | 3737 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
3871 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); | 3738 | netdev_info(dev, "request_irq failed %d\n", |
3739 | ret); | ||
3872 | pci_disable_msi(np->pci_dev); | 3740 | pci_disable_msi(np->pci_dev); |
3873 | np->msi_flags &= ~NV_MSI_ENABLED; | 3741 | np->msi_flags &= ~NV_MSI_ENABLED; |
3874 | dev->irq = np->pci_dev->irq; | 3742 | dev->irq = np->pci_dev->irq; |
@@ -3903,9 +3771,8 @@ static void nv_free_irq(struct net_device *dev) | |||
3903 | int i; | 3771 | int i; |
3904 | 3772 | ||
3905 | if (np->msi_flags & NV_MSI_X_ENABLED) { | 3773 | if (np->msi_flags & NV_MSI_X_ENABLED) { |
3906 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | 3774 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
3907 | free_irq(np->msi_x_entry[i].vector, dev); | 3775 | free_irq(np->msi_x_entry[i].vector, dev); |
3908 | } | ||
3909 | pci_disable_msix(np->pci_dev); | 3776 | pci_disable_msix(np->pci_dev); |
3910 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3777 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3911 | } else { | 3778 | } else { |
@@ -3954,7 +3821,7 @@ static void nv_do_nic_poll(unsigned long data) | |||
3954 | 3821 | ||
3955 | if (np->recover_error) { | 3822 | if (np->recover_error) { |
3956 | np->recover_error = 0; | 3823 | np->recover_error = 0; |
3957 | printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name); | 3824 | netdev_info(dev, "MAC in recoverable error state\n"); |
3958 | if (netif_running(dev)) { | 3825 | if (netif_running(dev)) { |
3959 | netif_tx_lock_bh(dev); | 3826 | netif_tx_lock_bh(dev); |
3960 | netif_addr_lock(dev); | 3827 | netif_addr_lock(dev); |
@@ -3975,7 +3842,7 @@ static void nv_do_nic_poll(unsigned long data) | |||
3975 | /* reinit nic view of the rx queue */ | 3842 | /* reinit nic view of the rx queue */ |
3976 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | 3843 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
3977 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | 3844 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
3978 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | 3845 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
3979 | base + NvRegRingSizes); | 3846 | base + NvRegRingSizes); |
3980 | pci_push(base); | 3847 | pci_push(base); |
3981 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | 3848 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
@@ -4082,6 +3949,7 @@ static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |||
4082 | writel(flags, base + NvRegWakeUpFlags); | 3949 | writel(flags, base + NvRegWakeUpFlags); |
4083 | spin_unlock_irq(&np->lock); | 3950 | spin_unlock_irq(&np->lock); |
4084 | } | 3951 | } |
3952 | device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled); | ||
4085 | return 0; | 3953 | return 0; |
4086 | } | 3954 | } |
4087 | 3955 | ||
@@ -4105,7 +3973,7 @@ static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
4105 | } | 3973 | } |
4106 | 3974 | ||
4107 | if (netif_carrier_ok(dev)) { | 3975 | if (netif_carrier_ok(dev)) { |
4108 | switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { | 3976 | switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
4109 | case NVREG_LINKSPEED_10: | 3977 | case NVREG_LINKSPEED_10: |
4110 | ecmd->speed = SPEED_10; | 3978 | ecmd->speed = SPEED_10; |
4111 | break; | 3979 | break; |
@@ -4250,14 +4118,14 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
4250 | } | 4118 | } |
4251 | 4119 | ||
4252 | if (netif_running(dev)) | 4120 | if (netif_running(dev)) |
4253 | printk(KERN_INFO "%s: link down.\n", dev->name); | 4121 | netdev_info(dev, "link down\n"); |
4254 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 4122 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4255 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | 4123 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4256 | bmcr |= BMCR_ANENABLE; | 4124 | bmcr |= BMCR_ANENABLE; |
4257 | /* reset the phy in order for settings to stick, | 4125 | /* reset the phy in order for settings to stick, |
4258 | * and cause autoneg to start */ | 4126 | * and cause autoneg to start */ |
4259 | if (phy_reset(dev, bmcr)) { | 4127 | if (phy_reset(dev, bmcr)) { |
4260 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | 4128 | netdev_info(dev, "phy reset failed\n"); |
4261 | return -EINVAL; | 4129 | return -EINVAL; |
4262 | } | 4130 | } |
4263 | } else { | 4131 | } else { |
@@ -4306,7 +4174,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
4306 | if (np->phy_oui == PHY_OUI_MARVELL) { | 4174 | if (np->phy_oui == PHY_OUI_MARVELL) { |
4307 | /* reset the phy in order for forced mode settings to stick */ | 4175 | /* reset the phy in order for forced mode settings to stick */ |
4308 | if (phy_reset(dev, bmcr)) { | 4176 | if (phy_reset(dev, bmcr)) { |
4309 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | 4177 | netdev_info(dev, "phy reset failed\n"); |
4310 | return -EINVAL; | 4178 | return -EINVAL; |
4311 | } | 4179 | } |
4312 | } else { | 4180 | } else { |
@@ -4344,7 +4212,7 @@ static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void | |||
4344 | 4212 | ||
4345 | regs->version = FORCEDETH_REGS_VER; | 4213 | regs->version = FORCEDETH_REGS_VER; |
4346 | spin_lock_irq(&np->lock); | 4214 | spin_lock_irq(&np->lock); |
4347 | for (i = 0;i <= np->register_size/sizeof(u32); i++) | 4215 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
4348 | rbuf[i] = readl(base + i*sizeof(u32)); | 4216 | rbuf[i] = readl(base + i*sizeof(u32)); |
4349 | spin_unlock_irq(&np->lock); | 4217 | spin_unlock_irq(&np->lock); |
4350 | } | 4218 | } |
@@ -4368,7 +4236,7 @@ static int nv_nway_reset(struct net_device *dev) | |||
4368 | spin_unlock(&np->lock); | 4236 | spin_unlock(&np->lock); |
4369 | netif_addr_unlock(dev); | 4237 | netif_addr_unlock(dev); |
4370 | netif_tx_unlock_bh(dev); | 4238 | netif_tx_unlock_bh(dev); |
4371 | printk(KERN_INFO "%s: link down.\n", dev->name); | 4239 | netdev_info(dev, "link down\n"); |
4372 | } | 4240 | } |
4373 | 4241 | ||
4374 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 4242 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
@@ -4376,7 +4244,7 @@ static int nv_nway_reset(struct net_device *dev) | |||
4376 | bmcr |= BMCR_ANENABLE; | 4244 | bmcr |= BMCR_ANENABLE; |
4377 | /* reset the phy in order for settings to stick*/ | 4245 | /* reset the phy in order for settings to stick*/ |
4378 | if (phy_reset(dev, bmcr)) { | 4246 | if (phy_reset(dev, bmcr)) { |
4379 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | 4247 | netdev_info(dev, "phy reset failed\n"); |
4380 | return -EINVAL; | 4248 | return -EINVAL; |
4381 | } | 4249 | } |
4382 | } else { | 4250 | } else { |
@@ -4464,10 +4332,9 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri | |||
4464 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | 4332 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), |
4465 | rxtx_ring, ring_addr); | 4333 | rxtx_ring, ring_addr); |
4466 | } | 4334 | } |
4467 | if (rx_skbuff) | 4335 | |
4468 | kfree(rx_skbuff); | 4336 | kfree(rx_skbuff); |
4469 | if (tx_skbuff) | 4337 | kfree(tx_skbuff); |
4470 | kfree(tx_skbuff); | ||
4471 | goto exit; | 4338 | goto exit; |
4472 | } | 4339 | } |
4473 | 4340 | ||
@@ -4491,14 +4358,14 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri | |||
4491 | np->tx_ring_size = ring->tx_pending; | 4358 | np->tx_ring_size = ring->tx_pending; |
4492 | 4359 | ||
4493 | if (!nv_optimized(np)) { | 4360 | if (!nv_optimized(np)) { |
4494 | np->rx_ring.orig = (struct ring_desc*)rxtx_ring; | 4361 | np->rx_ring.orig = (struct ring_desc *)rxtx_ring; |
4495 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; | 4362 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4496 | } else { | 4363 | } else { |
4497 | np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; | 4364 | np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; |
4498 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; | 4365 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4499 | } | 4366 | } |
4500 | np->rx_skb = (struct nv_skb_map*)rx_skbuff; | 4367 | np->rx_skb = (struct nv_skb_map *)rx_skbuff; |
4501 | np->tx_skb = (struct nv_skb_map*)tx_skbuff; | 4368 | np->tx_skb = (struct nv_skb_map *)tx_skbuff; |
4502 | np->ring_addr = ring_addr; | 4369 | np->ring_addr = ring_addr; |
4503 | 4370 | ||
4504 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); | 4371 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
@@ -4515,7 +4382,7 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri | |||
4515 | /* reinit nic view of the queues */ | 4382 | /* reinit nic view of the queues */ |
4516 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | 4383 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
4517 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | 4384 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
4518 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | 4385 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
4519 | base + NvRegRingSizes); | 4386 | base + NvRegRingSizes); |
4520 | pci_push(base); | 4387 | pci_push(base); |
4521 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | 4388 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
@@ -4550,12 +4417,11 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* | |||
4550 | 4417 | ||
4551 | if ((!np->autoneg && np->duplex == 0) || | 4418 | if ((!np->autoneg && np->duplex == 0) || |
4552 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | 4419 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { |
4553 | printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", | 4420 | netdev_info(dev, "can not set pause settings when forced link is in half duplex\n"); |
4554 | dev->name); | ||
4555 | return -EINVAL; | 4421 | return -EINVAL; |
4556 | } | 4422 | } |
4557 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | 4423 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { |
4558 | printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); | 4424 | netdev_info(dev, "hardware does not support tx pause frames\n"); |
4559 | return -EINVAL; | 4425 | return -EINVAL; |
4560 | } | 4426 | } |
4561 | 4427 | ||
@@ -4590,7 +4456,7 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* | |||
4590 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | 4456 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4591 | 4457 | ||
4592 | if (netif_running(dev)) | 4458 | if (netif_running(dev)) |
4593 | printk(KERN_INFO "%s: link down.\n", dev->name); | 4459 | netdev_info(dev, "link down\n"); |
4594 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 4460 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4595 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | 4461 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
4596 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | 4462 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
@@ -4841,7 +4707,7 @@ static int nv_loopback_test(struct net_device *dev) | |||
4841 | /* reinit nic view of the rx queue */ | 4707 | /* reinit nic view of the rx queue */ |
4842 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | 4708 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
4843 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | 4709 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
4844 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | 4710 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
4845 | base + NvRegRingSizes); | 4711 | base + NvRegRingSizes); |
4846 | pci_push(base); | 4712 | pci_push(base); |
4847 | 4713 | ||
@@ -4852,8 +4718,7 @@ static int nv_loopback_test(struct net_device *dev) | |||
4852 | pkt_len = ETH_DATA_LEN; | 4718 | pkt_len = ETH_DATA_LEN; |
4853 | tx_skb = dev_alloc_skb(pkt_len); | 4719 | tx_skb = dev_alloc_skb(pkt_len); |
4854 | if (!tx_skb) { | 4720 | if (!tx_skb) { |
4855 | printk(KERN_ERR "dev_alloc_skb() failed during loopback test" | 4721 | netdev_err(dev, "dev_alloc_skb() failed during loopback test\n"); |
4856 | " of %s\n", dev->name); | ||
4857 | ret = 0; | 4722 | ret = 0; |
4858 | goto out; | 4723 | goto out; |
4859 | } | 4724 | } |
@@ -4893,29 +4758,22 @@ static int nv_loopback_test(struct net_device *dev) | |||
4893 | if (flags & NV_RX_ERROR) | 4758 | if (flags & NV_RX_ERROR) |
4894 | ret = 0; | 4759 | ret = 0; |
4895 | } else { | 4760 | } else { |
4896 | if (flags & NV_RX2_ERROR) { | 4761 | if (flags & NV_RX2_ERROR) |
4897 | ret = 0; | 4762 | ret = 0; |
4898 | } | ||
4899 | } | 4763 | } |
4900 | 4764 | ||
4901 | if (ret) { | 4765 | if (ret) { |
4902 | if (len != pkt_len) { | 4766 | if (len != pkt_len) { |
4903 | ret = 0; | 4767 | ret = 0; |
4904 | dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", | ||
4905 | dev->name, len, pkt_len); | ||
4906 | } else { | 4768 | } else { |
4907 | rx_skb = np->rx_skb[0].skb; | 4769 | rx_skb = np->rx_skb[0].skb; |
4908 | for (i = 0; i < pkt_len; i++) { | 4770 | for (i = 0; i < pkt_len; i++) { |
4909 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | 4771 | if (rx_skb->data[i] != (u8)(i & 0xff)) { |
4910 | ret = 0; | 4772 | ret = 0; |
4911 | dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", | ||
4912 | dev->name, i); | ||
4913 | break; | 4773 | break; |
4914 | } | 4774 | } |
4915 | } | 4775 | } |
4916 | } | 4776 | } |
4917 | } else { | ||
4918 | dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name); | ||
4919 | } | 4777 | } |
4920 | 4778 | ||
4921 | pci_unmap_single(np->pci_dev, test_dma_addr, | 4779 | pci_unmap_single(np->pci_dev, test_dma_addr, |
@@ -4958,11 +4816,10 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 | |||
4958 | netif_addr_lock(dev); | 4816 | netif_addr_lock(dev); |
4959 | spin_lock_irq(&np->lock); | 4817 | spin_lock_irq(&np->lock); |
4960 | nv_disable_hw_interrupts(dev, np->irqmask); | 4818 | nv_disable_hw_interrupts(dev, np->irqmask); |
4961 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | 4819 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
4962 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | 4820 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
4963 | } else { | 4821 | else |
4964 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | 4822 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
4965 | } | ||
4966 | /* stop engines */ | 4823 | /* stop engines */ |
4967 | nv_stop_rxtx(dev); | 4824 | nv_stop_rxtx(dev); |
4968 | nv_txrx_reset(dev); | 4825 | nv_txrx_reset(dev); |
@@ -5003,7 +4860,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 | |||
5003 | /* reinit nic view of the rx queue */ | 4860 | /* reinit nic view of the rx queue */ |
5004 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | 4861 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
5005 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | 4862 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
5006 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | 4863 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
5007 | base + NvRegRingSizes); | 4864 | base + NvRegRingSizes); |
5008 | pci_push(base); | 4865 | pci_push(base); |
5009 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | 4866 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
@@ -5106,8 +4963,7 @@ static int nv_mgmt_acquire_sema(struct net_device *dev) | |||
5106 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { | 4963 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5107 | np->mgmt_sema = 1; | 4964 | np->mgmt_sema = 1; |
5108 | return 1; | 4965 | return 1; |
5109 | } | 4966 | } else |
5110 | else | ||
5111 | udelay(50); | 4967 | udelay(50); |
5112 | } | 4968 | } |
5113 | 4969 | ||
@@ -5167,8 +5023,6 @@ static int nv_open(struct net_device *dev) | |||
5167 | int oom, i; | 5023 | int oom, i; |
5168 | u32 low; | 5024 | u32 low; |
5169 | 5025 | ||
5170 | dprintk(KERN_DEBUG "nv_open: begin\n"); | ||
5171 | |||
5172 | /* power up phy */ | 5026 | /* power up phy */ |
5173 | mii_rw(dev, np->phyaddr, MII_BMCR, | 5027 | mii_rw(dev, np->phyaddr, MII_BMCR, |
5174 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | 5028 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); |
@@ -5204,7 +5058,7 @@ static int nv_open(struct net_device *dev) | |||
5204 | 5058 | ||
5205 | /* give hw rings */ | 5059 | /* give hw rings */ |
5206 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | 5060 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
5207 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | 5061 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
5208 | base + NvRegRingSizes); | 5062 | base + NvRegRingSizes); |
5209 | 5063 | ||
5210 | writel(np->linkspeed, base + NvRegLinkSpeed); | 5064 | writel(np->linkspeed, base + NvRegLinkSpeed); |
@@ -5216,9 +5070,11 @@ static int nv_open(struct net_device *dev) | |||
5216 | writel(np->vlanctl_bits, base + NvRegVlanControl); | 5070 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
5217 | pci_push(base); | 5071 | pci_push(base); |
5218 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); | 5072 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
5219 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | 5073 | if (reg_delay(dev, NvRegUnknownSetupReg5, |
5220 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | 5074 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
5221 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | 5075 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) |
5076 | netdev_info(dev, | ||
5077 | "%s: SetupReg5, Bit 31 remained off\n", __func__); | ||
5222 | 5078 | ||
5223 | writel(0, base + NvRegMIIMask); | 5079 | writel(0, base + NvRegMIIMask); |
5224 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | 5080 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
@@ -5251,8 +5107,7 @@ static int nv_open(struct net_device *dev) | |||
5251 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | 5107 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); |
5252 | else | 5108 | else |
5253 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | 5109 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); |
5254 | } | 5110 | } else |
5255 | else | ||
5256 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); | 5111 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
5257 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | 5112 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5258 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | 5113 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
@@ -5263,7 +5118,7 @@ static int nv_open(struct net_device *dev) | |||
5263 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | 5118 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); |
5264 | 5119 | ||
5265 | i = readl(base + NvRegPowerState); | 5120 | i = readl(base + NvRegPowerState); |
5266 | if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) | 5121 | if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) |
5267 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); | 5122 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
5268 | 5123 | ||
5269 | pci_push(base); | 5124 | pci_push(base); |
@@ -5276,9 +5131,8 @@ static int nv_open(struct net_device *dev) | |||
5276 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | 5131 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5277 | pci_push(base); | 5132 | pci_push(base); |
5278 | 5133 | ||
5279 | if (nv_request_irq(dev, 0)) { | 5134 | if (nv_request_irq(dev, 0)) |
5280 | goto out_drain; | 5135 | goto out_drain; |
5281 | } | ||
5282 | 5136 | ||
5283 | /* ask for interrupts */ | 5137 | /* ask for interrupts */ |
5284 | nv_enable_hw_interrupts(dev, np->irqmask); | 5138 | nv_enable_hw_interrupts(dev, np->irqmask); |
@@ -5296,7 +5150,6 @@ static int nv_open(struct net_device *dev) | |||
5296 | u32 miistat; | 5150 | u32 miistat; |
5297 | miistat = readl(base + NvRegMIIStatus); | 5151 | miistat = readl(base + NvRegMIIStatus); |
5298 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); | 5152 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
5299 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); | ||
5300 | } | 5153 | } |
5301 | /* set linkspeed to invalid value, thus force nv_update_linkspeed | 5154 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5302 | * to init hw */ | 5155 | * to init hw */ |
@@ -5309,7 +5162,7 @@ static int nv_open(struct net_device *dev) | |||
5309 | if (ret) { | 5162 | if (ret) { |
5310 | netif_carrier_on(dev); | 5163 | netif_carrier_on(dev); |
5311 | } else { | 5164 | } else { |
5312 | printk(KERN_INFO "%s: no link during initialization.\n", dev->name); | 5165 | netdev_info(dev, "no link during initialization\n"); |
5313 | netif_carrier_off(dev); | 5166 | netif_carrier_off(dev); |
5314 | } | 5167 | } |
5315 | if (oom) | 5168 | if (oom) |
@@ -5352,7 +5205,6 @@ static int nv_close(struct net_device *dev) | |||
5352 | base = get_hwbase(dev); | 5205 | base = get_hwbase(dev); |
5353 | nv_disable_hw_interrupts(dev, np->irqmask); | 5206 | nv_disable_hw_interrupts(dev, np->irqmask); |
5354 | pci_push(base); | 5207 | pci_push(base); |
5355 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); | ||
5356 | 5208 | ||
5357 | spin_unlock_irq(&np->lock); | 5209 | spin_unlock_irq(&np->lock); |
5358 | 5210 | ||
@@ -5421,8 +5273,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5421 | static int printed_version; | 5273 | static int printed_version; |
5422 | 5274 | ||
5423 | if (!printed_version++) | 5275 | if (!printed_version++) |
5424 | printk(KERN_INFO "%s: Reverse Engineered nForce ethernet" | 5276 | pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n", |
5425 | " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION); | 5277 | FORCEDETH_VERSION); |
5426 | 5278 | ||
5427 | dev = alloc_etherdev(sizeof(struct fe_priv)); | 5279 | dev = alloc_etherdev(sizeof(struct fe_priv)); |
5428 | err = -ENOMEM; | 5280 | err = -ENOMEM; |
@@ -5465,10 +5317,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5465 | err = -EINVAL; | 5317 | err = -EINVAL; |
5466 | addr = 0; | 5318 | addr = 0; |
5467 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | 5319 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
5468 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", | ||
5469 | pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), | ||
5470 | pci_resource_len(pci_dev, i), | ||
5471 | pci_resource_flags(pci_dev, i)); | ||
5472 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && | 5320 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
5473 | pci_resource_len(pci_dev, i) >= np->register_size) { | 5321 | pci_resource_len(pci_dev, i) >= np->register_size) { |
5474 | addr = pci_resource_start(pci_dev, i); | 5322 | addr = pci_resource_start(pci_dev, i); |
@@ -5476,8 +5324,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5476 | } | 5324 | } |
5477 | } | 5325 | } |
5478 | if (i == DEVICE_COUNT_RESOURCE) { | 5326 | if (i == DEVICE_COUNT_RESOURCE) { |
5479 | dev_printk(KERN_INFO, &pci_dev->dev, | 5327 | dev_info(&pci_dev->dev, "Couldn't find register window\n"); |
5480 | "Couldn't find register window\n"); | ||
5481 | goto out_relreg; | 5328 | goto out_relreg; |
5482 | } | 5329 | } |
5483 | 5330 | ||
@@ -5493,13 +5340,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5493 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; | 5340 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
5494 | if (dma_64bit) { | 5341 | if (dma_64bit) { |
5495 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) | 5342 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) |
5496 | dev_printk(KERN_INFO, &pci_dev->dev, | 5343 | dev_info(&pci_dev->dev, |
5497 | "64-bit DMA failed, using 32-bit addressing\n"); | 5344 | "64-bit DMA failed, using 32-bit addressing\n"); |
5498 | else | 5345 | else |
5499 | dev->features |= NETIF_F_HIGHDMA; | 5346 | dev->features |= NETIF_F_HIGHDMA; |
5500 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { | 5347 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { |
5501 | dev_printk(KERN_INFO, &pci_dev->dev, | 5348 | dev_info(&pci_dev->dev, |
5502 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | 5349 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); |
5503 | } | 5350 | } |
5504 | } | 5351 | } |
5505 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | 5352 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { |
@@ -5620,7 +5467,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5620 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | 5467 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
5621 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | 5468 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
5622 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); | 5469 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
5623 | printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n"); | 5470 | dev_dbg(&pci_dev->dev, |
5471 | "%s: set workaround bit for reversed mac addr\n", | ||
5472 | __func__); | ||
5624 | } | 5473 | } |
5625 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | 5474 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
5626 | 5475 | ||
@@ -5629,28 +5478,21 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5629 | * Bad mac address. At least one bios sets the mac address | 5478 | * Bad mac address. At least one bios sets the mac address |
5630 | * to 01:23:45:67:89:ab | 5479 | * to 01:23:45:67:89:ab |
5631 | */ | 5480 | */ |
5632 | dev_printk(KERN_ERR, &pci_dev->dev, | 5481 | dev_err(&pci_dev->dev, |
5633 | "Invalid Mac address detected: %pM\n", | 5482 | "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n", |
5634 | dev->dev_addr); | 5483 | dev->dev_addr); |
5635 | dev_printk(KERN_ERR, &pci_dev->dev, | ||
5636 | "Please complain to your hardware vendor. Switching to a random MAC.\n"); | ||
5637 | random_ether_addr(dev->dev_addr); | 5484 | random_ether_addr(dev->dev_addr); |
5485 | dev_err(&pci_dev->dev, | ||
5486 | "Using random MAC address: %pM\n", dev->dev_addr); | ||
5638 | } | 5487 | } |
5639 | 5488 | ||
5640 | dprintk(KERN_DEBUG "%s: MAC Address %pM\n", | ||
5641 | pci_name(pci_dev), dev->dev_addr); | ||
5642 | |||
5643 | /* set mac address */ | 5489 | /* set mac address */ |
5644 | nv_copy_mac_to_hw(dev); | 5490 | nv_copy_mac_to_hw(dev); |
5645 | 5491 | ||
5646 | /* Workaround current PCI init glitch: wakeup bits aren't | ||
5647 | * being set from PCI PM capability. | ||
5648 | */ | ||
5649 | device_init_wakeup(&pci_dev->dev, 1); | ||
5650 | |||
5651 | /* disable WOL */ | 5492 | /* disable WOL */ |
5652 | writel(0, base + NvRegWakeUpFlags); | 5493 | writel(0, base + NvRegWakeUpFlags); |
5653 | np->wolenabled = 0; | 5494 | np->wolenabled = 0; |
5495 | device_set_wakeup_enable(&pci_dev->dev, false); | ||
5654 | 5496 | ||
5655 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { | 5497 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
5656 | 5498 | ||
@@ -5663,16 +5505,15 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5663 | writel(powerstate, base + NvRegPowerState2); | 5505 | writel(powerstate, base + NvRegPowerState2); |
5664 | } | 5506 | } |
5665 | 5507 | ||
5666 | if (np->desc_ver == DESC_VER_1) { | 5508 | if (np->desc_ver == DESC_VER_1) |
5667 | np->tx_flags = NV_TX_VALID; | 5509 | np->tx_flags = NV_TX_VALID; |
5668 | } else { | 5510 | else |
5669 | np->tx_flags = NV_TX2_VALID; | 5511 | np->tx_flags = NV_TX2_VALID; |
5670 | } | ||
5671 | 5512 | ||
5672 | np->msi_flags = 0; | 5513 | np->msi_flags = 0; |
5673 | if ((id->driver_data & DEV_HAS_MSI) && msi) { | 5514 | if ((id->driver_data & DEV_HAS_MSI) && msi) |
5674 | np->msi_flags |= NV_MSI_CAPABLE; | 5515 | np->msi_flags |= NV_MSI_CAPABLE; |
5675 | } | 5516 | |
5676 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { | 5517 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5677 | /* msix has had reported issues when modifying irqmask | 5518 | /* msix has had reported issues when modifying irqmask |
5678 | as in the case of napi, therefore, disable for now | 5519 | as in the case of napi, therefore, disable for now |
@@ -5702,11 +5543,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5702 | if (id->driver_data & DEV_NEED_TIMERIRQ) | 5543 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5703 | np->irqmask |= NVREG_IRQ_TIMER; | 5544 | np->irqmask |= NVREG_IRQ_TIMER; |
5704 | if (id->driver_data & DEV_NEED_LINKTIMER) { | 5545 | if (id->driver_data & DEV_NEED_LINKTIMER) { |
5705 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); | ||
5706 | np->need_linktimer = 1; | 5546 | np->need_linktimer = 1; |
5707 | np->link_timeout = jiffies + LINK_TIMEOUT; | 5547 | np->link_timeout = jiffies + LINK_TIMEOUT; |
5708 | } else { | 5548 | } else { |
5709 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); | ||
5710 | np->need_linktimer = 0; | 5549 | np->need_linktimer = 0; |
5711 | } | 5550 | } |
5712 | 5551 | ||
@@ -5735,19 +5574,14 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5735 | nv_mgmt_acquire_sema(dev) && | 5574 | nv_mgmt_acquire_sema(dev) && |
5736 | nv_mgmt_get_version(dev)) { | 5575 | nv_mgmt_get_version(dev)) { |
5737 | np->mac_in_use = 1; | 5576 | np->mac_in_use = 1; |
5738 | if (np->mgmt_version > 0) { | 5577 | if (np->mgmt_version > 0) |
5739 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; | 5578 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; |
5740 | } | ||
5741 | dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", | ||
5742 | pci_name(pci_dev), np->mac_in_use); | ||
5743 | /* management unit setup the phy already? */ | 5579 | /* management unit setup the phy already? */ |
5744 | if (np->mac_in_use && | 5580 | if (np->mac_in_use && |
5745 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | 5581 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == |
5746 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | 5582 | NVREG_XMITCTL_SYNC_PHY_INIT)) { |
5747 | /* phy is inited by mgmt unit */ | 5583 | /* phy is inited by mgmt unit */ |
5748 | phyinitialized = 1; | 5584 | phyinitialized = 1; |
5749 | dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", | ||
5750 | pci_name(pci_dev)); | ||
5751 | } else { | 5585 | } else { |
5752 | /* we need to init the phy */ | 5586 | /* we need to init the phy */ |
5753 | } | 5587 | } |
@@ -5773,8 +5607,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5773 | np->phy_model = id2 & PHYID2_MODEL_MASK; | 5607 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
5774 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; | 5608 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5775 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | 5609 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
5776 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", | ||
5777 | pci_name(pci_dev), id1, id2, phyaddr); | ||
5778 | np->phyaddr = phyaddr; | 5610 | np->phyaddr = phyaddr; |
5779 | np->phy_oui = id1 | id2; | 5611 | np->phy_oui = id1 | id2; |
5780 | 5612 | ||
@@ -5788,8 +5620,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5788 | break; | 5620 | break; |
5789 | } | 5621 | } |
5790 | if (i == 33) { | 5622 | if (i == 33) { |
5791 | dev_printk(KERN_INFO, &pci_dev->dev, | 5623 | dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n"); |
5792 | "open: Could not find a valid PHY.\n"); | ||
5793 | goto out_error; | 5624 | goto out_error; |
5794 | } | 5625 | } |
5795 | 5626 | ||
@@ -5799,9 +5630,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5799 | } else { | 5630 | } else { |
5800 | /* see if it is a gigabit phy */ | 5631 | /* see if it is a gigabit phy */ |
5801 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | 5632 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
5802 | if (mii_status & PHY_GIGABIT) { | 5633 | if (mii_status & PHY_GIGABIT) |
5803 | np->gigabit = PHY_GIGABIT; | 5634 | np->gigabit = PHY_GIGABIT; |
5804 | } | ||
5805 | } | 5635 | } |
5806 | 5636 | ||
5807 | /* set default link speed settings */ | 5637 | /* set default link speed settings */ |
@@ -5811,37 +5641,27 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
5811 | 5641 | ||
5812 | err = register_netdev(dev); | 5642 | err = register_netdev(dev); |
5813 | if (err) { | 5643 | if (err) { |
5814 | dev_printk(KERN_INFO, &pci_dev->dev, | 5644 | dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err); |
5815 | "unable to register netdev: %d\n", err); | ||
5816 | goto out_error; | 5645 | goto out_error; |
5817 | } | 5646 | } |
5818 | 5647 | ||
5819 | dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, " | 5648 | dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n", |
5820 | "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", | 5649 | dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); |
5821 | dev->name, | 5650 | |
5822 | np->phy_oui, | 5651 | dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", |
5823 | np->phyaddr, | 5652 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", |
5824 | dev->dev_addr[0], | 5653 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? |
5825 | dev->dev_addr[1], | 5654 | "csum " : "", |
5826 | dev->dev_addr[2], | 5655 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? |
5827 | dev->dev_addr[3], | 5656 | "vlan " : "", |
5828 | dev->dev_addr[4], | 5657 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", |
5829 | dev->dev_addr[5]); | 5658 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", |
5830 | 5659 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
5831 | dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", | 5660 | np->gigabit == PHY_GIGABIT ? "gbit " : "", |
5832 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", | 5661 | np->need_linktimer ? "lnktim " : "", |
5833 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? | 5662 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", |
5834 | "csum " : "", | 5663 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", |
5835 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? | 5664 | np->desc_ver); |
5836 | "vlan " : "", | ||
5837 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", | ||
5838 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | ||
5839 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | ||
5840 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | ||
5841 | np->need_linktimer ? "lnktim " : "", | ||
5842 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | ||
5843 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | ||
5844 | np->desc_ver); | ||
5845 | 5665 | ||
5846 | return 0; | 5666 | return 0; |
5847 | 5667 | ||
@@ -5923,44 +5743,37 @@ static void __devexit nv_remove(struct pci_dev *pci_dev) | |||
5923 | } | 5743 | } |
5924 | 5744 | ||
5925 | #ifdef CONFIG_PM | 5745 | #ifdef CONFIG_PM |
5926 | static int nv_suspend(struct pci_dev *pdev, pm_message_t state) | 5746 | static int nv_suspend(struct device *device) |
5927 | { | 5747 | { |
5748 | struct pci_dev *pdev = to_pci_dev(device); | ||
5928 | struct net_device *dev = pci_get_drvdata(pdev); | 5749 | struct net_device *dev = pci_get_drvdata(pdev); |
5929 | struct fe_priv *np = netdev_priv(dev); | 5750 | struct fe_priv *np = netdev_priv(dev); |
5930 | u8 __iomem *base = get_hwbase(dev); | 5751 | u8 __iomem *base = get_hwbase(dev); |
5931 | int i; | 5752 | int i; |
5932 | 5753 | ||
5933 | if (netif_running(dev)) { | 5754 | if (netif_running(dev)) { |
5934 | // Gross. | 5755 | /* Gross. */ |
5935 | nv_close(dev); | 5756 | nv_close(dev); |
5936 | } | 5757 | } |
5937 | netif_device_detach(dev); | 5758 | netif_device_detach(dev); |
5938 | 5759 | ||
5939 | /* save non-pci configuration space */ | 5760 | /* save non-pci configuration space */ |
5940 | for (i = 0;i <= np->register_size/sizeof(u32); i++) | 5761 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
5941 | np->saved_config_space[i] = readl(base + i*sizeof(u32)); | 5762 | np->saved_config_space[i] = readl(base + i*sizeof(u32)); |
5942 | 5763 | ||
5943 | pci_save_state(pdev); | ||
5944 | pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled); | ||
5945 | pci_disable_device(pdev); | ||
5946 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
5947 | return 0; | 5764 | return 0; |
5948 | } | 5765 | } |
5949 | 5766 | ||
5950 | static int nv_resume(struct pci_dev *pdev) | 5767 | static int nv_resume(struct device *device) |
5951 | { | 5768 | { |
5769 | struct pci_dev *pdev = to_pci_dev(device); | ||
5952 | struct net_device *dev = pci_get_drvdata(pdev); | 5770 | struct net_device *dev = pci_get_drvdata(pdev); |
5953 | struct fe_priv *np = netdev_priv(dev); | 5771 | struct fe_priv *np = netdev_priv(dev); |
5954 | u8 __iomem *base = get_hwbase(dev); | 5772 | u8 __iomem *base = get_hwbase(dev); |
5955 | int i, rc = 0; | 5773 | int i, rc = 0; |
5956 | 5774 | ||
5957 | pci_set_power_state(pdev, PCI_D0); | ||
5958 | pci_restore_state(pdev); | ||
5959 | /* ack any pending wake events, disable PME */ | ||
5960 | pci_enable_wake(pdev, PCI_D0, 0); | ||
5961 | |||
5962 | /* restore non-pci configuration space */ | 5775 | /* restore non-pci configuration space */ |
5963 | for (i = 0;i <= np->register_size/sizeof(u32); i++) | 5776 | for (i = 0; i <= np->register_size/sizeof(u32); i++) |
5964 | writel(np->saved_config_space[i], base+i*sizeof(u32)); | 5777 | writel(np->saved_config_space[i], base+i*sizeof(u32)); |
5965 | 5778 | ||
5966 | if (np->driver_data & DEV_NEED_MSI_FIX) | 5779 | if (np->driver_data & DEV_NEED_MSI_FIX) |
@@ -5977,6 +5790,9 @@ static int nv_resume(struct pci_dev *pdev) | |||
5977 | return rc; | 5790 | return rc; |
5978 | } | 5791 | } |
5979 | 5792 | ||
5793 | static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume); | ||
5794 | #define NV_PM_OPS (&nv_pm_ops) | ||
5795 | |||
5980 | static void nv_shutdown(struct pci_dev *pdev) | 5796 | static void nv_shutdown(struct pci_dev *pdev) |
5981 | { | 5797 | { |
5982 | struct net_device *dev = pci_get_drvdata(pdev); | 5798 | struct net_device *dev = pci_get_drvdata(pdev); |
@@ -5990,9 +5806,8 @@ static void nv_shutdown(struct pci_dev *pdev) | |||
5990 | * If we really go for poweroff, we must not restore the MAC, | 5806 | * If we really go for poweroff, we must not restore the MAC, |
5991 | * otherwise the MAC for WOL will be reversed at least on some boards. | 5807 | * otherwise the MAC for WOL will be reversed at least on some boards. |
5992 | */ | 5808 | */ |
5993 | if (system_state != SYSTEM_POWER_OFF) { | 5809 | if (system_state != SYSTEM_POWER_OFF) |
5994 | nv_restore_mac_addr(pdev); | 5810 | nv_restore_mac_addr(pdev); |
5995 | } | ||
5996 | 5811 | ||
5997 | pci_disable_device(pdev); | 5812 | pci_disable_device(pdev); |
5998 | /* | 5813 | /* |
@@ -6000,15 +5815,13 @@ static void nv_shutdown(struct pci_dev *pdev) | |||
6000 | * only put the device into D3 if we really go for poweroff. | 5815 | * only put the device into D3 if we really go for poweroff. |
6001 | */ | 5816 | */ |
6002 | if (system_state == SYSTEM_POWER_OFF) { | 5817 | if (system_state == SYSTEM_POWER_OFF) { |
6003 | if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled)) | 5818 | pci_wake_from_d3(pdev, np->wolenabled); |
6004 | pci_enable_wake(pdev, PCI_D3hot, np->wolenabled); | ||
6005 | pci_set_power_state(pdev, PCI_D3hot); | 5819 | pci_set_power_state(pdev, PCI_D3hot); |
6006 | } | 5820 | } |
6007 | } | 5821 | } |
6008 | #else | 5822 | #else |
6009 | #define nv_suspend NULL | 5823 | #define NV_PM_OPS NULL |
6010 | #define nv_shutdown NULL | 5824 | #define nv_shutdown NULL |
6011 | #define nv_resume NULL | ||
6012 | #endif /* CONFIG_PM */ | 5825 | #endif /* CONFIG_PM */ |
6013 | 5826 | ||
6014 | static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = { | 5827 | static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = { |
@@ -6180,9 +5993,8 @@ static struct pci_driver driver = { | |||
6180 | .id_table = pci_tbl, | 5993 | .id_table = pci_tbl, |
6181 | .probe = nv_probe, | 5994 | .probe = nv_probe, |
6182 | .remove = __devexit_p(nv_remove), | 5995 | .remove = __devexit_p(nv_remove), |
6183 | .suspend = nv_suspend, | ||
6184 | .resume = nv_resume, | ||
6185 | .shutdown = nv_shutdown, | 5996 | .shutdown = nv_shutdown, |
5997 | .driver.pm = NV_PM_OPS, | ||
6186 | }; | 5998 | }; |
6187 | 5999 | ||
6188 | static int __init init_nic(void) | 6000 | static int __init init_nic(void) |