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-rw-r--r--drivers/net/forcedeth.c232
1 files changed, 115 insertions, 117 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index d0b1d9f17a5d..b60a3041b64c 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -77,27 +77,31 @@
77 * Hardware access: 77 * Hardware access:
78 */ 78 */
79 79
80#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */ 80#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
81#define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */ 81#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
82#define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */ 82#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
83#define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */ 83#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
84#define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */ 84#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
85#define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */ 85#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
86#define DEV_HAS_MSI 0x000040 /* device supports MSI */ 86#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
87#define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */ 87#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
88#define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */ 88#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
89#define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */ 89#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
90#define DEV_HAS_STATISTICS_V2 0x000600 /* device supports hw statistics version 2 */ 90#define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
91#define DEV_HAS_STATISTICS_V3 0x000e00 /* device supports hw statistics version 3 */ 91#define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
92#define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */ 92#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
93#define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */ 93#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
94#define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */ 94#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
95#define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */ 95#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
96#define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */ 96#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
97#define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */ 97#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
98#define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */ 98#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
99#define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */ 99#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
100#define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */ 100#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
101#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
102#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
103#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
104#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
101 105
102enum { 106enum {
103 NvRegIrqStatus = 0x000, 107 NvRegIrqStatus = 0x000,
@@ -898,6 +902,12 @@ enum {
898}; 902};
899static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; 903static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
900 904
905/*
906 * Power down phy when interface is down (persists through reboot;
907 * older Linux and other OSes may not power it up again)
908 */
909static int phy_power_down = 0;
910
901static inline struct fe_priv *get_nvpriv(struct net_device *dev) 911static inline struct fe_priv *get_nvpriv(struct net_device *dev)
902{ 912{
903 return netdev_priv(dev); 913 return netdev_priv(dev);
@@ -1265,14 +1275,7 @@ static int phy_init(struct net_device *dev)
1265 } 1275 }
1266 } 1276 }
1267 if (np->phy_model == PHY_MODEL_REALTEK_8201) { 1277 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1268 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 1278 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1269 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1270 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1271 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1272 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1273 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1274 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1275 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1276 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1279 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1277 phy_reserved |= PHY_REALTEK_INIT7; 1280 phy_reserved |= PHY_REALTEK_INIT7;
1278 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { 1281 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
@@ -1463,14 +1466,7 @@ static int phy_init(struct net_device *dev)
1463 } 1466 }
1464 } 1467 }
1465 if (np->phy_model == PHY_MODEL_REALTEK_8201) { 1468 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1466 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 1469 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1467 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1468 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1469 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1470 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1471 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1472 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1473 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1474 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1470 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1475 phy_reserved |= PHY_REALTEK_INIT7; 1471 phy_reserved |= PHY_REALTEK_INIT7;
1476 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { 1472 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
@@ -1503,7 +1499,10 @@ static int phy_init(struct net_device *dev)
1503 1499
1504 /* restart auto negotiation, power down phy */ 1500 /* restart auto negotiation, power down phy */
1505 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 1501 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1506 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN); 1502 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1503 if (phy_power_down) {
1504 mii_control |= BMCR_PDOWN;
1505 }
1507 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { 1506 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1508 return PHY_ERROR; 1507 return PHY_ERROR;
1509 } 1508 }
@@ -5534,7 +5533,7 @@ static int nv_close(struct net_device *dev)
5534 5533
5535 nv_drain_rxtx(dev); 5534 nv_drain_rxtx(dev);
5536 5535
5537 if (np->wolenabled) { 5536 if (np->wolenabled || !phy_power_down) {
5538 nv_txrx_gate(dev, false); 5537 nv_txrx_gate(dev, false);
5539 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); 5538 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5540 nv_start_rx(dev); 5539 nv_start_rx(dev);
@@ -5835,8 +5834,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5835 /* take phy and nic out of low power mode */ 5834 /* take phy and nic out of low power mode */
5836 powerstate = readl(base + NvRegPowerState2); 5835 powerstate = readl(base + NvRegPowerState2);
5837 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; 5836 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5838 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || 5837 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5839 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5840 pci_dev->revision >= 0xA3) 5838 pci_dev->revision >= 0xA3)
5841 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; 5839 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5842 writel(powerstate, base + NvRegPowerState2); 5840 writel(powerstate, base + NvRegPowerState2);
@@ -5892,14 +5890,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5892 /* Limit the number of tx's outstanding for hw bug */ 5890 /* Limit the number of tx's outstanding for hw bug */
5893 if (id->driver_data & DEV_NEED_TX_LIMIT) { 5891 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5894 np->tx_limit = 1; 5892 np->tx_limit = 1;
5895 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 5893 if ((id->driver_data & DEV_NEED_TX_LIMIT2) &&
5896 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5897 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5898 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5899 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5900 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5901 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5902 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5903 pci_dev->revision >= 0xA2) 5894 pci_dev->revision >= 0xA2)
5904 np->tx_limit = 0; 5895 np->tx_limit = 0;
5905 } 5896 }
@@ -6149,7 +6140,8 @@ static int nv_resume(struct pci_dev *pdev)
6149 for (i = 0;i <= np->register_size/sizeof(u32); i++) 6140 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6150 writel(np->saved_config_space[i], base+i*sizeof(u32)); 6141 writel(np->saved_config_space[i], base+i*sizeof(u32));
6151 6142
6152 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE); 6143 if (np->driver_data & DEV_NEED_MSI_FIX)
6144 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6153 6145
6154 /* restore phy state, including autoneg */ 6146 /* restore phy state, including autoneg */
6155 phy_init(dev); 6147 phy_init(dev);
@@ -6198,160 +6190,164 @@ static void nv_shutdown(struct pci_dev *pdev)
6198 6190
6199static struct pci_device_id pci_tbl[] = { 6191static struct pci_device_id pci_tbl[] = {
6200 { /* nForce Ethernet Controller */ 6192 { /* nForce Ethernet Controller */
6201 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), 6193 PCI_DEVICE(0x10DE, 0x01C3),
6202 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 6194 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6203 }, 6195 },
6204 { /* nForce2 Ethernet Controller */ 6196 { /* nForce2 Ethernet Controller */
6205 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), 6197 PCI_DEVICE(0x10DE, 0x0066),
6206 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 6198 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6207 }, 6199 },
6208 { /* nForce3 Ethernet Controller */ 6200 { /* nForce3 Ethernet Controller */
6209 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), 6201 PCI_DEVICE(0x10DE, 0x00D6),
6210 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 6202 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6211 }, 6203 },
6212 { /* nForce3 Ethernet Controller */ 6204 { /* nForce3 Ethernet Controller */
6213 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), 6205 PCI_DEVICE(0x10DE, 0x0086),
6214 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6206 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6215 }, 6207 },
6216 { /* nForce3 Ethernet Controller */ 6208 { /* nForce3 Ethernet Controller */
6217 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), 6209 PCI_DEVICE(0x10DE, 0x008C),
6218 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6210 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6219 }, 6211 },
6220 { /* nForce3 Ethernet Controller */ 6212 { /* nForce3 Ethernet Controller */
6221 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), 6213 PCI_DEVICE(0x10DE, 0x00E6),
6222 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6214 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6223 }, 6215 },
6224 { /* nForce3 Ethernet Controller */ 6216 { /* nForce3 Ethernet Controller */
6225 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), 6217 PCI_DEVICE(0x10DE, 0x00DF),
6226 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6218 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6227 }, 6219 },
6228 { /* CK804 Ethernet Controller */ 6220 { /* CK804 Ethernet Controller */
6229 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), 6221 PCI_DEVICE(0x10DE, 0x0056),
6230 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6222 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6231 }, 6223 },
6232 { /* CK804 Ethernet Controller */ 6224 { /* CK804 Ethernet Controller */
6233 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), 6225 PCI_DEVICE(0x10DE, 0x0057),
6234 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6226 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6235 }, 6227 },
6236 { /* MCP04 Ethernet Controller */ 6228 { /* MCP04 Ethernet Controller */
6237 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), 6229 PCI_DEVICE(0x10DE, 0x0037),
6238 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6230 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6239 }, 6231 },
6240 { /* MCP04 Ethernet Controller */ 6232 { /* MCP04 Ethernet Controller */
6241 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), 6233 PCI_DEVICE(0x10DE, 0x0038),
6242 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6234 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6243 }, 6235 },
6244 { /* MCP51 Ethernet Controller */ 6236 { /* MCP51 Ethernet Controller */
6245 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), 6237 PCI_DEVICE(0x10DE, 0x0268),
6246 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, 6238 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6247 }, 6239 },
6248 { /* MCP51 Ethernet Controller */ 6240 { /* MCP51 Ethernet Controller */
6249 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), 6241 PCI_DEVICE(0x10DE, 0x0269),
6250 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, 6242 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6251 }, 6243 },
6252 { /* MCP55 Ethernet Controller */ 6244 { /* MCP55 Ethernet Controller */
6253 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), 6245 PCI_DEVICE(0x10DE, 0x0372),
6254 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, 6246 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6255 }, 6247 },
6256 { /* MCP55 Ethernet Controller */ 6248 { /* MCP55 Ethernet Controller */
6257 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), 6249 PCI_DEVICE(0x10DE, 0x0373),
6258 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, 6250 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6259 }, 6251 },
6260 { /* MCP61 Ethernet Controller */ 6252 { /* MCP61 Ethernet Controller */
6261 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), 6253 PCI_DEVICE(0x10DE, 0x03E5),
6262 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6254 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6263 }, 6255 },
6264 { /* MCP61 Ethernet Controller */ 6256 { /* MCP61 Ethernet Controller */
6265 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), 6257 PCI_DEVICE(0x10DE, 0x03E6),
6266 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6258 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6267 }, 6259 },
6268 { /* MCP61 Ethernet Controller */ 6260 { /* MCP61 Ethernet Controller */
6269 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), 6261 PCI_DEVICE(0x10DE, 0x03EE),
6270 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6262 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6271 }, 6263 },
6272 { /* MCP61 Ethernet Controller */ 6264 { /* MCP61 Ethernet Controller */
6273 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), 6265 PCI_DEVICE(0x10DE, 0x03EF),
6274 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6266 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6275 }, 6267 },
6276 { /* MCP65 Ethernet Controller */ 6268 { /* MCP65 Ethernet Controller */
6277 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), 6269 PCI_DEVICE(0x10DE, 0x0450),
6278 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6270 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6279 }, 6271 },
6280 { /* MCP65 Ethernet Controller */ 6272 { /* MCP65 Ethernet Controller */
6281 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), 6273 PCI_DEVICE(0x10DE, 0x0451),
6282 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6274 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6283 }, 6275 },
6284 { /* MCP65 Ethernet Controller */ 6276 { /* MCP65 Ethernet Controller */
6285 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), 6277 PCI_DEVICE(0x10DE, 0x0452),
6286 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6278 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6287 }, 6279 },
6288 { /* MCP65 Ethernet Controller */ 6280 { /* MCP65 Ethernet Controller */
6289 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), 6281 PCI_DEVICE(0x10DE, 0x0453),
6290 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6282 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6291 }, 6283 },
6292 { /* MCP67 Ethernet Controller */ 6284 { /* MCP67 Ethernet Controller */
6293 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), 6285 PCI_DEVICE(0x10DE, 0x054C),
6294 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6286 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6295 }, 6287 },
6296 { /* MCP67 Ethernet Controller */ 6288 { /* MCP67 Ethernet Controller */
6297 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), 6289 PCI_DEVICE(0x10DE, 0x054D),
6298 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6290 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6299 }, 6291 },
6300 { /* MCP67 Ethernet Controller */ 6292 { /* MCP67 Ethernet Controller */
6301 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), 6293 PCI_DEVICE(0x10DE, 0x054E),
6302 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6294 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6303 }, 6295 },
6304 { /* MCP67 Ethernet Controller */ 6296 { /* MCP67 Ethernet Controller */
6305 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), 6297 PCI_DEVICE(0x10DE, 0x054F),
6306 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6298 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6307 }, 6299 },
6308 { /* MCP73 Ethernet Controller */ 6300 { /* MCP73 Ethernet Controller */
6309 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28), 6301 PCI_DEVICE(0x10DE, 0x07DC),
6310 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6302 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6311 }, 6303 },
6312 { /* MCP73 Ethernet Controller */ 6304 { /* MCP73 Ethernet Controller */
6313 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29), 6305 PCI_DEVICE(0x10DE, 0x07DD),
6314 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6306 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6315 }, 6307 },
6316 { /* MCP73 Ethernet Controller */ 6308 { /* MCP73 Ethernet Controller */
6317 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30), 6309 PCI_DEVICE(0x10DE, 0x07DE),
6318 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6310 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6319 }, 6311 },
6320 { /* MCP73 Ethernet Controller */ 6312 { /* MCP73 Ethernet Controller */
6321 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31), 6313 PCI_DEVICE(0x10DE, 0x07DF),
6322 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6314 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6323 }, 6315 },
6324 { /* MCP77 Ethernet Controller */ 6316 { /* MCP77 Ethernet Controller */
6325 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), 6317 PCI_DEVICE(0x10DE, 0x0760),
6326 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6318 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6327 }, 6319 },
6328 { /* MCP77 Ethernet Controller */ 6320 { /* MCP77 Ethernet Controller */
6329 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), 6321 PCI_DEVICE(0x10DE, 0x0761),
6330 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6322 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6331 }, 6323 },
6332 { /* MCP77 Ethernet Controller */ 6324 { /* MCP77 Ethernet Controller */
6333 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), 6325 PCI_DEVICE(0x10DE, 0x0762),
6334 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6326 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6335 }, 6327 },
6336 { /* MCP77 Ethernet Controller */ 6328 { /* MCP77 Ethernet Controller */
6337 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), 6329 PCI_DEVICE(0x10DE, 0x0763),
6338 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6330 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6339 }, 6331 },
6340 { /* MCP79 Ethernet Controller */ 6332 { /* MCP79 Ethernet Controller */
6341 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 6333 PCI_DEVICE(0x10DE, 0x0AB0),
6342 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6334 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6343 }, 6335 },
6344 { /* MCP79 Ethernet Controller */ 6336 { /* MCP79 Ethernet Controller */
6345 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 6337 PCI_DEVICE(0x10DE, 0x0AB1),
6346 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6338 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6347 }, 6339 },
6348 { /* MCP79 Ethernet Controller */ 6340 { /* MCP79 Ethernet Controller */
6349 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 6341 PCI_DEVICE(0x10DE, 0x0AB2),
6350 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6342 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6351 }, 6343 },
6352 { /* MCP79 Ethernet Controller */ 6344 { /* MCP79 Ethernet Controller */
6353 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 6345 PCI_DEVICE(0x10DE, 0x0AB3),
6354 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6346 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6347 },
6348 { /* MCP89 Ethernet Controller */
6349 PCI_DEVICE(0x10DE, 0x0D7D),
6350 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6355 }, 6351 },
6356 {0,}, 6352 {0,},
6357}; 6353};
@@ -6390,6 +6386,8 @@ module_param(dma_64bit, int, 0);
6390MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); 6386MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6391module_param(phy_cross, int, 0); 6387module_param(phy_cross, int, 0);
6392MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0."); 6388MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6389module_param(phy_power_down, int, 0);
6390MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6393 6391
6394MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); 6392MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6395MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); 6393MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 12:56:38 -0500