diff options
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r-- | drivers/net/forcedeth.c | 51 |
1 files changed, 39 insertions, 12 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 037d870712ff..11b8f1b43dd5 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
@@ -240,10 +240,12 @@ enum { | |||
240 | #define NVREG_RNDSEED_FORCE2 0x2d00 | 240 | #define NVREG_RNDSEED_FORCE2 0x2d00 |
241 | #define NVREG_RNDSEED_FORCE3 0x7400 | 241 | #define NVREG_RNDSEED_FORCE3 0x7400 |
242 | 242 | ||
243 | NvRegUnknownSetupReg1 = 0xA0, | 243 | NvRegTxDeferral = 0xA0, |
244 | #define NVREG_UNKSETUP1_VAL 0x16070f | 244 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
245 | NvRegUnknownSetupReg2 = 0xA4, | 245 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f |
246 | #define NVREG_UNKSETUP2_VAL 0x16 | 246 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f |
247 | NvRegRxDeferral = 0xA4, | ||
248 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | ||
247 | NvRegMacAddrA = 0xA8, | 249 | NvRegMacAddrA = 0xA8, |
248 | NvRegMacAddrB = 0xAC, | 250 | NvRegMacAddrB = 0xAC, |
249 | NvRegMulticastAddrA = 0xB0, | 251 | NvRegMulticastAddrA = 0xB0, |
@@ -269,8 +271,10 @@ enum { | |||
269 | #define NVREG_LINKSPEED_MASK (0xFFF) | 271 | #define NVREG_LINKSPEED_MASK (0xFFF) |
270 | NvRegUnknownSetupReg5 = 0x130, | 272 | NvRegUnknownSetupReg5 = 0x130, |
271 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | 273 | #define NVREG_UNKSETUP5_BIT31 (1<<31) |
272 | NvRegUnknownSetupReg3 = 0x13c, | 274 | NvRegTxWatermark = 0x13c, |
273 | #define NVREG_UNKSETUP3_VAL1 0x200010 | 275 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 |
276 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | ||
277 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | ||
274 | NvRegTxRxControl = 0x144, | 278 | NvRegTxRxControl = 0x144, |
275 | #define NVREG_TXRXCTL_KICK 0x0001 | 279 | #define NVREG_TXRXCTL_KICK 0x0001 |
276 | #define NVREG_TXRXCTL_BIT1 0x0002 | 280 | #define NVREG_TXRXCTL_BIT1 0x0002 |
@@ -658,7 +662,7 @@ static const struct register_test nv_registers_test[] = { | |||
658 | { NvRegMisc1, 0x03c }, | 662 | { NvRegMisc1, 0x03c }, |
659 | { NvRegOffloadConfig, 0x03ff }, | 663 | { NvRegOffloadConfig, 0x03ff }, |
660 | { NvRegMulticastAddrA, 0xffffffff }, | 664 | { NvRegMulticastAddrA, 0xffffffff }, |
661 | { NvRegUnknownSetupReg3, 0x0ff }, | 665 | { NvRegTxWatermark, 0x0ff }, |
662 | { NvRegWakeUpFlags, 0x07777 }, | 666 | { NvRegWakeUpFlags, 0x07777 }, |
663 | { 0,0 } | 667 | { 0,0 } |
664 | }; | 668 | }; |
@@ -1495,7 +1499,7 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
1495 | np->tx_skbuff[nr] = skb; | 1499 | np->tx_skbuff[nr] = skb; |
1496 | 1500 | ||
1497 | #ifdef NETIF_F_TSO | 1501 | #ifdef NETIF_F_TSO |
1498 | if (skb_shinfo(skb)->gso_size) | 1502 | if (skb_is_gso(skb)) |
1499 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | 1503 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
1500 | else | 1504 | else |
1501 | #endif | 1505 | #endif |
@@ -2127,7 +2131,7 @@ static int nv_update_linkspeed(struct net_device *dev) | |||
2127 | int newdup = np->duplex; | 2131 | int newdup = np->duplex; |
2128 | int mii_status; | 2132 | int mii_status; |
2129 | int retval = 0; | 2133 | int retval = 0; |
2130 | u32 control_1000, status_1000, phyreg, pause_flags; | 2134 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
2131 | 2135 | ||
2132 | /* BMSR_LSTATUS is latched, read it twice: | 2136 | /* BMSR_LSTATUS is latched, read it twice: |
2133 | * we want the current value. | 2137 | * we want the current value. |
@@ -2245,6 +2249,26 @@ set_speed: | |||
2245 | phyreg |= PHY_1000; | 2249 | phyreg |= PHY_1000; |
2246 | writel(phyreg, base + NvRegPhyInterface); | 2250 | writel(phyreg, base + NvRegPhyInterface); |
2247 | 2251 | ||
2252 | if (phyreg & PHY_RGMII) { | ||
2253 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | ||
2254 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; | ||
2255 | else | ||
2256 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | ||
2257 | } else { | ||
2258 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | ||
2259 | } | ||
2260 | writel(txreg, base + NvRegTxDeferral); | ||
2261 | |||
2262 | if (np->desc_ver == DESC_VER_1) { | ||
2263 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | ||
2264 | } else { | ||
2265 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | ||
2266 | txreg = NVREG_TX_WM_DESC2_3_1000; | ||
2267 | else | ||
2268 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | ||
2269 | } | ||
2270 | writel(txreg, base + NvRegTxWatermark); | ||
2271 | |||
2248 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), | 2272 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
2249 | base + NvRegMisc1); | 2273 | base + NvRegMisc1); |
2250 | pci_push(base); | 2274 | pci_push(base); |
@@ -3910,7 +3934,10 @@ static int nv_open(struct net_device *dev) | |||
3910 | 3934 | ||
3911 | /* 5) continue setup */ | 3935 | /* 5) continue setup */ |
3912 | writel(np->linkspeed, base + NvRegLinkSpeed); | 3936 | writel(np->linkspeed, base + NvRegLinkSpeed); |
3913 | writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); | 3937 | if (np->desc_ver == DESC_VER_1) |
3938 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | ||
3939 | else | ||
3940 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | ||
3914 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | 3941 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
3915 | writel(np->vlanctl_bits, base + NvRegVlanControl); | 3942 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
3916 | pci_push(base); | 3943 | pci_push(base); |
@@ -3932,8 +3959,8 @@ static int nv_open(struct net_device *dev) | |||
3932 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | 3959 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); |
3933 | get_random_bytes(&i, sizeof(i)); | 3960 | get_random_bytes(&i, sizeof(i)); |
3934 | writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); | 3961 | writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); |
3935 | writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); | 3962 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
3936 | writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); | 3963 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); |
3937 | if (poll_interval == -1) { | 3964 | if (poll_interval == -1) { |
3938 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | 3965 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) |
3939 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | 3966 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); |